CN1485726A - Process for reducing circulation frequency in fixed point division components accomplished by SRT algorithm - Google Patents
Process for reducing circulation frequency in fixed point division components accomplished by SRT algorithm Download PDFInfo
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- CN1485726A CN1485726A CNA031548415A CN03154841A CN1485726A CN 1485726 A CN1485726 A CN 1485726A CN A031548415 A CNA031548415 A CN A031548415A CN 03154841 A CN03154841 A CN 03154841A CN 1485726 A CN1485726 A CN 1485726A
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Abstract
The invention relates to the field of microprocessor architecture, which provides a new pattern handling method for accelerating the computational speed for the fixed point division component and lowering the power consumption by the component simultaneously, wherein the handling method can reduce the circulation frequency of the fixed point division component accomplished by the SRT algorithm, before the circulating computation of the fixed point division begins, the number of the fixed point division circulation is determined through the differential value between the numbers of 0 (1 if the number is negative) in front of the operation number joining the fixed point division.
Description
Technical field
The present invention relates to the micro-processor architecture technical field, the fixed point division parts that the SRT algorithm is realized reduce the disposal route of fixed point division parts in method, the especially microprocessor of cycle index.
Background technology
Fixed point division is one of extremely important functional part of processor (comprising some DSP and embedded chip), and its performance is an importance that influences processor performance.The implementation method of fixed point division is many, the field that the present invention relates to mainly is to use SRT algorithm (reference literature M.D.Ercegovac and T.Lang at all, Divi sion and Square Root:DigitRecurrence Algorithms and Implementations, Kluwer AcademicPublishers, Norwell, Mass., the 1994.) fixed point division of Shi Xianing.The SRT algorithm is a kind of digital loop algorithm, is the method that adopts subtraction, and each circulation obtains the fixedly figure place in the end product.For example adopt the fixed point division parts of the SRT algorithm of base 4, each circulation obtains 2 results, needs 16 circulations just can obtain end product for the fixed point division of single precision at least; And for the fixed point division of double precision, needing at least to circulate 32 times just can obtain end product.
Yet, in the computing of reality, participate in two operands of fixed point divisions at all, have very that major part has following characteristics, promptly the numeric ratio that differs of dividend front 0 number and divisor front 0 number is less.For example to the fixed point division of a no symbol single precision, dividend is 19, and divisor is that 5 their binary representations are respectively as follows:
Dividend: 00,000,000 00,000,000 00,000,000 00010011;
Divisor: 00,000,000 00,000,000 00,000,000 00000101
The number of dividend front 0 is 27 so, and divisor is 29, and that divisor is only bigger by 2 than dividend, and the fixed point division parts of general use SRT algorithm can not utilize these characteristics of two operands to improve the division performance.And has only reference literature (Huffman; William A " Mechanism andmethod for integer divide involving pre-alignment of the divisorrelative to the dividend " Appl.No:167006) method in is not also just at recovering the remainder algorithm, and making full use of operand front figure place is that zero number reduces cycle index.The present invention is applicable to all SRT algorithms, does not need to utilize reference literature (Huffman; William A " Mechani sm and method for integer divide involving pre-alignmentof the divisor relative to the dividend " Appl.No:167006) the alignment operation number in, but be that zero number directly draws needs round-robin number of times according to two operand front figure places that participate in division.
Summary of the invention
The object of the present invention is to provide a kind of fixed point division parts that the SRT algorithm is realized to reduce the method for cycle index.
For implementation method of the present invention is described, we are only with the no symbol division of fixed point, base 2
nSRT be example.
Because be the no symbol division of fixed point, so operand all is a positive number; What adopt is base 2
nThe SRT algorithm, so each circulation produces n position result.The present invention only need determine fixed point division round-robin number of times by the difference of calculating two operand front zero numbers.Two operands that for example participate in to calculate, divisor opa, dividend are opb, and divisor opa front figure place is that 0 number is a, and dividend opb front figure place is that 0 number is b, and then cycle index is
If a＜b then illustrates dividend less than divisor, the value that directly obtains discussing is 0, and the value of remainder is a dividend.
Technical scheme of the present invention:
A kind of fixed point division parts that the SRT algorithm is realized reduce the method for cycle index: before beginning fixed point division cycle calculations, determine to finish fixed point division round-robin number of times according to number (if negative then is 1 the number) difference of two operand fronts 0 of participating in fixed point division.Reduce cycle index thereby reach, accelerate the purpose that fixed point division speed reduces power consumption simultaneously.
The fixed point division parts that the present invention can make the SRT algorithm realize reduce the method for cycle index, suppose that two numbers of participation division all are positive number, and its step is as follows:
1) according to two operand of fixed point division, calculate earlier each operand front figure place and be 0 number, we might as well suppose that divisor opa front figure place is that 0 number is a, and dividend opb front figure place is that 0 number is b, according to above-mentioned principle, calculating needs the round-robin number of times to be
If a＜b wherein, the value that then directly obtains discussing is 0, and the value of remainder is the value of dividend; Then divisor is moved to the left a position, and dividend is moved to the left
The position, (value of the divisor foremost figure place after promptly moving is 1) obtains the initial value that the SRT algorithm is carried out preceding divisor and dividend like this;
2) calculate each round-robin result according to the SRT algorithm;
3) after drawing last merchant's result, remainder is adjusted, because divisor was moved to the left a position, identical figure place, i.e. a position so last remainder will move right according to the figure place that divisor moves before beginning SRT algorithm.
Embodiment
Below, we will be with 8 signless fixed point divisions, and the SRT algorithm of base 4 is an example, further specifies method of the present invention.If two operands are respectively dividend 7, divisor 4, its binary representation is as follows:
Dividend: opb=0000,0111 (7)
Divisor: opa=0000,0100 (4)
The first step:
Calculate dividend respectively, divisor front figure place is 0 number, obtains divisor, and the number of dividend front figure place 0 all is 5.Because the number difference of two operand fronts 0 is 0, so and the SRT algorithm that adopts base 4 according to principle of the present invention, it is 1 time that whole calculating needs the round-robin number of times.Can obtain simultaneously the preceding initial value of operand circulation is: opb=000.1110,0000, opa=000.1000,0000.
Second step:
Use the SRT algorithm computation of base 4, obtaining the merchant is 0000,0001; Remainder is 0110,000.
The 3rd step:
Remainder is adjusted, and remainder moves right 5, and getting to the end, remainder is 0000,0011;
And implementation method is identical with no symbol fixed point division for the symbol fixed point division is arranged, only when having symbol fixed point division and operand to be the situation of negative, the number that calculating operation is counted front zero is to realize by the number that calculating operation is counted front 1.
Relatively the present invention and the generally disposal route of fixed point division parts, we obviously as can be seen originally
Invention has following advantage:
1) accelerates computing velocity; General fixed point division adopts the method for fixed cycles number of times, can not make full use of the computing velocity that the operand characteristic is accelerated division like this.In actual conditions, the number of two operand fronts 0 that the participation fixed point division calculates is many, and two operand front 0 number differences are smaller.Use method of the present invention just can shorten the computing velocity of these operands greatly, all need the cycle index of fixing and do not treat any number as the fixed point division method.
2) reduce power consumption; Because the quickening computing velocity, having reduced needs cycle index, so can reduce the power consumption of fixed point division parts simultaneously.
The fixed point division parts that the SRT algorithm is realized of the present invention reduce the disposal route of cycle index, before beginning fixed point division cycle calculations, determine to finish fixed point division round-robin number of times according to number (if negative then is 1 the number) difference of two operand fronts 0 of participating in fixed point division.Reduce cycle index thereby reach, accelerate the purpose that fixed point division speed reduces power consumption simultaneously.The computing velocity of accelerating the fixed point division parts for contemporary processor reduces this parts power consumption simultaneously provides a kind of new-type processing method.
The present invention is applied in " Godson " 2 processors.
Claims (2)
1, a kind of fixed point division parts that the SRT algorithm is realized reduce the disposal route of cycle index, it is characterized in that, before beginning fixed point division cycle calculations, number according to two operand fronts 0 of participating in fixed point division, if negative then is 1 number, its difference determines to finish fixed point division round-robin number of times, reduces cycle index thereby reach, and accelerates fixed point division speed and reduces power consumption simultaneously.
2, a kind of fixed point division parts that the SRT algorithm is realized reduce the disposal route of cycle index, suppose that two numbers of participation division all are positive number, and its step is as follows:
1) according to two operands of fixed point division, calculate each operand front figure place earlier and be 0 number, suppose that divisor opa front figure place is that 0 number is a, dividend opb front figure place is that 0 number is b, calculating needs the round-robin number of times to be
If a＜b wherein, the value that then directly obtains discussing is 0, and the value of remainder is the value of dividend; Then divisor is moved to the left a position, and dividend is moved to the left
The position obtains the initial value that the SRT algorithm is carried out preceding divisor and dividend;
2) calculate each round-robin result according to the SRT algorithm;
3) after drawing last merchant's result, remainder is adjusted, because divisor was moved to the left a position, identical figure place, i.e. a position so last remainder will move right according to the figure place that divisor moves before beginning SRT algorithm.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA031548415A CN1485726A (en) | 2003-08-20 | 2003-08-20 | Process for reducing circulation frequency in fixed point division components accomplished by SRT algorithm |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984522A (en) * | 2014-05-27 | 2014-08-13 | 中国人民解放军国防科学技术大学 | Method for achieving fixed point and floating point mixed division in general-purpose digital signal processor (GPDSP) |
-
2003
- 2003-08-20 CN CNA031548415A patent/CN1485726A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103984522A (en) * | 2014-05-27 | 2014-08-13 | 中国人民解放军国防科学技术大学 | Method for achieving fixed point and floating point mixed division in general-purpose digital signal processor (GPDSP) |
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