CN1484280A - Low resistance silicon substrate containing oxidized porous silicon and preparation thereof - Google Patents
Low resistance silicon substrate containing oxidized porous silicon and preparation thereof Download PDFInfo
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- CN1484280A CN1484280A CNA031422055A CN03142205A CN1484280A CN 1484280 A CN1484280 A CN 1484280A CN A031422055 A CNA031422055 A CN A031422055A CN 03142205 A CN03142205 A CN 03142205A CN 1484280 A CN1484280 A CN 1484280A
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Abstract
This invention discloses a low resistance silicon substrate containing oxidation porous silicon suitable for manufacturing RF circuit, in which, one surface of the substrate is composed of zone 1 and 2 or even 3, zone1 is a low resistance one, zone2 and 3 are zones containing oxidation porous silicon, zone1 suits for making active units and zone 2 and 3 for passive ones reaching the aim of making IC of RF, microwave, millimetric wave bands on low resistance Si substrates. Preparation of the said substrate includes four steps: taking low resistance Si as the raw material, metal or silicon nitride as the mask to form porous Si in a selected zone to be oxidized, coated with polyimide, to be filmed and iminized, meeting the needs of different RF circuits to substrates and reducing the impedance loss and conductor loss of the substrate.
Description
Technical field
The present invention relates to be suitable for make the preparation of the low-resistance silicon substrate of radio circuit.Radio circuit refers to work in components and parts, assembly and combinational circuit thereof and microelectron-mechanical (MEMS) system of radio frequency, microwave and millimeter wave band, belongs to the technical field of microelectronics solid state device and manufacturing thereof.
Background technology
Develop rapidly along with communication, particularly wireless mobile telecommunication technology, urgent need is with RF active device and passive device, as co-plane waveguide, capacitor, inductor, filter, amplifier, phase shifter and antenna etc., be integrated on the one-piece substrate with conventional IC circuit compatibility.Resistivity is that the low-resistance silicon of 1～30 Ω cm is cheap, is suitable for as the substrate of making ULSIC and ASIC integrated circuit.But low-resistance silicon is not suitable as the substrate of radio circuit.As radio circuit being manufactured on the low-resistance silicon substrate, the latter will introduce excessive insertion loss and capacitance coupling effect for the former so, greatly reduce the former operating efficiency and quality.Because different active device, passive devices has different demands to the impedance of substrate with dielectric constant, on same substrate, be difficult to satisfy this demand again.Here it is does not adopt the low-resistance silicon substrate to make the reason of monolithic integrated circuits (MMIC) such as radio frequency, microwave and millimeter wave band so far.
Summary of the invention
Low-resistance silicon can form porous silicon (PS) on its surface through after the anodic attack, again through peroxidating, can be oxidized to oxidized porous silicon (OPS) to porous silicon.OPS is spongiform porous mass, and the resistivity of OPS is relevant with the vesicularity of OPS, aperture and thickness, can reach 10
6The order of magnitude that Ω cm is above.As monolithic integrated circuits (MMIC) such as radio frequency, microwave and millimeter wave band are manufactured on the OPS, the latter will reduce than the insertion loss and the capacitance coupling effect of low-resistance silicon substrate greatly for insertion loss and the capacitance coupling effect that the former introduces so.In addition, the dielectric constant of OPS is also relevant with vesicularity, aperture and the thickness of OPS.Because the relative dielectric constant of air, silicon dioxide and low-resistance silicon is respectively 1,3.4 and 11.9, so control OPS manufacturing procedure, with regard to vesicularity, aperture and the thickness of may command OPS, thereby obtain dielectric constant between 1～11.9 OPS, to satisfy of the requirement of different radio frequency circuit to substrate.In sum, OPS is suitable for doing to make the substrate of monolithic integrated circuits (MMIC) such as radio frequency, microwave and millimeter wave band.
The technical problem to be solved in the present invention is to propose a kind of low-resistance silicon substrate that contains oxidized porous silicon, it is characterized in that, a surface of this substrate is made up of zone 1 and zone 2 even regional 3, zone 1 is the low-resistance silicon area, zone 2 and the 3 OPS zones that are formed on the low-resistance silicon substrate, zone, according to desired impedance of circuit and dielectric constant values on zone 2 and the zone 3, can select vesicularity, aperture and the thickness of different OPS to satisfy its requirement.Be coated with polyimide layer 4 on zone 1, zone 2 and the zone 3.On zone 1, be suitable for making active device, on zone 2, zone 3 and the polyimide layer 4 above them thereof, be suitable for making passive device, reach the purpose of on low-resistance silicon, making monolithic integrated circuits (MMIC) such as radio frequency, microwave and millimeter wave band thus.
Another technical problem that the present invention will solve is to release a kind of preparation that contains the low-resistance silicon substrate of oxidized porous silicon.The present invention is by the following technical solutions: with low-resistance silicon is raw material, does mask with metal or silicon nitride, selects the zone to form porous silicon, oxidation, and coating polyimide, film forming, four steps of imidization, raw material is processed into finished product, promptly contain the low-resistance silicon substrate of oxidized porous silicon.
Now be described with reference to the accompanying drawings the preparation of substrate of the present invention.Above-described a kind of preparation that contains the low-resistance silicon substrate of oxidized porous silicon is N or the P type body silicon of 300 μ m with thickness.Production method can adopt full wafer as required or select to make PS.Can also add the polyimide film that is coated with one deck 5～10um on its surface.The dielectric constant of polyimides is 4, and its levelability is relatively good.Not only can improve porous silicon, oxidized porous silicon surface, can also repeat, stably make the micron order lines thereon, and can not increase the loss of substrate.
Operating procedure:
The first step forms porous silicon
1). conventional cleaning silicon chip
2). adopt microelectronic LPCVD technology growth one deck silicon nitride mask or form the CrAu mask at the low-resistance silicon face at the low-resistance silicon face with the evaporation coating technology
3). coating photoresist, preceding baking, the window of photoetching, the formation porous silicon that develops
4). remove photomask surface glue with acetone, alcohol and deionized water respectively
5). the silicon chip single face is put into 5～40%HF solution, and current density is 5～30mA/cm
2, the time is 0.5～3 hour
6). add reversed electric field after 2～10 minutes, take out silicon chip
7). after putting into deionized water immersion, cleaning, use dehydration of alcohol
8). remove CrAu or silicon nitride mask
As make passive component substrate, 2), 3), 4) and the step omits;
The second step oxidation (see figure 2)
1). the silicon chip of the porous silicon of having grown, put into oxidation furnace, feed dried oxygen earlier, be warming up to 300 ℃, feed wet oxygen again
2). progressively be warmed up to oxidizing temperature (600～1180 ℃), temperature-rise period continues 4～10 hours
3). constant temperature wet oxidation 1～2 hour, dry oxidation 0.5～1 hour
4). continue to feed dried oxygen, be cooled to naturally below 200 ℃, slice, thin piece is taken out;
The 3rd step coating polyimide layer
1). the oxidized porous silicon sheet of cleaning is put into a conventional oven, rise to 200 ℃ from room temperature, the time is half an hour
2). utilize the rotating centrifugal coating technique, the polyimides glue of solids content 10-30% is uniformly coated on the surface of oxidized porous silicon substrate, rotating speed is 3000～4000rpm, and temperature is 20 ℃, and the coating time is 60 seconds
3). the substrate of imide layer is reunited in coating, put into 80 ℃ baking oven heating half an hour, continue to be warming up to 100 ℃, 45 minutes
4). be coated with the positive glue of photoetching, 4000 change, and 30 minutes, preceding baking 15min, photoetching is developed, and removes unwanted polyimides
5). remove the positive glue of photoetching with acetone, alcohol and deionized water respectively;
The 4th step imidization
1). will go up three substrates finished of step and put into baking oven and heat-treat: ℃ half an hour → 200, ℃ half an hour → 175, ℃ half an hour → 150,100 ℃ of half an hour → 125 ℃ half an hour
2). feed nitrogen, continue to be warming up to 300 ℃, the time is 1～2 hour, makes the polyimides imidization, and so far, the low-resistance silicon substrate preparation that contains oxidized porous silicon finishes.
Outstanding advantage of the present invention is:
1). by control OPS manufacturing procedure, the aperture of scalable PS/OPS, thickness and vesicularity, its dielectric constant can be adjusted near 1 from 11.9;
2). can greatly reduce the impedance loss and the conductor losses of the substrate of low-resistance silicon;
3). by select making OPS, can obviously reduce the parasitic capacitance of active device, alleviated microwave active device parasitic capacitance and dead resistance this to contradiction, effectively improve the operating frequency of active device;
4). can so that passive component and active components and parts be integrated on a slice low-resistance silicon substrate.
Description of drawings
Fig. 1 is on low-resistance silicon substrate 1, selects to form the OPS schematic diagram, and (a) figure evaporates CrAu4 on low-resistance silicon, behind the resist coating 5, leaves the window schematic diagram that forms porous silicon; (b) figure is a low-resistance silicon generalized section of having finished oxidized porous silicon 2; (c) the low-resistance silicon generalized section that contains Local Porous silicon behind the figure foot removal mask layer.
Fig. 2 is the low-resistance silicon generalized section that contains selective oxidation porous silicon 6 after peroxidating.
After Fig. 3 is surface applied polyimides 7, the low-resistance silicon generalized section of selective oxidation porous silicon; (a) figure is illustrated in whole substrate surface coating one deck polyimides; (b) figure is again a coating photoresist 5 on polyimides, and (c) figure is after scribe line is left in photoetching, the low-resistance silicon generalized section of selective oxidation porous silicon.
Fig. 4 is through after the imidization, the low-resistance silicon generalized section of selective oxidation porous silicon.
Fig. 5 is the implementation step schematic diagram of embodiment 2.
Fig. 6 is the implementation step schematic diagram of embodiment 3.
Fig. 7 is the implementation step schematic diagram of embodiment 4.
Embodiment
Embodiment 1, on P type low-resistance silicon substrate area 1, selects to make porous silicon zone 2.
At first get growth one deck silicon nitride or evaporation CrAu mask on a low-resistance (1～30 Ω .cm) the Si substrate, use conventional photoetching method, the coating photoresist, the window of photoetching, the formation porous silicon that develops is seen Fig. 1 (a).Remove photoresist, after the cleaning, this sheet single face is put into 40%HF solution, current density is 5～10mA/cm
2, the time can 20 minutes～3 hours, and dielectric constant is a little low if desired, and substrate loss is a little bit smaller, the desirable longer reaction time.Then, form Local Porous silicon thus, see Fig. 1 (b).Remove the CrAu mask with iodine/KI and hydrochloric acid, see Fig. 1 (c).The low resistance silicon chip of the porous silicon of having grown, put into oxidation furnace, feed dried oxygen earlier, be warming up to 300 ℃, feed wet oxygen again, progressively be warmed up to oxidizing temperature (600～1180 ℃), temperature-rise period is slow, continue 4～10 hours, constant temperature wet oxidation 1～2 hour, dry oxidation 0.5～1 hour continues to feed dried oxygen, naturally be cooled to below 200 ℃, on low-resistance silicon, form the selective oxidation porous silicon.See Fig. 2.Above-mentioned slice, thin piece is put into baking oven, take out after being warming up to 200 ℃, coating polyimide, rotating speed are 3000～4000 to change, and the time is 1 minute.See Fig. 3 (a).The slice, thin piece of coating polyimide layer is put into baking oven, is warming up to 80 ℃ earlier, half an hour follow-up continuous be warming up to 100 ℃, 45 minutes after, take out slice, thin piece, the positive glue of coating photoetching, photoetching is developed, and removes the polyimide layer on the scribe line.See Fig. 3 (b).Remove photoresist, progressively be warming up to 200 ℃.See Fig. 3 (c).Feed nitrogen, progressively be warming up to 300 ℃, constant temperature 1～2 hour is finished imidization.See Fig. 4.So far finish whole technical process.
At first on the low-resistance silicon substrate that contains zone 1 and zone 2, see Fig. 5 (a).Behind the evaporation one deck CrAu, the coating photoresist, baking is 15 minutes before 80 ℃, and the window of desiring porous silicon is left in photoetching, development, sees Fig. 5 (b).Remove photoresist, after the cleaning, this sheet single face is put into 40%HF solution, current density is 5～10mA/cm
2, the time is 2～3 hours, then, forms Local Porous silicon area 3 thus, sees Fig. 5 (c).Remove the CrAu mask, see Fig. 5 (d).The back is arranged with Fig. 2 among the embodiment, 3,4.Fig. 5 (e) carries out oxidation, Fig. 5 (f) coating polyimide layer, and Fig. 5 (g) is coated with positive glue, photoetching, development, leaves scribe line, and Fig. 5 (h) goes positive glue, imidization.So far finish whole technical process.
Embodiment 3, behind the method growth one deck N type low-resistance silicon 9 with extension on the P type low-resistance silicon substrate area 1, make zone 2 and zone 10 more thereon.Specific embodiment is seen Fig. 6.
At first on P type low-resistance silicon substrate,, see Fig. 6 (a) with the N type low-resistance silicon area 9 of 1～10 micron of method growth one deck of conventional vapour phase epitaxy, liquid phase epitaxy or molecular beam epitaxy, metal organic chemical vapor deposition.Evaporate one deck CrAu mask more thereon, behind the coating photoresist, photoetching development, corrosion CrAu leaves the zone 2 that needs to form porous silicon, sees Fig. 6 (b).After removing photoresist, apply photoresist again, photoetching, development, corrosion CrAu, leaving needs to form porous silicon zone 10, sees that Fig. 6 (c) cleans up slice, thin piece, puts into 1～40%HF solution, forms porous silicon zone 2 and zone 10, sees Fig. 6 (d).Add KI with iodine and remove CrAu, see Fig. 6 (e).This sheet is put into oxidation furnace, feed dried oxygen earlier, be warming up to 300 ℃, feed wet oxygen again, progressively be warmed up to oxidizing temperature (600～1000 ℃), temperature-rise period is slow, continues 4～10 hours, constant temperature wet oxidation 1～2 hour, dry oxidation 0.5～1 hour continues to feed dried oxygen, is cooled to naturally below 200 ℃, on low-resistance silicon, form the selective oxidation porous silicon, see Fig. 6 (f).So far finish whole technical process.
At first on the P type low-resistance silicon substrate area 1 of cleaning, the silica 11 of oxidation 1 micron thickness, gluing, photoetching, corrode silicon dioxide is left window, removes photoresist, cleaning, sees Fig. 7 (a).Method with conventional thermal diffusion expands phosphorus, forms n-quadrant 12, sees Fig. 7 (b).If adopt ion to inject the method that forms the n-quadrant, can omit first step oxidation.Evaporation CrAu mask on above-mentioned slice, thin piece, the coating photoresist, photoetching, development, corrosion CrAu leaves the zone 2 and the zone 10 that form porous silicon, sees Fig. 7 (c).Put into HF solution and form porous silicon, see Fig. 7 (d).Add KI with iodine and remove the CrAu protective layer, clean up, this sheet is put into oxidation furnace; feed dried oxygen earlier, be warming up to 300 ℃, feed wet oxygen again; progressively be warmed up to oxidizing temperature (600～1000 ℃); continue 4～10 hours, constant temperature wet oxidation 1～2 hour, dry oxidation 0.5～1 hour; continue to feed dried oxygen; naturally be cooled to below 200 ℃, on low-resistance silicon, form the selective oxidation porous silicon, see Fig. 7 (e).So far finish whole technical process.
Claims (2)
1. low-resistance silicon substrate that contains oxidized porous silicon is characterized in that: a surface of this substrate is made up of zone (1) and zone (2) even regional (3); Zone (1) is the low-resistance silicon area, and zone (2) and regional (3) are formed in and contain the oxidized porous silicon zone on the low-resistance silicon substrate; Go up desired impedance of circuit and dielectric constant values according to zone (2) and zone (3), can select the different vesicularity that contains oxidized porous silicon, aperture and thickness to satisfy its requirement; Be coated with polyimide layer (4) on zone (1), zone (2) and the zone (3).
2. a preparation method who contains the low-resistance silicon substrate of oxidized porous silicon comprises that with low-resistance silicon be raw material, does mask with metal or silicon nitride, selects the zone to form porous silicon, oxidation, and coating polyimide, is characterized in that concrete steps are as follows at film forming, four steps of imidization:
The first step forms porous silicon
1). conventional cleaning silicon chip
2). adopt microelectronic LPCVD technology growth one deck silicon nitride mask or form the CrAu mask at the low-resistance silicon face at the low-resistance silicon face with the evaporation coating technology
3). coating photoresist, preceding baking, the window of photoetching, the formation porous silicon that develops
4). remove photomask surface glue with acetone, alcohol and deionized water respectively
5). the silicon chip single face is put into 5～40%HF solution, and current density is 5～30mA/cm
2, the time is 0.5～3 hour
6). add reversed electric field after 2～10 minutes, take out silicon chip
7). after putting into deionized water immersion, cleaning, use dehydration of alcohol
8). remove CrAu or silicon nitride mask
As make passive component substrate, 2), 3), 4) and the step omits;
The second step oxidation
1). the silicon chip of the porous silicon of having grown, put into oxidation furnace, feed dried oxygen earlier, be warming up to 300 ℃, feed wet oxygen again
2). progressively be warmed up to 600～1180 ℃ of oxidizing temperatures, temperature-rise period continues 4～10 hours
3). constant temperature wet oxidation 1～2 hour, dry oxidation 0.5～1 hour
4). continue to feed dried oxygen, be cooled to naturally below 200 ℃, slice, thin piece is taken out;
The 3rd step coating polyimide layer
1). the oxidized porous silicon sheet of cleaning is put into a conventional oven, rise to 200 ℃ from room temperature, the time is half an hour
2). utilize the rotating centrifugal coating technique, the polyimides glue of solids content 10-30% is uniformly coated on the surface of oxidized porous silicon substrate, rotating speed is 3000～4000rpm, and temperature is 20 ℃, and the coating time is 60 seconds
3). the substrate of imide layer is reunited in coating, put into 80 ℃ baking oven heating half an hour, continue to be warming up to 100 ℃, 45 minutes
4). be coated with the positive glue of photoetching, 4000 change, and 30 minutes, preceding baking 15min, photoetching is developed, and removes unwanted PI
5). remove the positive glue of photoetching with acetone, alcohol and deionized water respectively;
The 4th step imidization
1). will go up three substrates finished of step and put into baking oven and heat-treat: ℃ half an hour → 200, ℃ half an hour → 175, ℃ half an hour → 150,100 ℃ of half an hour → 125 ℃ half an hour
2). feed nitrogen, continue to be warming up to 300 ℃, the time is 1～2 hour, makes the polyimides imidization, and so far, the low-resistance silicon substrate preparation that contains oxidized porous silicon finishes.
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| CN100404408C (en) * | 2005-11-16 | 2008-07-23 | 华东师范大学 | Non-refrigeration infrared detector heat insulation substrate preparation method |
| CN100440650C (en) * | 2007-03-21 | 2008-12-03 | 山东华光光电子有限公司 | Method for producing semiconductor laser mask |
| US7608470B2 (en) | 2005-06-28 | 2009-10-27 | Intel Corporation | Interconnection device including one or more embedded vias and method of producing the same |
| CN106044704A (en) * | 2016-06-27 | 2016-10-26 | 李岩 | Microelectronic mechanical system structure forming method |
| CN106548928A (en) * | 2015-09-17 | 2017-03-29 | 索泰克公司 | Structure and the method for manufacturing the structure for radio frequency applications |
| CN111699551A (en) * | 2019-01-15 | 2020-09-22 | 深圳市汇顶科技股份有限公司 | Chip and method for manufacturing chip |
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2003
- 2003-08-11 CN CN 03142205 patent/CN1226774C/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7608470B2 (en) | 2005-06-28 | 2009-10-27 | Intel Corporation | Interconnection device including one or more embedded vias and method of producing the same |
| CN1897265B (en) * | 2005-06-28 | 2010-12-08 | 英特尔公司 | Interconnection device including one or more embedded vias and method of producing the same |
| CN100404408C (en) * | 2005-11-16 | 2008-07-23 | 华东师范大学 | Non-refrigeration infrared detector heat insulation substrate preparation method |
| CN100440650C (en) * | 2007-03-21 | 2008-12-03 | 山东华光光电子有限公司 | Method for producing semiconductor laser mask |
| CN106548928A (en) * | 2015-09-17 | 2017-03-29 | 索泰克公司 | Structure and the method for manufacturing the structure for radio frequency applications |
| CN106548928B (en) * | 2015-09-17 | 2019-09-24 | 索泰克公司 | Method for the structural body and manufacture of the radio frequency applications structural body |
| CN106044704A (en) * | 2016-06-27 | 2016-10-26 | 李岩 | Microelectronic mechanical system structure forming method |
| CN106044704B (en) * | 2016-06-27 | 2017-09-29 | 李岩 | Micro Electronic Mechanical System structure forming method |
| CN111699551A (en) * | 2019-01-15 | 2020-09-22 | 深圳市汇顶科技股份有限公司 | Chip and method for manufacturing chip |
| CN111699551B (en) * | 2019-01-15 | 2023-10-17 | 深圳市汇顶科技股份有限公司 | Chip and method for manufacturing chip |
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