CN1482546A - Charging-free ultra-low power virtual dynamic random access memory - Google Patents
Charging-free ultra-low power virtual dynamic random access memory Download PDFInfo
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- CN1482546A CN1482546A CNA021320993A CN02132099A CN1482546A CN 1482546 A CN1482546 A CN 1482546A CN A021320993 A CNA021320993 A CN A021320993A CN 02132099 A CN02132099 A CN 02132099A CN 1482546 A CN1482546 A CN 1482546A
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Abstract
A charge-free type super low power virtual dynamic random access memory, comprising an interface control circuit, for producing a second reading control signal, a second write control signal or a second non-reading and non-writing control signal in accordance with a first reading operation signal, a first write control signal or a first non-reading and non-writing operation signal, and a static random access memory unit coupled with the interface control circuit, for performing a -1 bit reading operation based on the second reading control signal.
Description
Technical field
The present invention is meant a kind of charging-free ultra-low power virtual dynamic random access memory especially relevant for a kind of DRAM (Dynamic Random Access Memory).Box, global position system, consumer IC (TV, game machine on low-power product such as computing machine, mobile phone, PDA (Personal Digital Assistant), the teaching machine ...) etc.
Background technology
Present volatile ram can be divided into two big classes: static random access memory (SRAM) and DRAM (Dynamic Random Access Memory) (DRAM), static random access memory, its main framework is that four transistors or six transistors constitute 1 storage framework, and 1 of DRAM (Dynamic Random Access Memory) stores framework and then formed by electric capacity of a transistor AND gate.
The electric capacity of DRAM (Dynamic Random Access Memory) need constantly charge to keep the correct of data, and it is faster more stable that static random access memory is handled the internal memory processing speed than general dynamic random.So-called static meaning is meant that internal storage data can reside and must not charge at any time.Because this specific character, static random is handled internal memory and is used to do memory buffer usually.Generally speaking, static random is handled internal memory and is intended for memory buffer; And sound attitude random processing internal memory is the role who plays the part of primary memory.
Yet, when the manufacture of semiconductor technology entered nanometer technology, the internal memory eucaryotic cell structure that a transistor AND gate one electric capacity of existing DRAM (Dynamic Random Access Memory) (DRAM) is formed was about to face two test of the restriction of the limit of semiconductor subassembly physics and semicoductor capacitor processing procedure.For example, the memory cell structure of existing DRAM (Dynamic Random Access Memory), the electric leakage problem of its electric capacity often than transistor itself come serious, perhaps the big young pathbreaker of internal memory cell is subjected to the influence of semiconductor subassembly object characteristic.
Therefore, when manufacture of semiconductor marches toward nanometer technology, a kind ofly can solve the leakage current characteristic of electric capacity in the internal memory cell and the new internal memory cell framework of the semiconductor physics assembly limit becomes the technical task that needs to be resolved hurrily at present then.
Summary of the invention
In view of above problem, fundamental purpose of the present invention is to provide a kind of charging-free DRAM (Dynamic Random Access Memory), need not charge by the storage unit of static random access memory and can keep the characteristic of data, the storage unit that replaces DRAM (Dynamic Random Access Memory) need be charged keeping the characteristic of data, keeps the purpose of data to reach to exempt to charge.
Another object of the present invention is to provide a kind of ultra low power DRAM (Dynamic Random Access Memory), by the low power characteristic of the storage unit of static random access memory, to reduce the power consumption of internal memory cell unit.
Another purpose of the present invention is to provide a kind of virtual dynamic random access memory, the storage unit that replaces dynamic randon access with the storage unit of static random access memory, and by an interface control circuit, clock data with the control DRAM (Dynamic Random Access Memory), be converted to the clock data of control static random access memory, comprising three kinds of control models are arranged, be respectively " writing ", " reading " and " non-reading write with non-", make static random access memory can with the operating clock compatibility of DRAM (Dynamic Random Access Memory).
Therefore, for reaching above-mentioned purpose, charging-free ultra-low power virtual dynamic random access memory provided by the present invention, in order to carry out one 1 read operation according to the clock period of a control one DRAM (Dynamic Random Access Memory), one 1 write operation or non-reading and non-write operation, include an interface control circuit, with a static random access memory storage unit, wherein interface control circuit is to produce one in order to the clock period according to this DRAM (Dynamic Random Access Memory) to read control signal, one write control signal or non-reading and non-write control signal, the static random access memory storage unit is then carried out this read operation of 1 in order to read control signal according to this, carry out this write operation of 1 according to this write control signal, or this non-reading is carried out this non-reading and non-write operation with non-write control signal.
The present invention also provides a kind of charging-free ultra-low power virtual dynamic random access memory storage unit, in order to carry out one 1 read operation, one 1 write operation or non-reading and non-write operation according to the clock period of a control one DRAM (Dynamic Random Access Memory), wherein this clock period includes one first read operation signal, the first write operation signal or first non-the reading and non-write operation signal, and this storage unit includes:
One interface control circuit is in order to read producing one second with non-write operation signal and read control signal, one second write control signal or one second non-reading and non-write control signal according to this first read operation signal, this first write operation signal or this first are non-;
One data write control circuit is with this interface control circuit coupling;
One data read control circuit is with this interface control circuit coupling;
One non-reading and non-write control circuit is with this interface control circuit coupling; And
One static random access memory storage unit is with this data write control circuit, this data read control circuit and this non-reading and non-write control circuit coupling;
Wherein when this interface control circuit is exported this second write control signal, this data write control circuit of activation, make this static random access memory storage unit carry out this write operation of 1, when this interface control circuit is exported this second when reading control signal, this data read control circuit of activation, make and to carry out this read operation of 1 from this static random access memory storage unit, this is second non-when reading with non-write control signal when this interface control circuit is exported, this non-reading and non-write control circuit of activation makes this static random access memory storage unit become the disabled state.
The present invention utilizes advanced nanometer process technique to realize low-power and dynamical virtual dynamic random access memory eucaryotic cell structure.This eucaryotic cell structure is with six or four structures that transistor is 1 storage, utilize the design circuit technology that the DRAM of existing synchronously (Synchronous), double data transmission (Double Data Rate), double data transmission II (Double Data Rate II) is used in addition and convert reading and writing to, non-reading controlled among the present invention with six or four internal memory eucaryotic cell structures that transistor is 1 storage with non-three kinds of different control models writing, make the present invention can have DRAM (Dynamic Random Access Memory) now and use compatible.
Transistor among the present invention can be NMOS or PMOS, can based on the assembly of peripheral circuit benchmark, adjust the manufacture of semiconductor parameter, for example critical voltage is adjusted ion implantation (Vt.adjustmentimplant) etc., change six or four characteristics of transistor, meet various needs of different applications in the future, on manufacture of semiconductor, have compatible height, advantage easy to implement.Relatively the time, have more excellent low power consumption characteristic and the simple advantage of circuit design with the internal memory eucaryotic cell structure of existing DRAM (Dynamic Random Access Memory) and circuit design.
In addition, owing to be the semiconductor nano technology of employing and general logic product compatibility, be easy to and general logic product, for example digital signal processing (DSP) chip, drawing chip, microcontroller are incorporated on the same chip, meet very much the development in pluralism trend of integrated circuit (IC) " Silicon onChip " (SOC).
For making purpose of the present invention, structure, feature and function thereof there are further understanding, cooperate embodiment to be described in detail as follows now.
Description of drawings
Fig. 1 is the circuit block diagram for charging-free ultra-low power virtual dynamic random access memory storage unit of the present invention.
Embodiment
The DRAM (Dynamic Random Access Memory) specification that provides at present includes FPM (Fast Page Mode), EDO (Extended Data Out), SDRAM (Synchronous DRAM), DDR (DoubleData Rate), DDRII (Double Data Rate II), DRDRAM (Direct RambusDRAM) etc., and the development of these DRAM (Dynamic Random Access Memory) is in order to cooperate the computer system of friction speed and operational architecture.
According to memory storage unit provided by the present invention, be by an interface control circuit, with the clock period of the DRAM (Dynamic Random Access Memory) of above different size, convert three kinds of different operator schemes to, be respectively read operation, write operation and non-reading and non-write operation, control with six or four internal memory eucaryotic cell structures that transistor is 1 storage, in the hope of reaching low power consumption, high-effect, compatible high high density ultra-low power virtual dynamic random access memory.
Please refer to Fig. 1, be charging-free ultra-low power virtual dynamic random access memory of the present invention, as shown in the figure, include an interface control circuit 10, and a static random access memory storage unit 20.
Static random access memory storage unit 20 is one with four transistors memory storage unit structure that is 1 storage or be one with six transistors memory storage unit structure that is 1 storage, transistor is a MOS field school transistor, can be P type MOS field-effect pipe (PMOS) or N type MOS field-effect pipe (NMOS).
In general, the circuit of using except addressing in the static random access memory storage unit 20, be used for transmitting the circuit of data, other includes three groups of control circuits, as shown in the figure, be respectively data write control circuit 30, data read control circuit 40 and non-reading and non-write control circuit 50.When data will write static random-access memory storage unit 20, data write control circuit 30 will be enabled (enable), and data will be written in the static random-access memory storage unit 20 this moment.And will be in static random-access memory storage unit 20 during reading of data, data read control circuit 40 will be enabled, and make data to read out in static random-access memory storage unit 20.When static random-access memory storage unit 20 carries out reading of data or writes the operation of data, non-reading is not activation with the state of non-write control circuit 50, make the operation that static random-access memory storage unit 20 can read normally and write, if in the time of will making the operation that static random-access memory storage unit 20 do not read or write, then this moment, the non-state of reading with non-write control circuit 50 was activation.
The clock period of one DRAM (Dynamic Random Access Memory) includes the operation signal of a pair of memory storage unit, operation signal may include the first read operation signal, the first write operation signal or first non-the reading and non-write operation signal, the first read operation signal makes memory storage unit can carry out the read operation of one 1 bit data, the first write operation signal makes memory storage unit can carry out the write operation of one 1 bit data, and first non-the reading then makes memory storage unit maintain high impedance status and not carry out any read or write operation with non-write operation
When in interface control circuit 10 detects clock period of a synchronous DRAM (Dynamic Random Access Memory) (SDRAM), one first write operation signal being arranged, interface control circuit 10 can will produce one second write operation signal according to the first write operation signal, in order to the data write control circuit 30 of activation static random access memory storage unit 20, make and 1 bit data can be write in the static random access memory storage unit 20.At this moment non-reading is disabled with non-write control circuit 50, makes static random access memory storage unit 20 carry out write operation.
When in interface control circuit 10 detects clock period of a synchronous DRAM (Dynamic Random Access Memory) (SDRAM), one first read operation signal being arranged, interface control circuit 10 can will produce a second reading extract operation signal according to the first read operation signal, in order to the data read control circuit 40 of activation static random access memory storage unit 20, make and to read 1 bit data from static random access memory storage unit 20.Similarly, at this moment, non-reading is disabled with non-write control circuit 30, makes static random access memory storage unit 30 can carry out read operation.
In interface control circuit 10 detects clock period of a synchronous DRAM (Dynamic Random Access Memory) (SDRAM), have one first non-when reading with non-write operation signal, interface control circuit 10 can will produce one second non-reading and non-write operation signal with non-write operation signal according to first non-the reading, read and non-write control circuit 50 in order to the non-of activation static random access memory storage unit 20, make static random access memory storage unit 20 become the high impedance status of disabled, and do not carry out any operation.
Claims (17)
1, a kind of charging-free ultra-low power virtual dynamic random access memory, it is characterized in that in order to carry out one 1 read operation, one 1 write operation or non-reading and non-write operation according to the clock period of a control one DRAM (Dynamic Random Access Memory), wherein this clock period includes one first read operation signal, the first write operation signal or first non-the reading and non-write operation signal, and this internal memory includes:
One interface control circuit is in order to read producing one second with non-write operation signal and read control signal, one second write control signal or one second non-reading and non-write control signal according to this first read operation signal, this first write operation signal or this first are non-; And
One static random access memory storage unit, with the coupling of this interface control circuit, in order to second to read control signal and carry out this read operation of 1, carry out this write operation of 1 or this second non-reading is carried out this non-reading and non-write operation with non-write control signal according to this second write control signal according to this.
2, charging-free ultra-low power virtual dynamic random access memory as claimed in claim 1, it is characterized in that this static random access memory (sram) cell more includes a data write control circuit, in order to this 1 bit data is write in this static random access memory (sram) cell.
3, charging-free ultra-low power virtual dynamic random access memory as claimed in claim 1, it is characterized in that this static random access memory (sram) cell more includes a data read control circuit, in order to read this 1 bit data in this static random access memory (sram) cell certainly.
4, charging-free ultra-low power virtual dynamic random access memory as claimed in claim 1, it is characterized in that this static random access memory storage unit more includes non-reading and non-write control circuit, when this is non-when reading with non-write control circuit activation, make this static random access memory storage unit not carry out any operation.
5, charging-free ultra-low power virtual dynamic random access memory as claimed in claim 1 is characterized in that this static random access memory storage unit more includes six transistors.
6, charging-free ultra-low power virtual dynamic random access memory as claimed in claim 5 is characterized in that this transistor is MOS field Ying Tiguan.
7, charging-free ultra-low power virtual dynamic random access memory as claimed in claim 1 is characterized in that this static random access memory storage unit more includes four transistors.
8, charging-free ultra-low power virtual dynamic random access memory as claimed in claim 7 is characterized in that this transistor is the MOS field-effect pipe.
9, charging-free ultra-low power virtual dynamic random access memory as claimed in claim 1 is characterized in that this DRAM (Dynamic Random Access Memory) is to be selected from the combination of FPM DRAM (Dynamic Random Access Memory), EDO DRAM (Dynamic Random Access Memory), SDRAM (Synchronous dynamic random access memory) SDRAM, DDR DRAM (Dynamic Random Access Memory), DDRII DRAM (Dynamic Random Access Memory) and DRDRAM one of them.
10, a kind of charging-free ultra-low power virtual dynamic random access memory storage unit, it is characterized in that in order to carry out one 1 read operation, one 1 write operation or non-reading and non-write operation according to the clock period of a control one DRAM (Dynamic Random Access Memory), wherein this clock period includes one first read operation signal, the first write operation signal or first non-the reading and non-write operation signal, and this storage unit includes:
One interface control circuit is in order to read producing one second with non-write operation signal and read control signal, one second write control signal or one second non-reading and non-write control signal according to this first read operation signal, this first write operation signal or this first are non-;
One data write control circuit is with this interface control circuit coupling;
One data read control circuit is with this interface control circuit coupling;
One non-reading and non-write control circuit is with this interface control circuit coupling; And
One static random access memory storage unit is with this data write control circuit, this data read control circuit and this non-reading and non-write control circuit coupling;
Wherein when this interface control circuit is exported this second write control signal, this data write control circuit of activation, make this static random access memory storage unit carry out this write operation of 1, when this interface control circuit is exported this second when reading control signal, this data read control circuit of activation, make and to carry out this read operation of 1 from this static random access memory storage unit, this is second non-when reading with non-write control signal when this interface control circuit is exported, this non-reading and non-write control circuit of activation makes this static random access memory storage unit become the disabled state.
11, charging-free ultra-low power virtual dynamic random access memory storage unit as claimed in claim 10, when it is characterized in that this static random access memory storage unit is carried out this write operation of 1, this is non-read with non-write control circuit be the disabled state.
12, charging-free ultra-low power virtual dynamic random access memory storage unit as claimed in claim 10, when it is characterized in that this static random access memory storage unit is carried out this read operation of 1, this is non-read with non-write control circuit be the disabled state.
13, charging-free ultra-low power virtual dynamic random access memory storage unit as claimed in claim 10 is characterized in that this static random access memory storage unit more includes six transistors.
14, charging-free ultra-low power virtual dynamic random access memory storage unit as claimed in claim 13 is characterized in that this transistor is the MOS field-effect pipe.
15, charging-free ultra-low power virtual dynamic random access memory storage unit as claimed in claim 10 is characterized in that this static random access memory storage unit more includes four transistors.
16, charging-free ultra-low power virtual dynamic random access memory storage unit as claimed in claim 15 is characterized in that this transistor is the MOS field-effect pipe.
17, charging-free ultra-low power virtual dynamic random access memory storage unit as claimed in claim 10 is characterized in that this DRAM (Dynamic Random Access Memory) is selected from the combination of FPM DRAM (Dynamic Random Access Memory), EDO DRAM (Dynamic Random Access Memory), SDRAM (Synchronous dynamic random access memory) SDRAM, DDR DRAM (Dynamic Random Access Memory), DDRII DRAM (Dynamic Random Access Memory) and DRDRAM one of them.
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| CNA021320993A CN1482546A (en) | 2002-09-10 | 2002-09-10 | Charging-free ultra-low power virtual dynamic random access memory |
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| CNA021320993A CN1482546A (en) | 2002-09-10 | 2002-09-10 | Charging-free ultra-low power virtual dynamic random access memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103455441A (en) * | 2008-09-30 | 2013-12-18 | 英特尔公司 | Disabling cache portions during low voltage operations |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103455441A (en) * | 2008-09-30 | 2013-12-18 | 英特尔公司 | Disabling cache portions during low voltage operations |
| CN103455441B (en) * | 2008-09-30 | 2016-08-24 | 英特尔公司 | Disabling cache portions during low voltage operating |
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