CN1472654A - Management unit of flash memory device and method thereof - Google Patents
Management unit of flash memory device and method thereof Download PDFInfo
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- CN1472654A CN1472654A CNA031472737A CN03147273A CN1472654A CN 1472654 A CN1472654 A CN 1472654A CN A031472737 A CNA031472737 A CN A031472737A CN 03147273 A CN03147273 A CN 03147273A CN 1472654 A CN1472654 A CN 1472654A
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Abstract
According to address contrast storage of flash storage, the present invention searches out actual serial number of flash storage and to use it to produce address and operation instruction for LPC1.1 storage of the flash storage device by fetching out the initial set component value.
Description
Technical field
This invention relates to a kind of storage arrangement system of selection, particularly relates to a kind of device selecting method of flash memory of the LPC1.1 of support specification.
Background technology
In the modem computer systems, include various memory cell.Some memory cell is called as volatibility (volatile) storer, that is is after computer power supply is closed, and the data that are present in this type of storer disappear immediately.Some memory cell is called as non-volatile (non-volatile) storer, that is is after computer power supply is closed, and the data that are present in this type of storer can't disappear.
Volatile memory can be used to realize many functions, as dynamic ram (DynamicRandom Access Memory; DRAM), be meant synchronous dynamic access memory (SynchronousDRAM especially; SDRAM), generally be used for storing primary system program (main system program).Computing machine can load operating system in the main system memory (main system memory) earlier after start is finished.When user's opening application program, application program can be loaded into the main system memory from storage facilitiess such as hard disk, CDs, uses for further carrying out.Main system memory also can be the term of execution of program, is used for temporal data, configuration (configuration) or out of Memory.
Nonvolatile memory is used for storing executable code (executable code), and computing machine can be carried out in each start, these sign indicating numbers firmware (firmware) that is otherwise known as.For instance, most of computing machine all can have one group of executable program, is called basic input/output (Basic Input/OutputSystem; BIOs), be used for operating different types of I/O device, for example floppy disk, hard disk etc.These BIOS executable codes in nonvolatile memory, are called ROM (read-only memory) (Read OnlyMemory by permanent storage; ROM).
But in some cases, be stored in firmware on the ROM (read-only memory) because of strengthening or the needs of debug upgrade, the ROM (read-only memory) of some kind allows the content of its storage to be updated, for example Electrically Erasable Read Only Memory (Electrically Erasable Programmable Read Only Memory; EEPROM).Want to upgrade the firmware among the EEPROM, must erase original firmware earlier, again with in the complete write store of new firmware.
In the design of many motherboards and making, recently, on ROM (read-only memory) was selected, the most normal employing was the device that meets LPC 1.1 specifications, and therein, the also most important device of typical case is flash memory (FlashROM).Flash memory can be used to realize following function, for example, and as system bios, support two BIOS frameworks, support (SuSE) Linux OS or allow other application system storage data.
At present, have two kinds of flash memories to be selected to use by system designer, one is the LPC flash memory, its two Firmware HUB flash memory for Intel's formulation.These two kinds of flash memories have different access speeds and manufacturing cost separately.In addition, these two kinds of storeies can be gathered around with different LPC cycle (cycle) types and instruction (command) collection.Fig. 1 represents the LPC flash memory operating clock cycle synoptic diagram of known technology.Fig. 2 represents the Firmware HUB flash memory operating clock cycle synoptic diagram of known technology.Two flash memory operating clock cycles were all utilized LFRAME# to begin as identification one storage operation and finished signal.But at LAD[3: 0] 4 Bit data stream in, but can be at different LCLK clocks, use the data bits that does not wait, from LPC flash memory or Firmware HUB flash memory reading of data, or at different LCLK clocks, use the data bits that does not wait, write data in LPC flash memory or the Firmware HUB flash memory.
Because the motherboard deviser because of the Consideration difference, adopts different flash memories.So must there be the administrative unit of two kinds of different editions in the flash management unit (Host) in past simultaneously for adapting to these two kinds of flash memory types.So, how to design a device management unit and can support two kinds of flash memories just to become an important problem.Because flash memory is commonly used to as system bios, therefore, this device must be at start selftest (Power On Self Test again; POST) before the step, determine which kind of flash memory this motherboard supports.And, two kinds of flash memories are gathered around separately with different LPC cycles and instruction (command) collection, when the user is reading or write store when instruction, this device management unit must adapt to the variety classes flash memory, changes out suitable LPC1.1 memory operation instruction or unit address.
The Firmware HUB flash memory that in addition, can have a plurality of different memory sizes on the motherboard.At present, the method for head it off is that the flash memory of getting a max cap. is worked as substrate, and for example, 256K is used as all flash memories the spacing of address then with this max cap..Though the method simply mode is supported the flash memory of a plurality of different memory sizes, but many memory address spaces have been wasted, for instance, if an application system only needs flash memory capacity 64K, but the storage space that it disposed remains 256K, so the memory address space has produced the waste of 192K.So the Firmware HUB flash memory of a plurality of different memory sizes also must be supported in this device management unit under the situation of not wasting storage space.
Summary of the invention
In view of this, purpose of the present invention is for providing a kind of flash memory device administrative unit and method.Can be used for not changing under the situation of motherboard hardware design, support to meet the traditional LPC and the Firmware HUB flash memory of LPC1.1 specification simultaneously.This device management unit can determine which kind of flash memory this motherboard supports before start selftest step.And when the user is reading or write store when instruction, this device management unit and method can adapt to the variety classes flash memory, change out suitable LPC instruction and give various flash memories on the lpc bus.This device management unit and method can also be supported the Firmware HUB flash memory of a plurality of different memory sizes except changing out suitable LPC instruction.
Flash memory device administrative unit and method proposed by the invention, be memory operation instruction and the storage operation address section that central processing unit is transmitted, flash memory type setting value and the stored flash memory address contrast record of flash memory address contrast storer according to initial setting (strapping) assembly, produce LPC flash memory or Firmware HUB flash memory device address and operational order, can allow LPC Memory Management Unit (Host) support traditional LPC flash memory and Firmware HUB flash memory simultaneously.
According to above-mentioned purpose, the present invention at first is provided with an initial setting assembly on the device management unit, in order to setting flash memory type, and flash memory address contrast storer, in order to a plurality of flash memories address contrast record that stores.Afterwards, one flash memory instruction converting unit is set, memory operation instruction and storage operation address section that central processing unit is transmitted, according to initial setting assembly and the contrast record of flash memory address, carry out suitable conversion, produce LPC flash memory or Firmware HUB flash memory device address and operational order.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, hereinafter in conjunction with the accompanying drawings embodiment is described in detail as follows.
Fig. 1 represents the LPC flash memory operating clock cycle synoptic diagram of known technology;
Fig. 2 represents the Firmware HUB flash memory operating clock cycle synoptic diagram of known technology;
Fig. 3 represents the device synoptic diagram according to the flash memory device administrative unit and the method for first embodiment of the invention;
Fig. 4 represents the flash memory architecture synoptic diagram of first embodiment;
Fig. 5 represents the original flash memory address contrast record synoptic diagram of first embodiment;
Fig. 6 represents the flash memory address contrast record synoptic diagram after the start flash memory of first embodiment changes;
Fig. 7 represents the flash memory device selection synoptic diagram of first embodiment;
Fig. 8 represents according to the flash memory device administrative unit of first embodiment of the invention and the method flow diagram of method.
Description of reference numerals
300 flash memory selecting arrangements; 310～central processing unit;
321,322,323 flash memories; 301～flash memory address contrast storer;
302～initial setting (strapping) assembly; 303 flash memory instruction converting unit;
304～BIOS address setting unit; 41～traditional LPC flash memory (BIOS);
42～FWH flash memory (BIOS); 43～FWH flash memory (BIOS);
44～FWH flash memory (special I/O); 45～FWH flash memory (network card);
S61-S66～operation steps.
Embodiment
Fig. 3 is the device synoptic diagram of expression according to the flash memory device administrative unit and the method for first embodiment of the invention.Flash memory device administrative unit and method according to first embodiment of the invention are applicable to a flash memory device administrative unit 300, and it comprises flash memory address contrast storer 301, an initial setting (strapping) assembly 302, a flash memory instruction converting unit 303 and a BIOS address setting unit 304.
Flash memory address contrast storer 301 is in the flash memory device administrative unit 300, in order to store the contrast record of a plurality of flash memories address, this flash memory address contrast record is the record of a tables of data (table) structure, comprises storer numbering, storage address interval and a BIOS mark.This storer numbering must correspond to when carrying out the LPC storage operation, employed IDSEL numbering.Add a termination address and the storage address interval can be a start address, or a start address adds a memory size, be used for noting down the storage address section of the Firmware HUB flash memory of a plurality of different memory sizes.This storer reality as ROM or EEPROM, is forever noted down the flash memory relevant information that has on this motherboard as a nonvolatile memory.
Fig. 4 represents the flash memory architecture synoptic diagram of first embodiment, with regard to conceptive, flash memory device administrative unit 300 flash memory device that meets the LPC1.1 specification of managing has two kinds, one is traditional LPC flash memory 41, another is a Firmware HUB flash memory 42,43,44,45, only can select wherein a kind of flash memory as ROM (read-only memory) with regard to motherboard manufacturer when the actual design motherboard, but with regard to chipset manufacturer, two kinds of dissimilar flash memories preferably must be supported simultaneously in its flash management unit.Motherboard manufacturer then has only a traditional LPC flash memory 41 that is used for storing the BIOS data if select traditional LPC flash memory as ROM (read-only memory) on its motherboard.Otherwise motherboard manufacturer is if adopt Firmware HUB flash memory as ROM (read-only memory), then on its motherboard only to have a plurality of ROM (read-only memory) simultaneously, can be used for storing the data of BIOS, I/O or network card respectively.
Fig. 5 represents the original flash memory address contrast record synoptic diagram of first embodiment.If a motherboard has four Firmware HUB flash memories, then there are four flash memory records in the address contrast storer, be respectively project 0 to 3.First flash memory 42 is used for storing the BIOS data of start, its initial base address is FFF8_0000H, memory size is 512K, that is be that the address that this flash memory is configured to is that FFF8_0000H is to FFFF_FFFFH, in the framework of FirmwareHUB flash memory, the flash memory that start is used, its IDSEL is numbered 0.Second flash memory 43 also is used for storing the BIOS data of start, makes this motherboard can support two BIOS frameworks, and memory size also is 512K, the address that this flash memory was configured to be FFF0_0000H to FFF7_FFFFH, its IDSEL is numbered 1.The 3rd flash memory 44 is used for storing embedded Keyboard Control (Embedded KBC controller) data, support the corresponding matrix (keyboard mappingmatrix) of keyboard symbol, memory size is 256K, the address that this flash memory was configured to be FFEC_0000H to FFEF_FFFFH, its IDSEL is numbered 2.The 4th flash memory 45 is used for storage network card data, and memory size is 128K, the address that this flash memory was configured to be FFEA_0000H to FFEB_FFFFH, its IDSEL is numbered 3.
Initial setting (strapping) assembly 302 before the selftest step that is used to start shooting, is exported a flash memory setting signal, and the flash memory type that shows this motherboard support is LPC flash memory or Firmware HUB flash memory.This assembly is a nextport hardware component NextPort, can be an initial setting pin position (strapping pin), and the user can set this initial component for and support LPC flash memory or Firmware HUB flash memory.
Flash memory instruction converting unit 303, in order to storer is read or writes instruction, convert the LPC1.1 memory operation instruction that reads or write the LPC flash memory to, or convert the LPC1.1 memory operation instruction that reads or write Firmware HUB flash memory to.When central processing unit 310 was distributed a memory operation instruction and a storage operation address section and given flash memory instruction converting unit 303, the flash memory instruction converting unit at first must detect the flash memory type that initial setting assembly 302 sets.If this flash memory type is the LPC flash memory, then directly use this storage operation address section, produce a LPC flash memory operational order.If this flash memory type is a Firmware HUB flash memory, then according to the storage operation address section, to flash memory address contrast storer 301, retrieve the IDSEL numbering, afterwards, IDSEL numbering and storage operation address section according to above-mentioned produce a Firmware HUB flash memory device address and an operational order.At last, according to memory operation instruction and IDSEL numbering,, perhaps write data in flash memory 321,322 or 323 from flash memory 321,322 or 323 reading of data.
Fig. 7 represents the flash memory device selection synoptic diagram of first embodiment.Store contrast storer 301 in a flash memory address in the flash memory device administrative unit 300, store the record of the corresponding IDSEL numbering of a plurality of flash memory address sections.The flash memory that will remove to meet LPC1.1 when flash memory device administrative unit 300 reads or when writing data, shown in 710, can read the value of initial setting assembly 302, and the unit address that reads or write.If the initial setting components values is on, shown in 721, represent that then it selects traditional LPC flash memory 722, carry out data read-write operation.Drop among the Range0 if the initial setting components values is off and unit address value, shown in 731, then represent its selection Boot FWH flash memory 732, carry out data read-write operation.If the unit address value drops among Range1 or the Range2, shown in 741,751, then represent its selection FWH flash memory 742 or 752, carry out data read-write operation.
Fig. 6 represents the flash memory address contrast record synoptic diagram after the start flash memory of first embodiment changes.When computing machine was started shooting, discovery can't be read the BIOS data, or the BIOS data that read are wrong, can pass an error messages back and give BIOS address setting unit 304.After BIOS address setting unit 304 receives this error messages, can be according to the stored BIOS flag data of flash memory address contrast storer 301, remove to seek next available BIOS storer, and the IDSEL numbering of the IDSEL of the old BIOS flash memory that is used for starting shooting numbering and next available BIOS storer exchanged, and the BIOS mark of the old BIOS flash memory that is used for starting shooting (IDSEL# is 0) is made as-1, represent that this BIOS damages, the action of starting shooting again again.
Fig. 8 represents according to the flash memory device administrative unit of first embodiment of the invention and the method flow diagram of method.
At first, as step S81, by memory operation instruction and storage operation address section that 303 inputs of flash memory instruction converting unit are transmitted by central processing unit 310, this memory operation instruction might be that memory read instruction fetch or storer write instruction.Afterwards,, read flash memory type setting value, carry out the initial setting condition judgment,, judge whether the flash memory type of this motherboard is traditional LPC flash memory as step S83 from initial setting (strapping) assembly as step S82.If, carry out step S84, produce traditional LPC flash memory operational order, this LPC flash memory operational order might be that LPC flash memory reading command or LPC flash memory write instruction.If not, then carry out step S85, from the stored flash memory address contrast record of flash memory address contrast storer, retrieve the IDSEL numbering according to the storage operation address section.At last, as step S86, produce Firmware HUB flash memory device address and operational order, this FirmwareHUB flash memory operational order might be that Firmware HUB flash memory reading command or Firmware HUB flash memory write instruction.
Therefore, by flash memory device administrative unit provided by the present invention and method, memory operation instruction and storage operation address section that central processing unit is transmitted, flash memory type setting value and the stored flash memory address contrast record of flash memory address contrast storer according to initial setting (strapping) assembly, produce LPC flash memory or Firmware HUB flash memory device address and operational order, can allow Memory Management Unit (Host) support LPC flash memory and Firmware HUB flash memory simultaneously.And this invention can determine which kind of flash memory this motherboard supports before start selftest step, except that can satisfying the demand that miscellaneous equipment reads the ROM data, can also satisfy the demand that central processing unit reads the BIOS data.In addition, this invention can be supported the Firmware HUB flash memory of a plurality of different memory sizes under the situation of not wasting storage space.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, those of ordinary skill in the art, under the premise without departing from the spirit and scope of the present invention; can do some changes and retouching, so protection scope of the present invention is looked appended claim and is as the criterion.
Claims (12)
1. a flash memory device administrative unit is applicable to a computer system, comprising:
One flash memory address contrast storer, in order to store the contrast record of a plurality of flash memories address, this flash memory address contrast record comprises storer numbering, a storage address interval;
One initial setting assembly is in order to export a flash memory setting value, the flash memory type on the decision motherboard; And
One flash memory instruction converting unit is coupled to this flash memory address contrast storer and this initial setting assembly, in order to import a memory operation instruction and a storage operation address section, detect this flash memory setting value, according to this storage operation address section, by this flash memory address contrast storer, retrieve this storer numbering,, produce a LPC1.1 memory operation instruction according to this flash memory setting value and this storer numbering.
2. flash memory device administrative unit as claimed in claim 1, in this flash memory address contrast storer, this storer is numbered the IDSEL numbering.
3. flash memory device administrative unit as claimed in claim 1, in this flash memory address contrast storer, this storage operation address section comprises an initial address and a termination address.
4. flash memory device administrative unit as claimed in claim 1, in this flash memory address contrast storer, this storage operation address section comprises an initial address and a memory size.
5. flash memory device administrative unit as claimed in claim 1 also comprises a BIOS mark in this flash memory address contrast storer, is the BIOS data in order to point out data stored in the flash memory.
6. flash memory device administrative unit as claimed in claim 1, also comprise a BIOS address setting unit, read BIOS error in data message in order to detect one, import this BIOS mark in this flash memory address contrast storer, the BIOS flash memory that changes in this flash memory address contrast storer is set.
7. a flash memory device management method is applicable to a computer system, and its method comprises the following steps:
Import a memory operation instruction and a storage operation address section;
Read a flash memory setting value;
Import flash memory address contrast and store record, this flash memory address contrast record comprises storer numbering, a storage address interval;
According to this storage operation address section, retrieve this storer numbering; And
Produce a LPC1.1 memory operation instruction according to this flash memory setting value, this storer numbering.
8. flash memory device management method as claimed in claim 7, in this memory operation instruction of input and this storage operation address section step, wherein this memory operation instruction is a memory read instruction fetch.
9. flash memory device management method as claimed in claim 7, in this memory operation instruction of input and this storage operation address section step, wherein this memory operation instruction is that a storer writes instruction.
10. flash memory device management method as claimed in claim 7 stores in the record step in the contrast of input one flash memory address, and this storer is numbered IDSEL numbering.
11. flash memory device management method as claimed in claim 7 stores in the record step in the contrast of input one flash memory address, this storage address interval comprises an initial address and a termination address.
12. flash memory device management method as claimed in claim 7 stores in the record step in the contrast of input one flash memory address, this storage address interval comprises an initial address and a memory size.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031472737A CN1238791C (en) | 2003-07-11 | 2003-07-11 | Management unit of flash memory device and method thereof |
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| CNB031472737A CN1238791C (en) | 2003-07-11 | 2003-07-11 | Management unit of flash memory device and method thereof |
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| CN1472654A true CN1472654A (en) | 2004-02-04 |
| CN1238791C CN1238791C (en) | 2006-01-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020024383A1 (en) * | 2018-07-31 | 2020-02-06 | 江苏华存电子科技有限公司 | Flash memory storage apparatus and method for elastically controlling multiple types of flash memories |
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2003
- 2003-07-11 CN CNB031472737A patent/CN1238791C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020024383A1 (en) * | 2018-07-31 | 2020-02-06 | 江苏华存电子科技有限公司 | Flash memory storage apparatus and method for elastically controlling multiple types of flash memories |
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| CN1238791C (en) | 2006-01-25 |
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Granted publication date: 20060125 |