CN1472643A - FPGA and CPLD based impulse sequence programmer - Google Patents
FPGA and CPLD based impulse sequence programmer Download PDFInfo
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Abstract
The programmer is connected as: using Forth language processing unit as a core, FPGA connecting directly to Forth language control circuit CPLD, Forth languag processing unit FPGA connecting to logical interface of radio frequency, gradient and external circuit through driving and buffer circuit and Forth language processing unit connecting to static RAM and two-port RAM through driving circuit, ISA interface control circuit CPLD connecting to two-port RAM and PIO and two-port RAM and PIO connecting with bus of ISA. The spectrometer system suitable for NMR, NQR and MRI system can be designed based on the present invention.
Description
Affiliated technical field
The invention belongs to the nuclear magnetic resonance technique field, particularly a kind of pulse train programmable device based on FPGA (field programmable gate array) and CPLD (CPLD) realization.
Background technology
The pulse train programmable device is the core component of MRI spectrometer, different MRI spectrometer manufacturer pulse sequence programmable devices adopt different implementation methods, some manufacturer is the SMIS MR3020 control system that is based on the Forth language treatment technology of MRRS, Datalink, SeveNMR employing for example, its design philosophy is: will be compiled into Forth language with the pulse sequence program of PPL language compilation by compiler earlier, and then, implement control to gradient, radio frequency unit through Forth language processing unit formation binary code.
HARRIS RTX2000 chipset is a standard platform of handling Forth language.Above-mentioned MRI spectrometer manufacturer all is as the Forth language processor with HARRIS RTX2000 chipset.
The RTX2000 processor is based on the processor of two stack architectures, structure that these two storehouses adopt all that last in, first out (Last-In-First-Out).Be called data stack (Data Stack) and return stack (Return Stack).See shown in Figure 1.The parameter storehouse is one 256 * 16 a memory construction, and two unit of its top layer are respectively TOP register and NEXT register; Return stack is the memory construction of one 256 * 21 bit wide, and its top layer unit is kept by the I register.The RTX2000 processor core has the hardware control unit of 8 16 internal registers, an ALU (ALU) unit, internal data bus and execution command decoding and instruction execution sequence.
What the RTX2000 processor structurally adopted is the high-speed parallel structure, its basic operation is to control all data routings by command decoder, comprise programmable counter PC (Program Counter Register), command decoder, which kind of operation the decision of the content by order register IR (Instruction Register) is carried out and is determined the various orders of various operations again.
RTX2000 is divided into the no memory accessing operation and two kinds of access modes of memory access operation is arranged.The no memory access instruction is the single clock cycle operation, at first, and in the clock incipient stage, instruction is latched among the order register IR, refer to that then command decoder finishes instruction decode, carry out corresponding various operations at last, finish the finger work of getting of next bar instruction simultaneously.It is the doubleclocking cycleoperation that memory reference instruction is arranged, and in first clock period, by instruction decode, the storage address that visit is placed on the address bus, occurs the data that will operate on the memory data bus; Second clock period, finish the ALU operation, the address that will execute instruction next bar simultaneously is placed on the address bus of storer, prepares for taking off an instruction.
RTX2000 adopts is two to overlap independently address bus and data bus structure, because the concurrency of RTX2000 inner structure, the Forth operation that its per second is finished reaches as high as 40M/s, because a RTX2000 instruction can comprise many Forth basic operations.Except comprising the hardware configuration that is suitable for the Forth program run: CPU nuclear, two storehouses etc., RXT2000 also comprises a hardware multiplier, 3 counter timers, general purpose I/O interface, interruptable controller etc., they provide convenience for the expansion of system, and for example processor can pass through I/O interface accessing external unit.
Although producing on the efficient at code, Forth language is better than coeval other language, but since the complex grammar structure of Forth language itself with can not support nested structure, so not as other language are easy to be accepted by the people, make that the demand of RTX2000 chipset is not very big, finally cause the RTX2000 chip state of supply of material difficulty to occur.
Summary of the invention
At the problem that existing RTX2000 processor exists, the invention provides a kind of pulse train programmable device based on FPGA and CPLD realization.
Though pulse train programmable device of the present invention also is to adopt and the identical design philosophy of above-mentioned each spectrometer manufacturer, promptly earlier pulse sequence program is compiled into Forth language by the Forth compiler, after the compiling of Forth compiler, download in the processor then to realize control gradient and radio frequency unit, but Forth language processing unit that we adopted and sequential control system are based on FPGA (field programmable gate array) and CPLD (CPLD) realization respectively, and it is structurally different fully with Forth language application specific processor RTX2000 based on 16 Forth language processing units of FPGA realization, and on function, can substitute it fully, this makes our pulse train programing system not be subjected to the restriction and the circuit structure of the supply of material of RTX2000 chip fairly simple, and debugging maintenance is also very convenient.
The structure of the pulse train programmable device of realizing based on FPGA and CPLD as shown in Figure 1.It partly is made up of radio frequency, gradient external circuit logic interfacing circuit, Forth language processing unit control circuit, ISA interface control circuit, dual port RAM (DPRAM), static RAM (SRAM) (SRAM) and Forth language processing unit etc.
When the pulse train programmable device is initialized, main frame is provided with the DPRAM address by the PIO mouth on the pulse train programmable device, in DPRAM, at this moment the ISA interface control circuit of being realized by piece of CPLD is mainly handled the hardware connectivity problem of isa bus and DPRAM with a BOOT.IMG document copying by name.After copy finishes, start the Forth language processing unit, begin to carry out the BOOT.IMG document code among the DPRAM, BOOT.IMG is actually a guiding Forth language processing unit and sets up the small routine of communicating by letter with main frame.DPRAM also exists as a transitional facility between main frame ISA and the Forth language processing unit simultaneously, the transmission of both sides' communication data is by its realization, under the assistance of DPRAM, main frame is with in the static RAM (SRAM) on the file POWER.IMG download pulse train programmable device plate, and POWER.IMG comprises the executable code of Forth language processing unit.After download is finished, the Forth language processing unit is turned the address space of static RAM (SRAM) and is begun to carry out POWER.IMG, it has comprised all control commands on the pulse train programmable device, under the effect of Forth language processing unit, these control commands are carried out, and carry out exchanges data by input/output port and gradient and rf board, and the problem of hardware interface of Forth language processing unit and DPRAM and external unit is finished by the Forth language processing unit control circuit that another sheet CPLD realizes.
Set up after the communication, main frame is bigger POWER.IMG file of the transmission of the RAM in the pulse train programmable device just.In case transmission is finished, and just begins to carry out the code among the RAM.POWER.IMG is the operating system of MR3020.
After above pulse train programmable device initial work was finished, main frame just can transmit a PPL program that has compiled (.fth program) to the pulse train programmable device, and moved the PPL program that has compiled of up-to-date download.
Below be based on the functional description of the each several part circuit of the pulse train programmable device that FPGA and CPLD realize.
Radio frequency, gradient external circuit logic interfacing circuit: PL1 are based on the expansion mouth of the Forth language processing unit memory map registers of FPGA realization, realize the control of impulse controller to gradient signal waveform frequency, phase place and gain by this interface; The PL2 mouth is based on the I/O bus expansion mouth of the Forth language processing unit of FPGA realization, and by the PL2 interface, pulse control unit can be provided with sampling interval, start address and the triggering waveform generator of image sequence; PL3 interface radio frequency control interface is realized the control of impulse controller to radio frequency output pulse waveform frequency, phase place and gain by this interface.Host interface mainly is the data communication that solves computing machine and pulse train programmable device.
Forth language processing unit control circuit: this partial circuit is based on that CPLD realizes, is used to finish the controls such as decoding of each control signal of storer, driving circuit and buffer circuit enable signal and peripheral interface control signal.
The ISA interface control circuit: this partial circuit is based on also that CPLD realizes, the interface logic that is used to finish pulse train programmable device and main frame is controlled.
Dual port RAM (DPRAM): the exchanges data that can realize computing machine (main frame) and Forth language processing unit by dual port RAM.
Static RAM (SRAM) (SRAM): because the design's Forth language processing unit does not have on-chip memory, so need to adopt static RAM (SRAM) to expand external memory storage.This Forth language processing unit has 20 address signal lines, the program/data memory addresses space of energy addressing 1M byte, and its address assignment is as shown in the table.
Table 1 Forth language processing unit allocation tables
| Storage address | Purposes |
| ??00000-7FFFF | Static RAM (SRAM) (SRAM) |
| ??80000-DFFFF | Do not use |
| ??E0000-EFFFF | The EPROM expansion |
| ??F0000-F7FFF | DPRAM |
| ??F8000-FFF7F | Memory mapped I/O, by expansion interface /IOE control |
| ??FFF80-FFFFF | Do not use |
The Forth language processing unit: the Forth language processing unit of realizing based on FPGA is the core of pulse train programmable device, this unit is made up of data stack and return stack, arithmetic/logic unit, stream instruction control unit, interruptable controller, time controller, value decoding scheme, multiplier, I/O interface and internal register, and its inner structure as shown in Figure 2.Each module all is to use hardware description language-VHDL to realize that in conjunction with the private resource of FPGA inside the performance period of every instruction in this Forth language processing unit is divided into following four-stage: get fingers-decoding-according to sequential requirement execution corresponding operating-return result.
When the instruction cycle begins, at first get and refer to operation, instruction is taken out from storer at the rising edge of first clock period, subsequently according to concrete instruction, state controller and decoding unit (the two is called control module again) can produce corresponding microoperation order, under the synchronous effect of clock, each register, data stack (Data Stack), return stack (Return Stack), the alu unit, multiplier or other internal resource begin action, carry out corresponding reading, write, computing, operations such as counting, when the instruction cycle will finish, also the result of instruction to be write corresponding target ground, and then finish command function.In each internal resource executable operations, under the control of controller, if present instruction is a sequential instructions, the address of next bar instruction is written into programmable counter (program counter), places it on the address bus again in the suitable moment then; If present instruction is the function call instruction, before with next bar instruction address write-in program counter, the value of current program counter need be saved in return stack, so so that program can obtain correct return address when returning.When interrupting taking place, also need to preserve current pc value to return stack.After present instruction was finished, an instruction can be taken off according to the value that occurs on the address wire automatically by system from storer, and so repeatedly, system is able to steady and continuous ground and carries out.
The implementation method and the gordian technique thereof that below are the Forth language processing unit are described.
The realization of instruction beat control: for the operation beat of steering order and each functional unit, finite state machine is the optimal selection object in design.The system clock of the Forth language processing unit of realizing based on FPGA is pclk, and under non-waiting status, the frequency of input clock iclk is two times of pclk.Therefore in VHDL realizes,, its instruction cycle can be divided into " run1 " and " fetch " two states by iclk to one-cycle instruction; And the binary cycle instruction can be divided into " run1 ", " run2 ", " run3 " reaches " fetch " one of four states.When being in waiting status, can add " wait1 " and " wait2 " or " wait3 " and " wait4 " two states.Reset mode is defined as RESET1, and the Forth language processing unit was got between the finger in the reset back and the first time, and it is the set-up procedure of two iclk that a length is arranged, and is defined as RESET2 and RESET3.The state conversion process of state machine as shown in Figure 3." run1 " must be the beginning of an instruction like this, and " fetch " must be its end.
State machine adopts the way of realization of two process state machine, and the enumeration type that defines in the implementation procedure of state machine is STATES, and it comprises 11 enumerated values, and definition currentstate and nextstate existing attitude of conduct and next state respectively.
Type?STATES?is(reset1，reset2，reset3，fetch，run1，run2，run3，wait1，wait2，wait3，wait4)；
Signal?currentstate，nextstate：STATES；
Above-mentioned waiting status is meant the residing state of Forth language processing unit when high level appears in pin WAIT, WAIT signal one occurs, the Forth language processing unit can be in waiting status (also no longer detecting the WAIT signal) at ensuing two iclk, rising edge at the 3rd iclk continues to detect the WAIT signal then, if it is still effective, continuing to wait for, so repeatedly, is low level until WAIT.
Reading of instruction: after the Forth language processing unit resets, the value of PC is zero, begin to get article one instruction, this moment, currentstate was " RESET3 " state, if the WAIT invalidating signal, instruction is read into order register IR at the rising edge of first iclk in present instruction cycle, if WAIT is effective, then postpone to get finger, until the WAIT blackout, this moment, currentstate was " WAIT2 ".Second is later gets and refers to the basic identical of operation and article one, different just currentstate=" FETCH " or " WAIT2 ".The convection current instruction will suspend and get the finger operation.Owing to order code need be latched in the IR register, so the mode that reads employing and state synchronized of instruction.
The control of instruction execution flow: at first, with the division of operations of each instruction is a plurality of microoperations, with each register, bus, storehouse, read mode etc. and all regard a kind of operand as, each of these objects is operating as a microoperation, and code translator and timeticks generator are used for producing the microoperation command sequence.In the design, all micro-orders of each operand are defined as a kind of enumeration type signal, different enumerated values is represented different microoperations, i.e. every kind of each object corresponding a kind of enumerated value of enumerating signal of mode of operation.In an instruction cycle, these enumerate signal is not changeless, and they are comprising time control information changing by the clock beat, i.e. operand complete operation when.All be the combinational logic design in the code translator, the effect of step is equivalent to the signal clock beat generator, and it is controlling the variation of micro-order signal in the instruction cycle, and promptly different timeticks is got different action types, finally produces the micro-order sequence.Fig. 4 is the abstract block diagram of control module entity, and wherein input signal mainly is instruction code and timeticks signal step, and output is the operating control signal of each operand.
The realization of stream instruction: flow a kind of special instruction in the Forth language processing unit that instruction is the design, but it is not to be a kind of new instruction, but concentrates existing certain bar specific instruction with specific continuation mode execution command.The characteristics of this instruction are, only get finger when carrying out for the first time, carry out for later n time to get finger no longer again, therefore in the execution of stream instruction, get and refer to that operation temporarily stops, just recovery after the stream instruction is finished.Do not have the instruction of division and square root in the design's Forth language processing unit, we realize by the stream instruction mode and by certain algorithm.
Pulse train programmable device based on FPGA and CPLD realization of the present invention can be broken away from the restriction that special chip handled in Forth language, for society creates more wealth so that rely on the user of Forth language processing capacity.
Description of drawings
Fig. 1 is a structural representation of the present invention,
Fig. 2 is the Forth language processing unit structured flowchart that the present invention is based on the FPGA realization,
Fig. 3 is the state conversion process figure of state machine of the present invention,
Fig. 4 is the abstract block diagram of control module entity of the present invention,
Fig. 5 is applied to the spectrometer system structured flowchart for the present invention.
Embodiment
Formation of the present invention is as shown in Figure 1: with the Forth language processing unit realized based on FPGA is core, the Forth language processing unit directly and control circuit CPLD link, the Forth language processing unit links to each other with radio frequency, gradient and external circuit logic interfacing with the buffering circuit by driving circuit, and the Forth language processing unit links by driving circuit and static RAM (SRAM) and dual port RAM; ISA interface control circuit CPLD and dual port RAM and PIO link, and dual port RAM and PIO link with isa bus.
Based on pulse train programmable device of the present invention, the spectrometer system of NMR (nuclear magnetic resonance NuclearMagnetic Resonance), NQR (nuclear quadrupole resonance Nuclear Quadrupole Resonance), MRI (Magnetic resonance imaging Magnetic Resonance Imaging) system be can be designed to be applicable to, petroleum prospecting, chemical analysis, water source searching and medical clinic applications or the like carried out to realize the method that image application is learned.
Adopt the method for this pulse train programmable device design spectrum instrument system as described below:
Use this pulse train programmable device pulse train is construed to various parameters and control command, and additional figure sequence generating unit, gradient waveform signal generating unit, radio frequency reception and transmitting element and DSP unit are worked in coordination with by certain time sequence by this programmable device, enable to export on request RF signal and gradient signal, and can carry out DSP (digital signal processing) to the RF signal that receives and handle.The annexation of each several part as shown in Figure 5.
Claims (8)
1, a kind of pulse train programmable device based on FPGA and CPLD realization, it is characterized in that by radio frequency, gradient external circuit logic interfacing circuit, Forth language processing unit control circuit, the ISA interface control circuit, dual port RAM, static RAM (SRAM) and Forth language processing unit are formed, it is to be core with the Forth language processing unit that its circuit connects, FPGA directly and Forth language control circuit CPLD link, Forth language processing unit FPGA is by driving circuit and buffering circuit and radio frequency, gradient and external circuit logic interfacing link to each other, and the Forth language processing unit links by driving circuit and static RAM (SRAM) and dual port RAM; ISA interface control circuit CPLD is connected with dual port RAM and PIO, dual port RAM is connected with isa bus with PIO, when the pulse train programmable device is initialized, main frame is provided with the DPRAM address by the PIO mouth on the pulse train programmable device, with a BOOT.IMG document copying by name in DPRAM, at this moment the ISA interface control circuit of being realized by piece of CPLD is mainly handled the hardware connectivity problem of isa bus and DPRAM, after copy finishes, start the Forth language processing unit, begin to carry out the BOOT.IMG document code among the DPRAM, DPRAM also exists as a transitional facility between main frame ISA and the Forth language processing unit simultaneously, realize the transmission of both sides' communication data by it, under the assistance of DPRAM, main frame is with in the static RAM (SRAM) on the file POWER.IMG download pulse train programmable device plate, POWER.IMG comprises the executable code of Forth language processing unit, after download is finished, the Forth language processing unit is turned the address space of static RAM (SRAM) and is begun to carry out POWER.IMG, it has comprised all control commands on the pulse train programmable device, under the effect of Forth language processing unit, these control commands are carried out, and carry out exchanges data by input/output port and gradient and rf board, and the problem of hardware interface of Forth language processing unit and DPRAM and external unit is finished by the Forth language processing unit control circuit that another sheet CPLD realizes; Set up after the communication, main frame is bigger POWER.IMG file of the transmission of the RAM in the pulse train programmable device just, in case transmission is finished, just begins to carry out the code among the RAM; After above pulse train programmable device initial work was finished, main frame just can transmit a PPL program that has compiled (.fth program) to the pulse train programmable device, and moved the PPL program that has compiled of up-to-date download.
2, pulse train programmable device based on FPGA and CPLD realization according to claim 1, it is characterized in that described Forth language processing unit, it is the core of pulse train programmable device, this unit is by data stack and return stack, arithmetic/logic unit, the stream instruction control unit, interruptable controller, time controller, the value decoding scheme, multiplier, I/O interface and internal register are formed, each module all is to use hardware description language-VHDL to realize that in conjunction with the private resource of FPGA inside the performance period of every instruction in this Forth language processing unit is divided into following four-stage: get fingers-decoding-according to sequential requirement execution corresponding operating-return result; When the instruction cycle begins, at first get and refer to operation, instruction is taken out from storer at the rising edge of first clock period, subsequently according to concrete instruction, state controller and decoding unit can produce corresponding microoperation order, and under the synchronous effect of clock, each register, data stack, return stack, alu unit, multiplier or other internal resource begin action, carry out operations such as corresponding reading and writing, computing, counting, when the instruction cycle will finish; Also the result of instruction to be write corresponding target ground, and then finish command function, in each internal resource executable operations, under the control of controller; If present instruction is a sequential instructions, the address of next bar instruction is written into programmable counter, places it on the address bus again in the suitable moment then; If present instruction is the function call instruction, before with next bar instruction address write-in program counter, the value of current program counter need be saved in return stack, so so that program can obtain correct return address when returning; When interrupting taking place, also need to preserve current pc value to return stack; After present instruction was finished, an instruction can be taken off according to the value that occurs on the address wire automatically by system from storer, and so repeatedly, system is able to steady and continuous ground and carries out.
3, the pulse train programmable device based on FPGA and CPLD realization according to claim 1, it is characterized in that described PL1 is based on the expansion mouth of the Forth language processing unit memory map registers of FPGA realization, realizes the control of impulse controller to gradient signal waveform radio frequency, phase place and gain by PL1.
4, the pulse train programmable device based on FPGA and CPLD realization according to claim 1, it is characterized in that described PL2 is based on the I/O bus expansion mouth of the Forth language processing unit of FPGA realization, sampling interval, start address and the triggering waveform generator of image sequence can be set by PL2 mouth pulse control unit.
5, the pulse train programmable device based on FPGA and CPLD realization according to claim 1 is characterized in that described PL3 interface is the radio frequency control interface, realizes the control of impulse controller to radio frequency output waveform frequency, phase place and gain by this interface.
6, the pulse train programmable device based on FPGA and CPLD realization according to claim 1 is characterized in that host interface mainly is the data communication that solves computing machine and pulse train programmable device.
7, the pulse train programmable device based on FPGA and CPLD realization according to claim 1 is characterized in that described Forth language processing unit control circuit is used to finish the encoded control of each control signal of storer, driving circuit and buffer circuit enable signal and peripheral interface control signal.
8, the pulse train programmable device based on FPGA and CPLD realization according to claim 1 is characterized in that the ISA interface circuit is used to finish the interface logic control of pulse train programmable device and main frame; Realize the exchanges data of main frame and Forth language processing unit by dual port RAM; Adopt static RAM (SRAM) expansion external memory storage.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100483348C (en) * | 2005-04-29 | 2009-04-29 | 美国凹凸微系有限公司 | System and method for upgrading bit files for a field programmable gate array |
| CN101436171B (en) * | 2008-11-24 | 2010-04-07 | 中国电子科技集团公司第二十八研究所 | Modular communication control system |
| CN101330326B (en) * | 2007-06-18 | 2011-07-06 | 上海普天邮通科技股份有限公司 | Digital circuit for implementing audio data optical transmission using CPLD and method thereof |
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| CN100483348C (en) * | 2005-04-29 | 2009-04-29 | 美国凹凸微系有限公司 | System and method for upgrading bit files for a field programmable gate array |
| CN101330326B (en) * | 2007-06-18 | 2011-07-06 | 上海普天邮通科技股份有限公司 | Digital circuit for implementing audio data optical transmission using CPLD and method thereof |
| CN101436171B (en) * | 2008-11-24 | 2010-04-07 | 中国电子科技集团公司第二十八研究所 | Modular communication control system |
| CN102103196B (en) * | 2009-12-18 | 2013-03-06 | 东软飞利浦医疗设备系统有限责任公司 | System and method for generating magnetic resonance gradient waveform with adjustable digital pre-emphasis |
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| CN102522901A (en) * | 2011-11-19 | 2012-06-27 | 中国西电电气股份有限公司 | Method, device and system for controlling power conversion of frequency converter |
| CN102522901B (en) * | 2011-11-19 | 2014-03-12 | 中国西电电气股份有限公司 | Method, device and system for controlling power conversion of frequency converter |
| CN106339027A (en) * | 2016-09-08 | 2017-01-18 | 合肥迈威德智能科技有限公司 | Pulse signal generator |
| CN109683523A (en) * | 2018-12-25 | 2019-04-26 | 中国人民解放军96630部队 | Accelerator control method and system based on programmable gate array FPGA |
| CN113064692A (en) * | 2021-04-06 | 2021-07-02 | 深圳市研强物联技术有限公司 | Firmware picture resource data generation method and system |
| CN113064692B (en) * | 2021-04-06 | 2022-11-29 | 深圳市研强物联技术有限公司 | Method and system for generating firmware picture resource data |
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