CN1469456A - Manufacture of integrated circuit array structure - Google Patents
Manufacture of integrated circuit array structure Download PDFInfo
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- CN1469456A CN1469456A CNA031374999A CN03137499A CN1469456A CN 1469456 A CN1469456 A CN 1469456A CN A031374999 A CNA031374999 A CN A031374999A CN 03137499 A CN03137499 A CN 03137499A CN 1469456 A CN1469456 A CN 1469456A
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Abstract
The present invention reveals one kind of manufacture process of integrated circuit array structure with two masks. The first mask with hole array pattern is used to perform the first incomplete exposure and the second mask with the required memory code pattern is used to perform the second exposure in the complementary exposure dosage to the first one, photoresist in the hole regions to be opened is made to obtain sufficient exposure dosage and the holes are opened after further development. The said process can obtain excellent exposure resolution and proper focus depth and lowered optical proximity effect with easy-to-make masks.
Description
Technical field
The present invention relates to the manufacture method of array (Array) structure of a kind of integrated circuit (IC), particularly relate to a kind of method of utilizing selectivity to expose to make the array structure of integrated circuit.
Prior art
Generally speaking, the kind of integrated circuit mainly comprises two kinds of logic (Logic) device and internal memories, wherein logical device, for example microprocessor of computer (Microprocessor), in order to the actuating logic computing, internal memory is then in order to store the semiconductor device of data or data.Usually, internal memory can roughly be divided into read-only memory (Read Only Memory; ROM) and random access memory (Random Access Memory; RAM) two classes.
At least include a plurality of memory cell (Cell) in the read-only memory, then comprise a metal-oxide semiconductor (MOS) (Metal OxideSemiconductor in each memory cell at least for the storage data; MOS) transistor.Because, being stored in data in the read-only memory or data can not change because of electric power starting or power interruptions, and when power-off, therefore the data that are stored in read-only memory can not disappear yet, reason that why read-only memory can only Gong read that Here it is.Read-only memory can be subdivided into mask ROM (Mask ROM according to the difference of data logging mode again; MROM), programmable read only memory (ProgrammableROM; PROM), EROM (Erasable PROM; EPROM) and erasable read-only memory (the Electrically Erasable PROM that writes; EEPROM) etc.
Mask ROM is the most basic a kind of read-only memory, its manufacture is for being arranged in a plurality of metal oxide semiconductor transistors on the chip with matrix-style earlier, and wherein these metal oxide semiconductor transistors are taken as the memory cell in order to the storage data.Then, carry out write step, utilize lithography process that the memory code pattern on the mask (code pattern) layout is transferred on the read-only memory, and optionally inject the metal oxide semiconductor transistor of ion to appointment, and the metal oxide semiconductor transistor that makes ion inject can't operate, and then forms read-only memory structure.Because the mask manufacturing that the utilization of this kind read-only memory has the memory code pattern forms, thereby is called mask ROM.
Please refer to Fig. 1 and Fig. 2, Fig. 1 illustrates known binary system (Binary) memory code pattern layout figure, and Fig. 2 illustrates the made mask of binary storage sign indicating number pattern layout figure according to Fig. 1.Binary storage sign indicating number pattern layout Figure 100 becomes the matrix form distribution to be constituted by memory code " 1 " and memory code " 0 ", and the memory code " 1 " on binary storage sign indicating number pattern layout Figure 100 and the position of memory code " 0 " correspond respectively to the unit area on the mask 102, the position that is memory code " 0 " is corresponding with the transmission region 104 of mask 102, and the position of memory code " 1 " is light tight regional 106 corresponding with mask 102 then.
Please refer to Fig. 3 to Fig. 5, it illustrates the known schematic flow diagram that the binary storage sign indicating number pattern layout of Fig. 1 is write read-only memory.As shown in Figure 3, read-only memory 122 is positioned on the predeterminable area of chip 120, and comprise the memory cell 124 that a plurality of one-tenth matrix forms are arranged on the read-only memory 122 at least, wherein each memory cell 124 comprises a metal oxide semiconductor transistor (not shown) all at least.When binary storage sign indicating number pattern layout Figure 100 of Fig. 1 is write read-only memory 122, at first on read-only memory 122, cover one deck photoresist layer 126, use lithography process again, and utilize according to the formed mask 102 of binary storage sign indicating number pattern layout Figure 100, to read-only memory 122, wherein the unit area of mask 102 is corresponding with the memory cell 124 of read-only memory 122 with the design transfer on the mask 102.Therefore, behind lithography process, in these memory cell 124 on the read-only memory 122, the position is light tight regional 106 with respect to mask 102, still is coated with photoresist layer 126 on it, as shown in Figure 4.
Then, carry out the ion implantation step, ion being injected the memory cell 124 that does not cover photoresist layer 126 on it, and form ion implanted region 128, again remaining photoresist layer 126 is removed, as shown in Figure 5.Therefore, the operating voltage of the metal oxide semiconductor transistor of ion implanted region 128 can improve, and makes the metal oxide semiconductor transistor of ion implanted region 128 lose its usefulness and can't use.At this moment, made the read-only memory 122 of the binary storage sign indicating number pattern layout Figure 100 that meets Fig. 1.
Yet along with the lifting day by day of device integrated level, device size also tends to microminiaturization.When using mask 102 to carry out the step of exposure of lithography process, because optical approximate effect (OpticalProximity Effect; OPE) influence makes the resolution that shifts pattern reduce.In order to improve the resolution that shifts pattern, can select for use the short light source of wavelength to be used as exposure light source usually, yet short wavelength's exposure light source but can cause the depth of focus (depth of focus, reduction DOF).Therefore, can't effectively and successfully the memory code pattern layout on the mask 102 be transferred on the read-only memory 122, and then cause and correctly binary storage sign indicating number pattern layout Figure 100 to be write in the read-only memory 122.
At present, the another kind of known method that the binary storage sign indicating number is write read-only memory is disclosed in United States Patent (USP) 6,166, in 943.When utilization the method writes read-only memory with the binary storage sign indicating number, utilize the twice mask, and coating Twi-lithography glue-line, can reach and improve the purpose that the binary storage sign indicating number writes the success rate of read-only memory.Yet, because the employed twice mask of the method all belongs to crucial mask (Critical Mask), and need utilization resolution to strengthen technology (RET:ResolutionEnhancement Technologies), and the manufacture process of this twice mask is all quite loaded down with trivial details, the degree of difficulty of making is also quite high, manufacturing time is long, expends the cost height.In addition, this method need use two-layer photoresist, therefore not only can increase the process time, improves the complexity of technology, and the also raising relatively of required cost, can't meet the demand of semiconductor technology.
Summary of the invention
In the manufacture process in view of the array structure of above-mentioned known integrated circuit, when the memory code pattern is write read-only memory, the Chang Wufa acquisition has the transfer pattern of the depth of focus of high-resolution and abundance, and causes and can't successfully memory code be write in the read-only memory.In addition, in order to obtain the preferable resolution and the darker depth of focus, the method that is adopted, its employed twice mask is quite complicated, difficult on making, and the cost height of mask, and it is tediously long to make time-histories, does not meet process requirements.
Therefore, a purpose of the present invention is exactly the manufacture method at the array structure that a kind of integrated circuit is provided, it utilizes the first road mask, carry out the step of exposure first time with part dosage, utilize the second road mask again, carry out the step of exposure second time to replenish dosage, so that the area of the pattern of required unlatching exposes fully.Therefore, can reduce the optical approximate effect, improve resolution, increase the depth of focus, and then improve the accuracy that memory code writes the internal memory of integrated circuit.
Another object of the present invention is exactly the manufacture method at the array structure that a kind of read-only memory is provided, in the manufacture method of the array structure of this read-only memory, can utilize the first road mask earlier, and carry out first step of exposure with incomplete exposure dose, expose with hole zone, be used as semi-finished product array structure.Again when receiving customer order, make and have the second road mask of the required memory code pattern of client, and utilize this second road mask, with replenish first step of exposure not enough exposure dose carry out second step of exposure, and memory code is write in the read-only memory.Utilization the present invention can not need the change because of product, and the manufacture process of whole read-only memory is done change significantly, only need change the second road mask and get final product.Therefore, can significantly shorten the manufacturing time of read-only memory, be highly suitable for a large amount of productions.
Another object of the present invention is exactly because in the manufacturing of the array structure of read-only memory, only need use one deck photoresist, therefore can reduce the use of photoresist, reduces the technology cost, and shortens the process time.
According to above-described purpose, the present invention also provides a kind of manufacture method of array structure of integrated circuit, be applicable to an array layout is write in the read-only memory, wherein this read-only memory comprises a plurality of memory cell at least, and the manufacture method of the array structure of this integrated circuit comprises at least: form a photoresist layer and cover on this read-only memory; One first road mask is provided, wherein comprise a plurality of first kind of unit area and a plurality of second kind of unit area on this first road mask at least, and the position of these first kind of unit area and second kind of unit area is corresponding to the memory cell of read-only memory; Utilize the first road mask and, this photoresist layer is carried out one first step of exposure, first kind of unit area on this first road mask and second kind of unit area are shifted so far on the photoresist layer with a part of exposure dose; One second road mask is provided, and comprise above-mentioned array layout at least on this second road mask, wherein this array layout comprises a plurality of first kind of unit area and a plurality of second kind of unit area at least, and the position of these first kind of unit area and second kind of unit area is corresponding to the memory cell of read-only memory; Utilize the second road mask and replenish exposure dose with one, this photoresist layer is carried out one second step of exposure, the array layout on this second road mask is shifted so far on the photoresist layer; Carry out a development step, with remove the part this photoresist layer, and expose the part memory cell; Carry out an ion implantation step, ion is injected the memory cell that exposes; And the photoresist layer that removes remainder.Wherein, above-mentioned ion implantation step also can replace by an etching step, to remove the memory cell of exposure.
The accompanying drawing simple declaration
Fig. 1 draws the layout of known binary storage sign indicating number pattern.
Fig. 2 draws the top view according to the made mask of the binary storage sign indicating number pattern layout figure of Fig. 1.
Fig. 3 to Fig. 5 draws the known schematic flow diagram that the binary storage sign indicating number pattern layout of Fig. 1 is write read-only memory.
Fig. 6 draws the binary storage sign indicating number pattern layout figure of a preferred embodiment of the present invention.
Fig. 7 draws the top view of the first road mask of a preferred embodiment of the present invention.
Fig. 8 draws the top view of the second road mask of a preferred embodiment of the present invention, and this second road mask forms according to the binary storage sign indicating number pattern layout figure manufacturing of Fig. 6.
Fig. 9 to Figure 13 draws the schematic flow diagram that the binary storage sign indicating number pattern layout of Fig. 6 is write read-only memory of a preferred embodiment of the present invention.
The conventional letter simple declaration
100: binary storage sign indicating number pattern layout figure
102: mask
104: transmission region
106: light tight zone
120: chip
122: read-only memory
124: memory cell
126: photoresist layer
128: ion implanted region
200: binary storage sign indicating number pattern layout figure
210: the first road masks
212: the first kinds of unit areas
214: the second kinds of unit areas
220: the second road masks
222: the first kinds of unit areas
224: the second kinds of unit areas
240: chip
242: read-only memory
244: memory cell
246: photoresist layer
248: incomplete exposure region
249: complete exposure region
250: ion implanted region
Execution mode
The present invention discloses a kind of manufacture method of array structure of integrated circuit, it utilizes the twice mask, to the same photoresist layer on the read-only memory that is covered in integrated circuit, double expose, exactly required memory code being write in the read-only memory, and form required read-only memory array.In order to make narration of the present invention more detailed and complete, can be with reference to the diagram of following description and cooperation Fig. 6 to Figure 13.
Please refer to Fig. 6, it illustrates the binary storage sign indicating number pattern layout figure of a preferred embodiment of the present invention, and wherein the layout of this binary storage sign indicating number pattern layout figure is the array layout of internal memory.In an embodiment of the present invention, the binary storage sign indicating number pattern layout Figure 200 that is adopted is identical with known binary storage sign indicating number pattern layout Figure 100, and wherein this binary storage sign indicating number pattern layout Figure 200 only in order to explanation, the invention is not restricted to this.This binary storage sign indicating number pattern layout Figure 200 is made of the memory code " 1 " and the memory code " 0 " of arranging with matrix form.When the layout with this binary storage sign indicating number pattern layout Figure 200 is transferred to the internal memory of integrated circuit, promptly represents array layout to be transferred on the internal memory, and form required memory array structure thus internal memory.
Please refer to Fig. 7, it illustrates the top view of the first road mask of a preferred embodiment of the present invention.At least comprise a plurality of first kind of unit area 212 and a plurality of second kind of unit area 214 on the first road mask 210 of the present invention, wherein arrange with matrix-style these first kind of unit area 212 and second kind of unit area 214, and first kind of unit area 212 is the light-permeable zone, and second kind of unit area 214 then is light tight zone.In addition, the position of these first kind of unit area 212 and second kind of unit area 214 is corresponding with the memory cell 244 on the read-only memory 242 (shown in Figure 9).
Please refer to Fig. 8, it illustrates the top view of the second road mask of a preferred embodiment of the present invention, and this second road mask forms according to the binary storage sign indicating number pattern layout figure manufacturing of Fig. 6.The second road mask 220 of the present invention comprises a plurality of first kind of unit area 222 and a plurality of second kind of unit area 224 at least, wherein arrange with matrix-style these first kind of unit area 222 and second kind of unit area 224, and these first kind of unit area 222 be corresponding to the memory code " 0 " of binary storage sign indicating number pattern layout Figure 200 of Fig. 6, and these second kind of unit area 224 is then corresponding to the memory code " 1 " of binary storage sign indicating number pattern layout Figure 200.That is to say to have the memory code layout of read-only memory 242 of the present invention on the second road mask 220.In addition, the position of these first kind of unit area 222 and second kind of unit area 224 is corresponding to the memory cell 244 of read-only memory 242, and these first kind of unit areas 222 are the light-permeable zone, and these second kind of unit areas 224 are light tight zone.
Please refer to Fig. 9 to Figure 13, it illustrates a preferred embodiment of the present invention the binary storage sign indicating number pattern layout of Fig. 6 is write the schematic flow diagram of read-only memory, and please in the lump with reference to Fig. 6, Fig. 7 and Fig. 8.Read-only memory 242 shown in Figure 9 is positioned on the chip 240, and does not write data as yet.This read-only memory 242 comprises a plurality of memory cell 244 at least, wherein each memory cell 244 comprises a metal oxide semiconductor transistor (not shown) all at least, and the position of these memory cell 244 is corresponding to first kind of unit area 222 and second kind of unit area 224 of first kind of unit area 212 of the first road mask 210 and the second kind of unit area 214 and the second road mask 220.
Figure 200 writes read-only memory 242 with binary storage sign indicating number pattern layout, when forming required array structure, forms one deck photoresist layer 246 earlier and covers on the memory cell 244 of read-only memory 242.Utilize for example step of exposure of lithography process again, utilize the first road mask 210, and use incomplete part exposure dose, photoresist layer 246 is carried out first step of exposure, and on photoresist layer 246, form a plurality of incomplete exposure regions 248, as shown in figure 10.Wherein, first kind of unit area 212 of the position of these incomplete exposure regions 248 and the first road mask 210, can transmission region corresponding.
Then, utilize for example step of exposure of lithography process, use the second road mask 220, with first step of exposure not enough additional exposure dose, photoresist layer 246 is carried out second step of exposure, and on photoresist layer 246, form a plurality of complete exposure regions 249, as shown in figure 11.Wherein, the position of these complete exposure regions 249 gets final product transmission region corresponding to first kind of unit area 222 of the second road mask 220.Carry out the development of photoresist layer 246 again, remove, and expose the memory cell 244 that is positioned under the complete exposure region 249, as shown in figure 12 with the photoresist that will cover on the complete exposure region 249.
With after covering photoresist on the complete exposure region 249 and removing fully, the memory cell 244 that exposes is carried out subsequent treatment, for example ion implantation step or etching step.When the subsequent treatment of being carried out is the ion implantation step, will be for example boron (B) plasma doping in the memory cell 244 that exposes, and make each memory cell that exposes 244 become an ion implanted region 250, as shown in figure 13.Metal oxide semiconductor transistor in the memory cell 244 of each ion implanted region 250, the operating voltage of grid of these metal oxide semiconductor transistors can improve because of ion injects, and causes these metal oxide semiconductor transistors to operate.On the other hand, when the subsequent treatment of being carried out was etching step, the memory cell 244 that then can utilize etching step directly will expose was removed.After the memory cell 244 that exposes loses effectiveness, remaining photoresist layer 246 is removed, just finished the array structure of read-only memory.
An advantage of the present invention just provides a kind of manufacture method of array structure of integrated circuit, it is writing memory code in the read-only memory, when forming required array structure, utilize the first road mask, carry out first step of exposure, utilize the second road mask again with incomplete dosage, with replenish first step of exposure not enough dosage carry out second step of exposure, and the memory cell of opening section, and then remove the memory cell of being opened, form required array structure.Therefore, can reduce the optical approximate effect of step of exposure, and improve the resolution and the depth of focus of lithography process, and then improve the accuracy that memory code writes the internal memory of integrated circuit, to form correct array structure.
Another advantage of the present invention is for being exactly the manufacture method at the array structure that a kind of read-only memory is provided, in the manufacture method of array structure of the present invention, can utilize the first road mask, carry out first step of exposure with incomplete exposure dose, and make the subregion partial exposure of read-only memory array structure, be used as semi-finished product.Again when receiving customer order, manufacturing has the second road mask of the required memory code pattern of client, and utilize this second road mask, with replenish first step of exposure not enough exposure dose carry out second step of exposure, and memory code is write in the read-only memory, read-only memory promptly is written into.In addition, can not need difference, and significantly change the technology of read-only memory, only need change the second road mask and get final product because of the storage data.Therefore, can shorten the manufacturing time of read-only memory widely.
Another advantage of the present invention is exactly because in the manufacture process of the array structure of read-only memory, and it is fashionable to carry out writing of memory code, only need use one deck photoresist.Therefore, can reduce the use of photoresist, reduce the technology cost, and shorten the process time.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can do various changes and modification, so protection scope of the present invention should be as the criterion with the scope that claim was defined.
Claims (19)
1. the manufacture method of the array structure of an integrated circuit, be applicable to an array layout is write in the read-only memory of an integrated circuit, wherein said read-only memory comprises a plurality of memory cell at least, and the manufacture method of the array structure of described integrated circuit comprises at least:
Forming a photoresist layer covers on the described read-only memory;
One first road mask is provided, comprises a plurality of first kind of unit area and a plurality of second kind of unit area on the wherein said first road mask at least;
Utilize the described first road mask, and, described photoresist layer is carried out one first step of exposure with a part of exposure dose;
One second road mask is provided, and comprises described array layout at least on the described second road mask, wherein said array layout comprises a plurality of first kind of unit area and a plurality of second kind of unit area at least;
Utilize the described second road mask, and, described photoresist layer is carried out one second step of exposure with an additional exposure dose;
Carry out a development step, with remove the part described photoresist layer, and expose the part described memory cell;
Carry out an ion implantation step, ion is injected the described memory cell that exposes; And
Remove remaining described photoresist layer.
2. the manufacture method of the array structure of integrated circuit according to claim 1, wherein said array layout forms according to one group of binary storage sign indicating number.
3. the manufacture method of the array structure of integrated circuit according to claim 1, wherein each described memory cell comprises a metal-oxide semiconductor (MOS) (MOS) transistor at least.
4. the manufacture method of the array structure of integrated circuit according to claim 1, wherein said memory cell become matrix form to arrange.
5. the manufacture method of the array structure of integrated circuit according to claim 1, described first kind of unit area of the wherein said first road mask and described first kind of unit area of the described second road mask are a plurality of light-permeables zones.
6. the manufacture method of the array structure of integrated circuit according to claim 1, described second kind of unit area of the wherein said first road mask and described second kind of unit area of the described second road mask are a plurality of light tight zones.
7. the manufacture method of the array structure of integrated circuit according to claim 1, the described first kind of unit area of the wherein said first road mask and the position of described second kind of unit area are corresponding to the described memory cell of described read-only memory.
8. the manufacture method of the array structure of integrated circuit according to claim 1, the described first kind of unit area of the wherein said second road mask and the position of described second kind of unit area are corresponding to the described memory cell of described read-only memory.
9. the manufacture method of the array structure of integrated circuit according to claim 1, wherein said second step of exposure also comprise the described array layout on the described second road mask are transferred on the described photoresist layer.
10. the manufacture method of the array structure of an integrated circuit, be applicable to an array layout is write in the read-only memory of an integrated circuit, wherein said read-only memory comprises a plurality of memory cell at least, and the manufacture method of the array structure of described integrated circuit comprises at least:
Forming a photoresist layer covers on the described read-only memory;
Utilize one first road mask, and, described photoresist layer is carried out one first step of exposure, comprise a plurality of first kind of unit area and a plurality of second kind of unit area on the wherein said first road mask at least with a part of exposure dose;
Utilize one second road mask, and, described photoresist layer is carried out one second step of exposure, comprise described array layout at least on the wherein said second road mask with an additional exposure dose;
Carry out a development step, with remove the part described photoresist layer, and expose the part described memory cell;
Carry out an etching step, to remove the described memory cell of exposure; And
Remove remaining described photoresist layer.
11. the manufacture method of the array structure of integrated circuit according to claim 10, wherein said array layout forms according to one group of binary storage sign indicating number.
12. the manufacture method of the array structure of integrated circuit according to claim 10, wherein said array layout comprise a plurality of first kind of unit area and a plurality of second kind of unit area at least.
13. the manufacture method of the array structure of integrated circuit according to claim 12, wherein said first kind of unit area is a plurality of light-permeables zones.
14. the manufacture method of the array structure of integrated circuit according to claim 12, wherein said second kind of unit area is a plurality of light tight zones.
15. the manufacture method of the array structure of integrated circuit according to claim 10, wherein each described memory cell comprises a metal oxide semiconductor transistor at least.
16. the manufacture method of the array structure of integrated circuit according to claim 10, wherein said memory cell become matrix form to arrange.
17. the manufacture method of the array structure of integrated circuit according to claim 10, described first kind of unit area of the wherein said first road mask is a plurality of transmission regions.
18. the manufacture method of the array structure of integrated circuit according to claim 10, described second kind of unit area of the wherein said first road mask is a plurality of light tight zones.
19. according to the manufacture method of the array structure of claim 10 a described integrated circuit, wherein said second step of exposure also comprises the described array layout on the described second road mask is transferred on the described photoresist layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/178,476 | 2002-06-25 | ||
| US10/178,476 US6709923B2 (en) | 2002-05-24 | 2002-06-25 | Method for manufacturing an array structure in integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1469456A true CN1469456A (en) | 2004-01-21 |
| CN1240125C CN1240125C (en) | 2006-02-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03137499 Expired - Fee Related CN1240125C (en) | 2002-06-25 | 2003-06-25 | Manufacture of integrated circuit array structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN1240125C (en) |
| TW (1) | TW594938B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171827B (en) * | 2005-03-08 | 2011-04-20 | 索尼爱立信移动通讯股份有限公司 | Method and device for creating pictures |
| CN107015443A (en) * | 2016-01-27 | 2017-08-04 | 台湾积体电路制造股份有限公司 | The developing method and lithographic equipment of photosensitive material |
| US11880140B2 (en) | 2016-01-27 | 2024-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for dynamic lithographic exposure |
-
2003
- 2003-06-17 TW TW92116455A patent/TW594938B/en not_active IP Right Cessation
- 2003-06-25 CN CN 03137499 patent/CN1240125C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101171827B (en) * | 2005-03-08 | 2011-04-20 | 索尼爱立信移动通讯股份有限公司 | Method and device for creating pictures |
| US7962034B2 (en) | 2005-03-08 | 2011-06-14 | Sony Ericsson Mobile Communications Ab | Method and device for creating pictures |
| CN107015443A (en) * | 2016-01-27 | 2017-08-04 | 台湾积体电路制造股份有限公司 | The developing method and lithographic equipment of photosensitive material |
| US10663868B2 (en) | 2016-01-27 | 2020-05-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for dynamic lithographic exposure |
| US11003089B2 (en) | 2016-01-27 | 2021-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for dynamic lithographic exposure |
| US11520237B2 (en) | 2016-01-27 | 2022-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for dynamic lithographic exposure |
| US11880140B2 (en) | 2016-01-27 | 2024-01-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for dynamic lithographic exposure |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200400599A (en) | 2004-01-01 |
| TW594938B (en) | 2004-06-21 |
| CN1240125C (en) | 2006-02-01 |
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