CN1467843A - Integrated capacitor having polarity - Google Patents
Integrated capacitor having polarity Download PDFInfo
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- CN1467843A CN1467843A CNA021264244A CN02126424A CN1467843A CN 1467843 A CN1467843 A CN 1467843A CN A021264244 A CNA021264244 A CN A021264244A CN 02126424 A CN02126424 A CN 02126424A CN 1467843 A CN1467843 A CN 1467843A
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- vertical panel
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Abstract
An integration capacitor having polarity comprising a semiconductor substrate, a vertical board arranged on the semiconductor substrate, composed of a plurality of parallel first conductive strips through the electric connection of a plurality of first male plugs from top to bottom, a second vertical board arranged on the semiconductor substrate in parallel to the first vertical board, composed of a plurality of parallel second conductive strips through the electric connection of a plurality of parallel second male plugs from top to bottom, and a conductive plate, arranged under the first vertical board and the second vertical board, and between them and the semiconductor substrate, wherein the first vertical board is in electric connection with the conductive plate through at least a third male plug.
Description
Technical field
The present invention relates to a kind of integrated capacitance (integrated capacitor), relate in particular to a kind of integrated capacitance structure, be particularly suitable for being applied to analog/digital converter (A/D converter) or digital/analog converter (D/A converter) or commutation circuit (switch cap circuit) field with polarity.
Background technology
All the time, passive device (passive component) has been widely used at radio wave (radio frequency as electric capacity etc., RF) and in mixed-signal (mixed-signal) circuit, be applied in such as filter (filter), resonant circuit (resonant circuit), and bypass circuit circuit design such as (bypass) on.And in order to reduce manufacturing cost, IC makes or the design dealer there's no one who doesn't or isn't joins hands to stride forward towards the trend that improves the integrated integrated level of integrated circuit.
Fig. 1 is the partial structure end view of known high integration integrated capacitance.As shown in Figure 1, known integrated capacitance 1 is made of a plurality of vertical metal plates 100 that are arranged in parallel and 120, and wherein unblanketed is vertical metal plate 120, represents that it is to be electrically connected a node A, hypographous is vertical metal plate 100, represents that it is to be electrically connected a Node B. Vertical metal plate 100 and 120 all is formed on the semiconductor substrate (not shown).Each vertical metal plate 100 all is made of a plurality of metal level 10a, 10b, 10c and 10d and metal plug 11a, the 11b and the 11c that are electrically connected a plurality of metal level 10a, 10b, 10c and 10d.Each vertical metal plate 120 all is made of a plurality of metal level 12a, 12b, 12c and 12d and metal plug 13a, the 13b and the 13c that are electrically connected a plurality of metal level 12a, 12b, 12c and 12d.It between the vertical metal plate 100 and 120 a dielectric layer (not shown).Generally speaking, a plurality of metal level 10a, 10b, 10c and the 10d of known integrated capacitance 1 and a plurality of metal level 12a, 12b, 12c and 12d are that the metal interconnecting processing procedure with integrated circuit defines simultaneously and finishes, do not need extra light shield to come define pattern, therefore can save cost.In addition, known integrated capacitance 1 can provide higher unit-area capacitance value (capacitance per unit area).
Yet known integrated capacitance 1 is because the vertical metal plate 120 of connected node A and the vertical metal plate 100 of connected node B all can produce so-called parasitic capacitance (parasitic capacitance) with the semiconductor-based end that is positioned at its below during operation.See also Fig. 2, Fig. 2 is the equivalent circuit diagram of the known integrated capacitance 1 among Fig. 1.As previously mentioned, the vertical metal plate 120 of known integrated capacitance 1, it is electrical connection one node A, vertical metal plate 100, it is for being electrically connected a Node B.Between A node and B node, except the capacitance Cin that the self capacity structure is contributed, still there is a parasitic capacitance CA to produce at node A end, and still has a parasitic capacitance CB to produce at the Node B end.Parasitic capacitance CA and parasitic capacitance CB all are because the orlop metal level (being respectively metal level 10a and metal level 12a) of vertical metal plate 100 and 120 is responded to generation with the semiconductor-based end of ground connection.Thus, make known integrated capacitance 1 since in design two end nodes all parasitic capacitance is arranged and does not have polarity, therefore be not suitable for being applied to analog/digital converter (A/D converter) or digital/analog converter (D/A converter) or commutation circuit (switch cap circuit) field.
Summary of the invention
In view of the above, main purpose of the present invention is to provide a kind of high integration integrated capacitance with polarity, can be applied in the design of analog/digital converter (A/D converter) or digital/analog converter (D/A converter) or commutation circuit (switch cap circuit).
In most preferred embodiment of the present invention, disclosed a kind of integrated capacitance with polarity, include the semiconductor substrate; First vertical panel was located on this semiconductor-based end, and this first vertical panel system is electrically connected institute mutually via a plurality of first connectors up and down by a plurality of buss that are locked in a tie for first and constitutes; Second vertical panel, itself and this first vertical panel were set in parallel on this semiconductor-based end, and this second vertical panel system is electrically connected institute mutually via a plurality of second connectors up and down by a plurality of buss that are locked in a tie for second and constitutes; And a conductive plate, be located under this first vertical panel and this second vertical panel, and between this first vertical panel and this second vertical panel and between this semiconductor-based end.Wherein this first vertical panel system is electrically connected with this conductive plate via at least one the 3rd connector.
According to another preferred embodiment of the present invention, a kind of integrated capacitance with polarity of the present invention includes the semiconductor substrate; The first vertical capacitor post was located on this semiconductor-based end, and this first vertical capacitor post is electrically connected institute mutually via a plurality of first connectors up and down by a plurality of first conducting blocks and constitutes; The second vertical capacitor post, itself and this first vertical capacitor post was set in parallel on this semiconductor-based end, and this second vertical capacitor post system is electrically connected institute mutually via a plurality of second connectors up and down by a plurality of second conducting blocks and constitutes; And a horizontal conductive plate, be located under this first vertical capacitor post and this second vertical capacitor post, and between this first vertical capacitor post and this second vertical capacitor post and between this semiconductor-based end.Wherein this first vertical capacitor post system is electrically connected with this conductive plate via at least one the 3rd connector.
For further specifying above-mentioned purpose of the present invention, design feature and effect, the present invention is described in detail below with reference to accompanying drawing.
Description of drawings
Fig. 1 is the partial structure enlarged side view of known high integration integrated capacitance.
Fig. 2 is the equivalent circuit diagram of the known integrated capacitance among Fig. 1.
Fig. 3 is the partial structure enlarged side view of high integration integrated capacitance of the present invention.
Fig. 4 is the equivalent circuit diagram of the integrated capacitance of the present invention among Fig. 3.
Fig. 5 is the end view of another preferred embodiment of the present invention.
Embodiment
See also Fig. 3, Fig. 3 is the partial structure enlarged side view of high integration integrated capacitance of the present invention.As shown in Figure 3, high integration integrated capacitance 3 of the present invention is to be made of a plurality of vertical metal plates 300 that are arranged in parallel and 320, and wherein unblanketed is vertical metal plate 320, represents that it is to be electrically connected a node A, hypographous is vertical metal plate 300, represents that it is to be electrically connected a Node B.Vertical metal plate 300 and 320 all is formed on the semiconductor substrate (not shown).Each vertical metal plate 300 all is made of a plurality of metal level 30a, 30b, 30c and 30d and metal plug 31a, the 31b and the 31c that are electrically connected a plurality of metal level 30a, 30b, 30c and 30d.Each vertical metal plate 320 all is made of a plurality of metal level 32a, 32b, 32c and 32d and metal plug 33a, the 33b and the 33c that are electrically connected a plurality of metal level 32a, 32b, 32c and 32d.It between the vertical metal plate 300 and 320 a dielectric layer (not shown).According to preferred embodiment of the present invention, the metal interconnecting processing procedure of a plurality of metal level 30a, 30b, 30c and the 30d of integrated capacitance 3 and a plurality of metal level 32a, 32b, 32c and 32d system and integrated circuit defines simultaneously to be finished, do not need extra light shield to come define pattern, therefore can save cost.
Still consult Fig. 3, high integration integrated capacitance 3 of the present invention includes a conductive plate 340 in addition, be located under vertical metal plate 300 and the vertical metal plate 320, and between vertical metal plate 300 and vertical metal plate 320 and (not shown) of the semiconductor-based end.Conductive plate 340 is constituted by electric conducting material, for example metal or polysilicon.According to preferred embodiment of the present invention, the ground floor plain conductor (metal 1) in the metal interconnecting processing procedure of conductive plate 340 and integrated circuit defines simultaneously to be finished.Seeing through at least one metal plug 340a between conductive plate 340 and the vertical metal plate 300 is electrically connected.Be dielectric layer between conductive plate 340 and the vertical metal plate 320, form insulation.
See also Fig. 4, Fig. 4 is the equivalent circuit diagram of the integrated capacitance 3 among Fig. 3.As previously mentioned, the vertical metal plate 320 of high integration integrated capacitance 3 of the present invention, it is electrical connection one node A, vertical metal plate 300, it is for being electrically connected a Node B.Between A node and B node, except the capacitance Cin that the self capacity structure is contributed, there is a parasitic capacitance CB to produce at the Node B end.Parasitic capacitance CB all is because conductive plate 340 is responded to generation with the (not shown) of the semiconductor-based end of ground connection.Hold then because covering of conductive plate 340 produces and there is parasitic capacitance at node A.Thus, make known integrated capacitance 3 owing to having only an end node that parasitic capacitance is arranged in design thereby having polarity, be fit to be applied to analog/digital converter (A/D converter) or digital/analog converter (D/A converter) or commutation circuit (switchcap circuit) field.
See also Fig. 5, Fig. 5 is the end view of another preferred embodiment of the present invention.As shown in Figure 5, high integration integrated capacitance 5 of the present invention is to be made of a plurality of vertical capacitor posts that are arranged in parallel or electrode column 500 and 520, wherein unblanketed is vertical electrode post 520, represent that it is to be electrically connected a node A, hypographous is vertical electrode post 500, represents that it is to be electrically connected a Node B. Vertical electrode post 500 and 520 all is formed on the semiconductor substrate (not shown).Each vertical electrode post 500 all is made of a plurality of metal derby 50a, 50b, 50c and 50d and metal plug 51a, the 51b and the 51c that are electrically connected a plurality of metal derby 50a, 50b, 50c and 50d.Each vertical electrode post 520 all is made of a plurality of metal derby 52a, 52b, 52c and 52d and metal plug 53a, the 53b and the 53c that are electrically connected a plurality of metal derby 52a, 52b, 52c and 52d.It between the vertical electrode post 500 and 520 a dielectric layer (not shown).A plurality of metal derby 50a, 50b, 50c and the 50d of integrated capacitance 5 and a plurality of metal derby 52a, 52b, 52c and 52d are that the metal interconnecting processing procedure with integrated circuit defines simultaneously and finishes, and do not need extra light shield to come define pattern, therefore can save cost.
High integration integrated capacitance 5 of the present invention includes a conductive plate 540 in addition, is located under vertical electrode post 500 and the vertical metal plate 520, and between vertical electrode post 500 and vertical electrode post 520 and (not shown) of the semiconductor-based end.Conductive plate 540 is constituted by electric conducting material, for example metal or polysilicon.According to preferred embodiment of the present invention, the ground floor plain conductor (metal 1) in the metal interconnecting processing procedure of conductive plate 540 and integrated circuit defines simultaneously to be finished.Seeing through at least one metal plug 540a between conductive plate 540 and the vertical metal plate 500 is electrically connected.Be dielectric layer between conductive plate 540 and the vertical electrode post 520, form insulation.
Compared to known technology, the present invention is the high integration integrated capacitance that can have polarity, can be applicable in the design of analog/digital converter (A/D converter) or digital/analog converter (D/A converter) or commutation circuit (switch cap circuit).The metal level of integrated capacitance is that the metal interconnecting processing procedure with integrated circuit defines simultaneously and finishes, and does not need extra light shield to come define pattern, therefore can save cost
The above only is preferred embodiment of the present invention, effectiveness of the present invention is not limited to aforesaid capacitance structure, every other known integrated capacitance structure, if it has bilateral parasitic capacitance, all can be according to the way of previous embodiment, between substrate and electric capacity, increase by a conductive plate, and form an integrated capacitance with polarity.Therefore, all integrated capacitances of finishing according to said method, and change and modify according to the equivalence that embodiments of the invention and claims are done, all should belong to the scope of present patent application.
Claims (23)
1. integrated capacitance that can have polarity includes:
The semiconductor substrate;
First vertical panel was located on this semiconductor-based end, and this first vertical panel system is electrically connected institute mutually via a plurality of first connectors up and down by a plurality of buss that are locked in a tie for first and constitutes;
Second vertical panel, itself and this first vertical panel were set in parallel on this semiconductor-based end, and this second vertical panel is to be electrically connected institute mutually via a plurality of second connectors up and down by a plurality of buss that are locked in a tie for second to constitute; And
One conductive plate is located under this first vertical panel and this second vertical panel, and between this first vertical panel and this second vertical panel and between this semiconductor-based end;
Wherein this second vertical panel system is electrically connected with this conductive plate via at least one the 3rd connector.
2. the integrated capacitance with polarity as claimed in claim 1 is characterized in that this conductive plate is made of metal.
3. the integrated capacitance with polarity as claimed in claim 1 is characterized in that, this conductive plate and this first vertical panel form by a dielectric layer and be electrically insulated.
4. the integrated capacitance with polarity as claimed in claim 1 is characterized in that, this first bus and this second bus all are made of metal.
5. the integrated capacitance with polarity as claimed in claim 1 is characterized in that, this first vertical panel and this second vertical panel are electrically insulated each other.
6. the integrated capacitance with polarity as claimed in claim 1 is characterized in that, this first vertical panel is electrically connected a node A, and this second vertical panel is electrically connected a Node B, and this integrated capacitance constitutes a parasitic capacitance in this Node B end and this semiconductor-based end.
7. the integrated capacitance with polarity as claimed in claim 6 is characterized in that, this first vertical panel is electrically connected a node A, and this second vertical panel is electrically connected a Node B, and this integrated capacitance there is no parasitic capacitance in this node A end and produces.
8. integrated capacitance that can have polarity includes:
The semiconductor substrate;
The first vertical capacitor post was located on this semiconductor-based end, and this first vertical capacitor post is to be electrically connected institute mutually via a plurality of first connectors up and down by a plurality of first conducting blocks to constitute;
The second vertical capacitor post, itself and this first vertical capacitor post was set in parallel on this semiconductor-based end, and this second vertical capacitor post is to be electrically connected institute mutually via a plurality of second connectors up and down by a plurality of second conducting blocks to constitute; And
One horizontal conductive plate is located under this first vertical capacitor post and this second vertical capacitor post, and between this first vertical capacitor post and this second vertical capacitor post and between this semiconductor-based end;
Wherein this second vertical capacitor post is electrically connected with this conductive plate via at least one the 3rd connector.
9. the integrated capacitance with polarity as claimed in claim 8 is characterized in that, this horizontal conductive plate is made of metal.
10. the integrated capacitance with polarity as claimed in claim 8 is characterized in that, is electrically insulated by dielectric layer formation between this horizontal conductive plate and this first vertical capacitor post.
11. the integrated capacitance with polarity as claimed in claim 8 is characterized in that, this first conducting block and this second conducting block all are made of metal.
12. the integrated capacitance with polarity as claimed in claim 8 is characterized in that, this first vertical capacitor post and this second vertical capacitor post are electrically insulated each other.
13. the integrated capacitance with polarity as claimed in claim 8, it is characterized in that, this first vertical capacitor post is electrically connected a node A, and this second vertical capacitor post is electrically connected a Node B, and this integrated capacitance constitutes a parasitic capacitance in this Node B end and this semiconductor-based end.
14. the integrated capacitance with polarity as claimed in claim 8 is characterized in that, this first vertical capacitor post is electrically connected a node A, and this second vertical capacitor post is electrically connected a Node B, and this integrated capacitance there is no parasitic capacitance in this node A end and produces.
15. a formation has the method for polarity integrated capacitance, includes:
The semiconductor substrate is provided, includes first vertical panel, it is electrically connected institute mutually via a plurality of first connectors up and down by a plurality of buss that are locked in a tie for first and constitutes; And second vertical panel, it is electrically connected institute mutually via a plurality of second connectors up and down by a plurality of buss that are locked in a tie for second and constitutes;
One conductive plate is provided, is located under this first vertical panel and this second vertical panel, and between this first vertical panel and this second vertical panel and between this semiconductor-based end; And
Be electrically connected this second vertical panel and this conductive plate via at least one the 3rd connector.
16. method as claimed in claim 15 is characterized in that, this conductive plate is made of metal.
17. method as claimed in claim 15 is characterized in that, this conductive plate and this first vertical panel form by a dielectric layer and are electrically insulated.
18. method as claimed in claim 15 is characterized in that, this first vertical panel is electrically connected a node A, and this second vertical panel is electrically connected a Node B, and this integrated capacitance constitutes a parasitic capacitance in this Node B end and this semiconductor-based end.
19. method as claimed in claim 15 is characterized in that, this first vertical panel system is electrically connected a node A, and this second vertical panel is electrically connected a Node B, and this integrated capacitance there is no parasitic capacitance in this node A end and produces.
20. a formation has the method for polarity integrated capacitance, includes:
The semiconductor substrate is provided;
Provide a conductive plate on this semiconductor-based end, this conductive plate was electrically insulated with this semiconductor-based end;
Provide a plurality of first electric capacity metalworks and a plurality of second electric capacity metalwork on this conductive plate, these a plurality of first electric capacity metalworks and parallel formation one integrated capacitance of these a plurality of second electric capacity metalworks;
These a plurality of first electric capacity metalworks and this conductive plate are electrically insulated; And
These a plurality of second electric capacity metalworks and this conductive plate are electrically connected.
21. method as claimed in claim 20 is characterized in that, this electric capacity metalwork is the vertical capacitor plate, and it is electrically connected institute mutually via a plurality of connectors up and down by a plurality of buss arranged side by side and constitutes.
22. method as claimed in claim 20 is characterized in that, this electric capacity metalwork is the vertical capacitor post, is electrically connected institute mutually via a plurality of connectors up and down by a plurality of conducting blocks and constitutes.
23. method as claimed in claim 20 is characterized in that, these a plurality of first electric capacity metalworks form the capacitance structure that is crisscross arranged with these a plurality of second electric capacity metalworks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021264244A CN1467843A (en) | 2002-07-11 | 2002-07-11 | Integrated capacitor having polarity |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA021264244A CN1467843A (en) | 2002-07-11 | 2002-07-11 | Integrated capacitor having polarity |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1467843A true CN1467843A (en) | 2004-01-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA021264244A Pending CN1467843A (en) | 2002-07-11 | 2002-07-11 | Integrated capacitor having polarity |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1467843A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019127489A1 (en) * | 2017-12-29 | 2019-07-04 | 华为技术有限公司 | Capacitor |
-
2002
- 2002-07-11 CN CNA021264244A patent/CN1467843A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019127489A1 (en) * | 2017-12-29 | 2019-07-04 | 华为技术有限公司 | Capacitor |
| CN111357103A (en) * | 2017-12-29 | 2020-06-30 | 华为技术有限公司 | Capacitor with a capacitor element |
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