CN1466280A - Method and device for inversing optical fibre node - Google Patents
Method and device for inversing optical fibre node Download PDFInfo
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- CN1466280A CN1466280A CNA021404011A CN02140401A CN1466280A CN 1466280 A CN1466280 A CN 1466280A CN A021404011 A CNA021404011 A CN A021404011A CN 02140401 A CN02140401 A CN 02140401A CN 1466280 A CN1466280 A CN 1466280A
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Abstract
This invention relates to a method and device for fiber nexus conversion of electric communication technology, in which, nexuses are connected by fibers, the frame interface on physical layer chip of nexus detects the fiber status, in the fiber ring network applying dual ring topology, if interrupt happens, it is reported to CPU, if broken fiber happens, the physical chip will report it, CPU will rectify parameters of a register, physical chip on any mexus is composed of two chips called HARN and HARNMATE, connected by a MATE interface. If the MATE interface detect that mode register changes, it will convert wires at the packet end or packet gap.
Description
Technical field
The present invention relates to electrical communication technology, relate in particular to a kind of Fiber Node reverse method and device.
Background technology
The SDH multiplexing segment protect is meant by the K byte in the multiplex section in the expense finishes the series of protocols handshake procedure; make originally to transfer on the protection route and transmit at the service signal that transmits on the impaired optical fiber; thereby a kind of protected mode that makes original business proceed to transmit and be unlikely to interrupt; topological mode difference according to networking; multiplex section protection can simply be divided into linear multiplex section protection mode and ring property multiplex section protection mode; multiplex section protective ring can be divided into two fine and four fine two classes according to number of fibers, and two fine rings are divided into multiplex section privacy protection two fine rings and multi-section shared protection two fine rings according to service route.
Multiplex section two fine protection rings are a kind of bidirectional protective rings.Share; a capacity part that refers on an optical fiber is used as the protection path; and a part is used for regular traffic as active channel in addition; and when disconnected fibre takes place; remove to protect regular traffic on the impaired optical fiber with the protection path on the optical fiber on other sections; for example, the two-fibre two-way multi-section shared protection ring of a STM-N, its total N AU-4.Be numbered in the clockwise direction 1 to the AU-4 time slot arrangement of N/2 as active channel, be numbered N/2+1 to the AU-4 time slot arrangement of N as protecting path.The time slot of optical fiber in the counterclockwise direction is same.The AU-4 active channel that is numbered m is protected by protection path (N/2+m) individual AU-4 in the opposite direction of correspondence.Working service two-way transmission in each section in this in addition protection rings: the service signal that enters is then advanced in the rightabout active channel in same section at a direction of the active channel with it related service signal of going out of advancing.
When protection path when not being used as the information of the path of resuming work, i.e. normal operating conditions, they also can be used to carry extra information service.Under the situation that protection is switched, the service access in the active channel is to the protection path, and any extra traffic information all will shift out the protection path.
Multiplex section two fine protection rings need be used the APS agreement, and the SONET/SDH network provides the APS with performance monitoring and self-healing ability, and APS has following function:
1, the overhead byte by SDH provides performance degradation monitoring and malfunction monitoring and isolation merit
Can;
2, in breaking down back assurance 50ms, physical layer recovers;
3, the protection of multiple spot inefficacy.
The protection reversed process of two-fibre two-way multi-section protection rotating loop is as shown in Figure 1; two-fibre two-way multi-section protection rotating loop is in the two-fibre two-way multi-section guard ring; half distributes to service channel with the capacity of each transmission direction optical fiber, and half distributes to the protection passage in addition.Under the normal condition, shown in Fig. 1 (a), advancing ring from node A is that the service signal of purpose transmits in the direction of the clock along S1/P2 optical fiber with node C; From node C advance ring with node A be purpose service signal then along S2/P1 optical fiber by transmission counterclockwise.
Two optical fiber are cut off simultaneously when between Node B, C, and shown in Fig. 1 (b), the switch of switching of Node B and node C is linked up S1/P2 optical fiber and S2/P1 optical fiber.To advance the protection time slot that service signal time slot that ring sends here along S1/P2 optical fiber is transferred to S2/P1 optical fiber from node A in Node B, be sent to node C.To advance service signal time slot that ring sends along S2/P1 optical fiber from this node at node C and switch protection time slot, be sent to node A to S1/P2 optical fiber.
Because the business time-slot of each direction and protection time slot transmit on same optical fiber in the two-fibre two-way ring, i.e. not only transmitting business signal but also transmit guard signal on an optical fiber.At this moment, no matter be that receiver, transmitter, optical cable or node break down, always can influence service aisle and protection passage simultaneously, and always depend on the overhead byte of SDH, performance degradation monitoring and malfunction monitoring are provided.
Summary of the invention
The object of the present invention is to provide a kind of reliability height, well behaved Fiber Node to switch scheme.
The technical solution adopted in the present invention is:
This Fiber Node reverse method is characterized in that: in the optical fiber ring network of a, dicyclo type topological structure, link to each other physics on the node between node by optical fiber
The frame interface of layer chip detects the state of optical fiber, produces to interrupt reporting CPU to do processing; B, when disconnected fine the generation, physical chip can report disconnected fine, CPU can remove to revise mode then
The parameter of register, circuit is switched at the bag tail or the Inter-packet gap of data, adopts physics
Layer chip switch circuit, the data on the disconnected fine ring are all imported on another ring, weigh
Newly constituted a closed loop; C, when optical fiber recover normal after, physical chip detects data flow, just notifies the CPU will
The parameter of mode register is restored, and switches to normal forwarding circuit;
The sampling clock frequency of described physical chip inside, when adopting different circuits, corresponding sampling clock is inequality, read the clock selecting of clock by clock selection circuit, get an identical clock of reading, select active data, give follow-up resume module.
This Fiber Node changeover apparatus according to above-mentioned Fiber Node reverse method, it is characterized in that: in the optical fiber ring network that comprises dicyclo type topological structure, link to each other by optical fiber between node, the physical chip of arbitrary node all is made up of two chip blocks, be called HARN and HARNMATE, HARN links to each other by gigabit MATE interface with the HARNMATE chip, and the MATE interface comprises two parts: TOMI and FRMI; The TOMI module is finished external transmission data, and the FRMI module receives external data; Also there is the circuit that directly feeds the FRMI module in MATE interface inside separately, promptly switches circuit from the TOMI module; On the receiving terminal FRMI of MATE interface, there is monitoring module to detect from the data on the circuit, when optical fiber ruptures, node reports disconnected fine, the parameter of the mode register of HARN and HARNMATE chip is modified, circuit is switched, and the data on the disconnected fine ring are all imported by switching on another ring that circuit constitutes; After the optical fiber of fracture recovered normally, the node of originally switching can switch back the normal circuit of transmitting; Line switching is finished in MATE interface inner control, and the MATE interface detects the mode register and changes, and just carries out line switching at bag tail or Inter-packet gap;
Described MATE interface detects the mode register for switching parameter when effective, the MATE interface will prepare to carry out line switching so, if this moment, the TOMI module sent packet, wait until that so this packet sends end, no matter whether also have data to exist in the FIFO memory this moment, and TOMI forces chip to enter into the SEND_SYNC state, sends the SYNC sequence code always, freezed the transmission of packet, until switching generation; Be under the freezing data bag state in the TOMI module, whether the FRMI module of also always monitoring this film is receiving packet, if, receive complete packet by the time after, line switching just takes place; If this moment, the TOMI module did not send packet, whether its FRMI module of just beginning to monitor this film is receiving packet so, if, receive packet by the time, line switching just takes place;
When linking to each other by high speed deserializer serdes between described intranodal HARN and the HARNMATE, if the optical fiber between the high speed deserializer serdes, it is the fibercuts of intra-node, monitoring module on the FRMI will be received interrupt signal, and report interruption, CPU has no progeny in receiving, the mode register that will revise this chip is wrap, by the mode of following, the pattern information mode of this chip bring on this node to sheet, by the extraction of monitoring module, give cpu i/f to sheet with the pattern information that extracts to pattern information, revising corresponding mode register by CPU is wrap, and this node has entered switches circuit; After the optical fiber that ruptures between intranodal high speed deserializer serdes recovers normally, also be to go to extract the pattern information of carrying in the data flow by monitoring module, according to pattern information, HARN that intranodal has been switched and HARNMATE can switch back the normal circuit of transmitting, and this node recovers the normal circuit of transmitting;
When having disconnected fibre to take place between described node, the frame interface of physical chip is not received data flow for a long time on the node, will produce regularly and interrupt, report the CPU fine information of breaking, CPU can go to revise the parameter of this node mode register then, when rupturing for single fiber between node, descendant node does not receive data flow, the frame interface of descendant node will send regularly and interrupt, notice CPU removes to revise the mode register of HARN or HARNMATE, sheet is revised corresponding mode register parameters by the mode of following in this descendant node, descendant node enters switches circuit, will be carried the IPS message of switch messages by the software of this descendant node and deliver to this disconnected fine upstream node, after upstream node is received the IPS message, equally, CPU will remove to revise its mode register, and this upstream node has also entered the node switches process; When two fibres all ruptured between node, the node at disconnected fine two did not all receive data flow, and they all can be owing to overtime interruption makes CPU remove to revise their mode register, and these two nodes enter respectively switches circuit; Behind the single fiber or the fine recovery normally of double break of fracture, node is received data flow, and frame interface detects data flow, produces to recover to interrupt, and requires CPU to remove to revise corresponding mode register, enters normal operating state;
The sampling clock frequency of described FRMI, have nothing in common with each other during when HARN directly links to each other with HARNMATE or when HARN links to each other by high speed deserializer serdes with HARNMATE or at line switching, the sampling clock of corresponding three pairs of FIFOs memories is inequality, read the clock selecting of clock by clock selection circuit, get an identical clock of reading, from corresponding three pairs of FIFOs memories, select active data, give follow-up resume module;
The sampling clock frequency of described FRMI, when HARN linked to each other by high speed deserializer serdes with HARNMATE, FRMI received from the data to sheet, and sampling clock is 62.5M, two clock: frm1clk, frm2clk that phase place is opposite; When HARN directly linked to each other with HARNMATE, FRMI received from the data to sheet, and sampling clock frm1clk is 125M; When line switching, FRMI receives the data from this film, sampling clock mateclk also is 125M, but with frm1clk be fully asynchronous, read the clock selecting of clock by clock selection module, the generation of reading clock determines according to chip status: switch when entering, clock adopts the two divided-frequency clock mateclkp of mateclk; Switch when withdrawing from, when HARN linked to each other by high speed deserializer serdes with HARNMATE, clock adopted frm1clk, or when HARN directly linked to each other with HARNMATE, clock adopted the two divided-frequency clock frm1clkp of frm1clk, and frequency all is 62.5M;
In the described clock selection circuit, adopt high speed deserializer serdes and switch enable signal wrap_en and select clock, produce an inner derived clock CLKF, in the moment that applied clock switching signal index1_a, index2_a control clock switches, use following control structure:
CLKF＝(index1_a∩CLKA)∪(index2_a∩CLKB)；
CLKB is the two divided-frequency clock mateclkp of sampling clock mateclk;
When HARN linked to each other by high speed deserializer serdes with HARNMATE, CLKA was clock frm1clk; When HARN directly linked to each other with HARNMATE, CLKA was the two divided-frequency clock frm1clkp of clock frm1clk;
The internal clocking CLKF that clock selection circuit produces goes to read three pairs of data in the FIFOs memory simultaneously, three circuit-switched data of reading select module DAT_SEL according to clock switching signal index1_a in data, index2_a does selection, selecting a circuit-switched data gives module SYNC_DTC and does processing, when the mode register has been revised as wrap, and, module SYNC_DTC detects bag tail EOP, or during the SYNC sequence code, reset signal wrap_rst_n is switched in generation, after state variation, promptly, switch enable signal wrap_en saltus step is arranged, the data of storing on this paths are eliminated, module and memory element are subjected to switching the effect of reset signal wrap_rst_n, write reset values.
Beneficial effect of the present invention is: in the present invention, when disconnected fibre took place, physical chip can report disconnected fine, and CPU can go to revise the parameter of mode register then, switches circuit by physical chip, has constituted a closed loop again, guarantees transfer of data; After optical fiber recovers normally, physical chip detects data flow, just notify CPU that the parameter of mode register is restored, the node of originally switching can switch back the normal circuit of transmitting, and adopts this physical chip can realize fast reaction, when having disconnected fibre to take place between node, make the rapid reconstruct of loop closed loop, and this system need not to depend on overhead byte carry out performance and and malfunction monitoring, and, the MATE interface detects the mode register and changes, will be at the bag tail, or Inter-packet gap carries out line switching, when guaranteeing that circuit switches, the integrality that keeps data, therefore, reliability height of the present invention, functional, make full use of bandwidth, improve the broadband utilance;
The problem of clock for a long time during when HARN directly links to each other with HARNMATE or when HARN links to each other by high speed deserializer serdes with HARNMATE or at line switching etc. under the situation, identical the read clock of clock of reading that adopts that clock switch circuit generates as corresponding FIFOs, therefrom select active data, give follow-up resume module, simplify processing procedure greatly, improved practicality of the present invention;
To detect the mode register effective for switching parameter when the MATE interface, the MATE interface will prepare to carry out line switching so, if this moment, the TOMI module sent packet, wait until that so this packet sends end, no matter whether also have data to exist in the FIFO memory this moment, and TOMI forces chip to enter into the SEND sync state, sends the SYNC sequence code always, freezed the transmission of packet, until switching generation; Be under the freezing data bag state in the TOMI module, whether the FRMI module of also always monitoring this film is receiving packet, if, receive complete packet by the time after, line switching just takes place; If this moment, the TOMI module did not send packet, whether it just begins to monitor the FRMI module of this film at the reception packet so, if, by the time receive packet, line switching just takes place, and like this, the MATE interface can not received broken bag at the switching edge, and, the internal clocking CLKF that clock selection circuit produces goes to read three pairs of data in the FIFOs memory simultaneously, after selecting a circuit-switched data and give module SYNC_DTC and go to handle according to the clock switching signal, when the mode register has been revised as wrap, and, module SYNC_DTC detects bag tail EOP, or during the SYNC sequence code, generate and switch reset signal, after state variation, the data of storing on this paths are eliminated, module and memory element are subjected to switching the effect of reset signal, write reset values, and be same, guaranteed under circuit switches, can not receive remaining bag.
In a word, reliability height of the present invention, functional, make full use of bandwidth, improve the broadband utilance; When circuit switches, can not receive remaining bag, guaranteed the integrality of data passes as far as possible.
Description of drawings
Fig. 1 is SDH two-direction duplexing section protection rotating loop schematic diagram;
Fig. 2 is physical chip HARN between two nodes and a HARNMATE connection diagram in the optical fiber ring network;
Fig. 3 is the physical chip connection diagram between two nodes in the optical fiber ring network;
Fig. 4 is the clock selection circuit structural representation;
Fig. 5 is the clock selection circuit sequential chart;
Data processing principle schematic diagram when Fig. 6 is line switching;
Data time sequence figure when Fig. 7 is line switching.
Embodiment
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
According to Fig. 2, Fig. 3, Fig. 4 and Fig. 6, in the optical fiber ring network that adopts dicyclo type topological structure, inner and outer ring can transmits data packets and controlling packet, can be on another ring in any one ring transmitting data bag transmission controlling packets, the transmission direction of inner and outer ring is opposite, link to each other by optical fiber between node, the frame interface of physical chip detects the state of optical fiber on the node, produces to interrupt reporting CPU to do processing;
When disconnected fine the generation, physical chip can report disconnected fine, and can to go to revise the parameter of mode register be wrap to CPU then; After optical fiber recovered normally, physical chip detected data flow, just notified CPU that the parameter of mode register is restored and was normal;
As shown in Figures 2 and 3, the physical chip of arbitrary node all is made up of two chip blocks in the optical fiber ring network, is called HARN and HARNMATE, and HARN links to each other by gigabit MATE interface with the HARNMATE chip; The MATE interface comprises two parts: TOMI and FRMI; The TOMI module is finished external transmission data, and the FRMI module receives external data, as circuit 1-1,2-1 among Fig. 2 and Fig. 3; In addition, at inner circuit 1-2, the 2-2 that directly feeds the FRMI module from the TOMI module that also exist separately, these two circuits are used to transmit data for switching circuit when switching;
As shown in Figure 3, two nodes 1,2 in the looped network, link to each other by optical fiber between node, such as I_12, O_21 all is optical fiber, the data transfer direction of two rings is opposite, has monitoring module to detect to the data on the sheet circuit control character that monitoring module sends from 1-1,2-1 circuit on the receiving terminal FRMI of the MATE of HARM chip interface, comprise in EOP, the SYNC sequence code and extract pattern information, and report CPU to remove to revise mode register sheet.
When linking to each other by high speed deserializer serdes between intranodal HARN and the HARNMATE, if the optical fiber between the high speed deserializer serdes, it is the fibercuts of intra-node, monitoring module on the FRMI will be received the Frm_los interrupt signal, and report interruption, CPU has no progeny in receiving, the mode register that will revise this chip is wrap, by the mode of following, the pattern information mode of this chip bring on this node to sheet, by the extraction of monitoring module, give cpu i/f to sheet with the pattern information that extracts to pattern information, revising corresponding mode register by CPU is wrap, and this node has entered switches circuit; After the optical fiber that ruptures between intranodal high speed deserializer serdes recovers normally, also be to go to extract the pattern information of carrying in the data flow by monitoring module, according to pattern information, HARN that intranodal has been switched and HARNMATE can switch back the normal circuit of transmitting, and this node recovers the normal circuit of transmitting.
When internodal optical fiber ruptures, monitoring module can't detect data flow in a period of time, show that optical fiber ruptures, this node reports disconnected fine, the parameter of the mode register of HARN and HARNMATE chip is modified, circuit is switched, data on the disconnected fine ring are all imported on another ring, parameter to the mode register on the sheet also is modified, enter and switch circuit, like this, switch circuit by physical chip, constituted a closed loop again, guarantee transfer of data, lack obliterated data as far as possible, such as: as shown in Figure 3, when rupturing for single fiber, when 0_21 optical fiber ruptures, the frame interface of node 1 all can't detect data flow in a period of time, frame interface will report interruption so, the mode register that CPU removes to revise HARN is the wrap pattern, TOMI transmitting terminal among the HARN is when sending data, be sent to simultaneously and transmit circuit and switch circuit, HARNMATE extracts the pattern information of carrying in the HARN data flow, and reports CPU to remove to revise its mode register, in this mode of following, HARN and HARNMATE are switched to by regular link respectively and switch circuit, HARN, HARNMATE is respectively by 1-1, the 2-1 circuit switches to switches circuit 1-2,2-2, when this node entered switch after, the software that is advanced by this node will carry the IPS bag of switch messages and send, in case node 2 receives this IPS bag, will report CPU to remove to revise the mode register, has constituted a closed loop so again; After the optical fiber that ruptures between node recovered normally, the node of originally switching can switch back the normal circuit of transmitting.
When two fibres all ruptured between node, the node at disconnected fine two did not all receive data flow, and they all can be owing to overtime interruption makes CPU remove to revise their mode register, and these two nodes enter respectively switches circuit; Behind the single fiber or the fine recovery normally of double break of fracture, node is received data flow, and frame interface detects data flow, produces to recover to interrupt, and requires CPU to remove to revise corresponding mode register, enters normal operating state.
Above-mentioned line switching is mainly finished in MATE interface inner control, it is effective for switching parameter that the MATE interface detects the mode register, will be at the bag tail, or Inter-packet gap carries out line switching, when the MATE interface will be prepared to carry out line switching, if this moment, the TOMI module sent packet, wait until that so this packet sends end, no matter whether also have data to exist in the FIFO memory this moment, TOMI forces chip to enter into the SENLSYNC state, send the SYNC sequence code always, freezed the transmission of packet, until switching generation; Be under the freezing data bag state in the TOMI module, whether the FRMI module of also always monitoring this film is receiving packet, if, receive complete packet by the time after, line switching just takes place; If this moment, the TOMI module did not send packet, whether its FRMI module of just beginning to monitor this film is receiving packet so, if, receive packet by the time, line switching just takes place; After the mode register is modified, corresponding variation can take place in the mode register mode_op of chip internal, three bit register mode_op[2:0 of chip internal] be the one_hot type, effective when promptly having only one to be high-order, mode_op[2] to represent chip mode be to switch, mode_op[0] be normal.
Under Switch mode, FRMI receives the data flow from circuit 1-2,2-2, otherwise it just receives the data flow from circuit 1-1,2-1, because the clock of TOMI is 125M, and whether the clock among the FRMI will be according to adopting high speed deserializer serdes to decide; When HARN links to each other by high speed deserializer serdes with HARNMATE, the clock of FRMI is dominant frequency 62.5M so, two clocks that phase place is opposite; When HARN directly links to each other with HARNMATE, do not pass through serdes, the clock of FRMI is exactly 125M so, but with the clock of TOMI be fully asynchronous, so can not directly send into FRMI to the dateout of TOMI as input, at first must make clock to the data of different clock-domains handles, that is to say, the sampling clock frequency of FRMI, when HARN directly links to each other with HARNMATE, or when HARN links to each other by high speed deserializer serdes with HARNMATE, or when line switching, have nothing in common with each other, the sampling clock of corresponding three pairs of FIFOs memories is inequality, read the clock selecting of clock by clock selection circuit, get an identical clock of reading, from corresponding three pairs of FIFOs memories, select active data, give follow-up resume module.
Its concrete processing method is: the sampling clock frequency of FRMI, when HARN links to each other by high speed deserializer serdes with HARNMATE, FRMI receives from the data to sheet, and sampling clock is 62.5M, two clock: frm1clk, frm2clk that phase place is opposite; When HARN directly linked to each other with HARNMATE, FRMI received from the data to sheet, and sampling clock frm1clk is 125M; When line switching, FRMI receives the data from this film, sampling clock mateclk also is 125M, but with frm1clk be fully asynchronous, read the clock selecting of clock by clock selection module, the generation of reading clock determines according to chip status: switch when entering, clock adopts the two divided-frequency clock mateclkp of mateclk; Switch when withdrawing from, when HARN links to each other by high speed deserializer serdes with HARNMATE, clock adopts frm1clk, or when HARN directly links to each other with HARNMATE, clock adopts the two divided-frequency clock frm1clkp of frm1clk, frequency all is 62.5M, as shown in Figure 4, in the clock selection circuit, adopt high speed deserializer serdes and switch enable signal wrap_en and select clock, produce an inner derived clock CLKF, because the clock generating burr can seriously influence the function of circuit, can not adopt common multiplexer circuit MUX so do clock selecting, adopt the deburring circuit, connect high speed deserializer serdes, be that serdes is 1 o'clock, when chip enters when switching, to switch enable signal wrap_en and become high level by low transition, clock switches to mateclkp by frm1clk; In like manner, when chip withdraws from when switching, switch enable signal wrap_en and become low level by the high level saltus step, clock switches to frm1clk by mateclkp; At serdes is 0 o'clock, when chip enters when switching, switches enable signal wrap_en and becomes high level by low transition, and clock switches to mateclkp by frm1clkp; In like manner, when chip withdraws from when switching, switch enable signal wrap_en and become low level by the high level saltus step, clock switches to frm1clkp by mateclkp; The moment of switching is not to switch enable signal wrap_en variation constantly, adopts index1_a, index2_a to go to control the moment that clock switches, and its control structure is as follows:
Rega＝(-wrap_en)∩(-index2_a)；
Regb＝wrap_en∩(-index1_a)；
Always@(negedge?CLKA)
Index1_a＜=rega; (represent when the CLKA trailing edge, rega imports Index1_a herein)
Always@(negedge?CLKB)
Index2_a＜=rega; (represent when the CLKB trailing edge, regb imports Index2_a herein)
CLKF＝(index1_a∩CLKA)∪(index2_a∩CLKB)；
CLKB is the two divided-frequency clock mateclkp of sampling clock mateclk;
When HARN linked to each other by high speed deserializer serdes with HARNMATE, CLKA was clock frm1clk; When HARN directly links to each other with HARNMATE, CLKA is the two divided-frequency clock frm1clkp of clock frm1clk, above control mode has guaranteed the integrality of clock, can not produce burr, the sequential chart of this clock selection circuit as shown in Figure 5, like this, the internal clocking CLKF that clock selection circuit produces goes to read three pairs of data in the FIFOs memory simultaneously, three circuit-switched data of reading select module DAT_SEL to do selection according to clock switching signal index1_a, index2_a in data, select a circuit-switched data and give module SYNC_DTC and do processing.
After clock switches, produce and switch reset signal wrap_rst_n, this reset signal has kept several clock cycle effective, as shown in Figure 6, when handling to receiving data, at first, the data that receive are write among the FIFOs, the internal clocking CLKF that produces according to clock selection circuit then, remove to read UO_125 simultaneously, UO_625 and UO_WRAP, three circuit-switched data of reading select module DAT_SEL to do selection according to the clock switching signal in data, selecting a circuit-switched data gives module SYNC_DTC and does processing, when the mode register has been revised as wrap, and, module SYNC_DTC detects bag tail EOP, or during the SYNC sequence code, produce and effectively switch enable signal wrap_en signal, clock selection module CLK_SEL produces clock switching signal index1_a according to switching enable signal wrap_en signal, index2_a, and reset signal Wrap_rst_n is switched in generation, in module SYNC DTC, there is several levels of data to handle, wherein there are some memory cell, as shown in Figure 6, in third level storage, detect EOP, or SYNC sequence code, will produce and effectively switch enable signal wrap_en signal, this signal directly goes to control the switching of clock, also determined data to select the output of module DAT_SEL, as can see from Figure 6, output to from the data of FIFOs between the third level storage of module SYNC_DTC and have long path, wherein also stored plurality of data, and these data are to switch under the enable signal wrap_en saltus step state before, so after state variation, switch enable signal wrap_en saltus step is arranged, the data of storing on this paths all should be eliminated, this has just guaranteed under circuit switches, can not receive remaining bag, among Fig. 6, grey module and memory element all are subjected to switching the effect of reset signal wrap_rst_n signal, write reset values.
It is worthy of note, cause a small amount of packet loss at reverse side along meeting, especially under the situation that pattern is followed, pattern information is delivered to sheet, revise the mode register by CPU again, the time is longer, causes HARN and HARNMATE to enter/withdraw from being out of step of switching, such as: when being introduced into, switches HARN, it self carries out synchronizing process, and HARNMATE still is in normal mode, if it is also sending data, this bag may just have been lost so, lost part as shown in Figure 7, but in case switch and to finish all is consistent to the subsequent treatment of data, as normal flow, so do not have the packet loss phenomenon again.
Claims (10)
1. Fiber Node reverse method is characterized in that:
In the optical fiber ring network of a, dicyclo type topological structure, link to each other by optical fiber between node, the frame interface of physical chip detects the state of optical fiber on the node, produces to interrupt reporting CPU to do processing;
B, when disconnected fine the generation, physical chip can report disconnected fine, CPU can go to revise the parameter of mode register then, circuit is switched at the bag tail or the Inter-packet gap of data, adopt the circuit of switching of physical chip, data on the disconnected fine ring are all imported on another ring, reconstituted a closed loop;
C, when optical fiber recover normal after, physical chip detects data flow, just notifies CPU that the parameter of mode register is restored, and switches to normal forwarding circuit.
2. Fiber Node reverse method according to claim 1, it is characterized in that: the sampling clock frequency of described physical chip inside, when adopting different circuits, corresponding sampling clock is inequality, read the clock selecting of clock by clock selection circuit, get an identical clock of reading, select active data, give follow-up resume module.
3. the Fiber Node changeover apparatus of a Fiber Node reverse method according to claim 1, it is characterized in that: in the optical fiber ring network that comprises dicyclo type topological structure, link to each other by optical fiber between node, the physical chip of arbitrary node all is made up of two chip blocks, be called HARN and HARNMATE, HARN links to each other by gigabit MATE interface with the HARNMATE chip, and the MATE interface comprises two parts: TOMI and FRMI; The TOMI module is finished external transmission data, and the FRMI module receives external data; Also there is the circuit that directly feeds the FRMI module in MATE interface inside separately, promptly switches circuit from the TOMI module; On the receiving terminal FRMI of MATE interface, there is monitoring module to detect from the data on the circuit, when optical fiber ruptures, node reports disconnected fine, the parameter of the mode register of HARN and HARNMATE chip is modified, circuit is switched, and the data on the disconnected fine ring are all imported by switching on another ring that circuit constitutes; After the optical fiber of fracture recovered normally, the node of originally switching can switch back the normal circuit of transmitting; Line switching is finished in MATE interface inner control, and the MATE interface detects the mode register and changes, and just carries out line switching at bag tail or Inter-packet gap.
4. Fiber Node changeover apparatus according to claim 3, it is characterized in that: described MATE interface detects the mode register for switching parameter when effective, the MATE interface will prepare to carry out line switching so, if this moment, the TOMI module sent packet, wait until that so this packet sends end, no matter whether also have data to exist in the FIFO memory this moment, TOMI forces chip to enter into the SEND_SYNC state, send the SYNC sequence code always, freezed the transmission of packet, until switching generation; Be under the freezing data bag state in the TOMI module, whether the FRMI module of also always monitoring this film is receiving packet, if, receive complete packet by the time after, line switching just takes place; If this moment, the TOMI module did not send packet, whether its FRMI module of just beginning to monitor this film is receiving packet so, if, receive packet by the time, line switching just takes place.
5. Fiber Node changeover apparatus according to claim 3, it is characterized in that: when linking to each other by high speed deserializer (serdes) between described intranodal HARN and the HARNMATE, if the optical fiber between the high speed deserializer (serdes), it is the fibercuts of intra-node, monitoring module on the FRMI will be received interrupt signal, and report interruption, CPU has no progeny in receiving, the mode register that will revise this chip is wrap, by the mode of following, the pattern information mode of this chip bring on this node to sheet, to sheet by the extraction of monitoring module to pattern information, give cpu i/f with the pattern information that extracts, revising corresponding mode register by CPU is wrap, and this node has entered switches circuit; After the optical fiber of fracture between intranodal high speed deserializer (serdes) recovers normally, also be to go to extract the pattern information of carrying in the data flow by monitoring module, according to pattern information, HARN that intranodal has been switched and HARNMATE can switch back the normal circuit of transmitting, and this node recovers the normal circuit of transmitting.
6. according to claim 3 or 5 described Fiber Node changeover apparatus, it is characterized in that: when having disconnected fibre to take place between described node, the frame interface of physical chip is not received data flow for a long time on the node, will produce regularly and interrupt, report the CPU fine information of breaking, CPU can go to revise the parameter of this node mode register then, when rupturing for single fiber between node, descendant node does not receive data flow, the frame interface of descendant node will send regularly and interrupt, notice CPU removes to revise the mode register of HARN or HARNMATE, what this descendant node was interior revises corresponding mode register parameters to sheet by the mode of following, descendant node enters switches circuit, to carry the IPS message of switch messages by the software of this descendant node and deliver to this disconnected fine upstream node, after upstream node is received the IPS message, same, CPU will remove to revise its mode register, and this upstream node has also entered the node switches process; When two fibres all ruptured between node, the node at disconnected fine two did not all receive data flow, and they all can be owing to overtime interruption makes CPU remove to revise their mode register, and these two nodes enter respectively switches circuit; Behind the single fiber or the fine recovery normally of double break of fracture, node is received data flow, and frame interface detects data flow, produces to recover to interrupt, and requires CPU to remove to revise corresponding mode register, enters normal operating state.
7. Fiber Node changeover apparatus according to claim 3, it is characterized in that: the sampling clock frequency of described FRMI, when HARN directly links to each other with HARNMATE or at HARN and HARNMATE, have nothing in common with each other during when linking to each other or at line switching by high speed deserializer (serdes), the sampling clock of corresponding three pairs of FIFOs memories is inequality, read the clock selecting of clock by clock selection circuit, get an identical clock of reading, from corresponding three pairs of FIFOs memories, select active data, give follow-up resume module.
8. Fiber Node changeover apparatus according to claim 7, it is characterized in that: the sampling clock frequency of described FRMI, at HARN and HARNMATE by high speed deserializer (serdes) when linking to each other, FRMI receives from the data to sheet, sampling clock is 62.5M, two clock: frm1clk, frm2clk that phase place is opposite; When HARN directly linked to each other with HARNMATE, FRMI received from the data to sheet, and sampling clock frm1clk is 125M; When line switching, FRMI receives the data from this film, sampling clock mateclk also is 125M, but with frm1clk be fully asynchronous, read the clock selecting of clock by clock selection module, the generation of reading clock determines according to chip status: switch when entering, clock adopts the two divided-frequency clock mateclkp of mateclk; Switch when withdrawing from, when linking to each other, clock adopts frm1clk by high speed deserializer (serdes) for HARN and HARNMATE, or when HARN directly links to each other with HARNMATE, the two divided-frequency clock frm1clkp of clock employing frm1clk, frequency all is 62.5M.
9. Fiber Node changeover apparatus according to claim 8, it is characterized in that: in the described clock selection circuit, adopt high speed deserializer (serdes) and switch enable signal (wrap_en) and select clock, produce an inner derived clock (CLKF), in the moment that applied clock switching signal (index1_a), (index2_a) control clock switch, use following control structure:
CLKF＝(index1_a∩CLKA)∪(index2_a∩CLKB)；
CLKB is the two divided-frequency clock mateclkp of sampling clock mateclk;
When HARN and HARNMATE by high speed deserializer (serdes) when linking to each other, CLKA is clock frm1clk; When HARN directly linked to each other with HARNMATE, CLKA was the two divided-frequency clock frm1clkp of clock frm1clk.
10. Fiber Node changeover apparatus according to claim 9, it is characterized in that: the internal clocking (CLKF) that clock selection circuit produces goes to read three pairs of data in the FIFOs memory simultaneously, three circuit-switched data of reading select module (DAT_SEL) according to clock switching signal (index1_a) in data, (index2_a) do selection, selecting a circuit-switched data gives module (SYNC_DTC) and does processing, when the mode register has been revised as wrap, and, module (SYNC_DTC) detects bag tail (EOP), or during the SYNC sequence code, reset signal (wrap_rst_n) is switched in generation, after state variation, promptly, switch enable signal (wrap_en) saltus step is arranged, the data of storing on this paths are eliminated, and module and memory element are subjected to switching the effect of reset signal (wrap_rst_n), write reset values.
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| CNB021404011A CN1214576C (en) | 2002-06-22 | 2002-06-22 | Method and device for inversing optical fibre node |
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| CNB021404011A CN1214576C (en) | 2002-06-22 | 2002-06-22 | Method and device for inversing optical fibre node |
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| CN100336357C (en) * | 2005-08-25 | 2007-09-05 | 上海交通大学 | Redundant crossing ring data bus network topological structure |
| CN100496009C (en) * | 2004-11-04 | 2009-06-03 | 华为技术有限公司 | Node protection inversion method and device in RPR network |
| CN101494858B (en) * | 2008-01-21 | 2011-01-05 | 中兴通讯股份有限公司 | Method, apparatus and system for encipher recovery when switching user side processor |
| CN101242252B (en) * | 2007-02-08 | 2012-05-09 | 北京天融信网络安全技术有限公司 | Method for realizing dual-link redundancy backup of network device based on Combo interface |
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| CN100336357C (en) * | 2005-08-25 | 2007-09-05 | 上海交通大学 | Redundant crossing ring data bus network topological structure |
| CN101242252B (en) * | 2007-02-08 | 2012-05-09 | 北京天融信网络安全技术有限公司 | Method for realizing dual-link redundancy backup of network device based on Combo interface |
| CN101494858B (en) * | 2008-01-21 | 2011-01-05 | 中兴通讯股份有限公司 | Method, apparatus and system for encipher recovery when switching user side processor |
| CN104270191B (en) * | 2014-04-14 | 2017-02-15 | 上海大学 | System and method of implementing wavelength multiplexing function and mutual protection function in wavelength division multiplexing convergent access type double fiber ring optical network |
| CN104270191A (en) * | 2014-04-14 | 2015-01-07 | 上海大学 | System and method of implementing wavelength multiplexing function and mutual protection function in wavelength division multiplexing convergent access type double fiber ring optical network |
| CN106027331A (en) * | 2016-06-03 | 2016-10-12 | 深圳市达士科技股份有限公司 | Unidirectional optical fiber data alarm method |
| CN111262558A (en) * | 2020-02-25 | 2020-06-09 | 云知声智能科技股份有限公司 | Method and system for realizing rapid glitch-free clock switching circuit |
| CN111262558B (en) * | 2020-02-25 | 2023-05-26 | 云知声智能科技股份有限公司 | Method and system for realizing fast burr-free clock switching circuit |
| CN111431760A (en) * | 2020-02-28 | 2020-07-17 | 深圳市风云实业有限公司 | Method for measuring bandwidth utilization rate of port in switching chip |
| CN113329546A (en) * | 2021-06-03 | 2021-08-31 | 陕西科技大学 | Landscape lighting control system with loop-back data transmission and working method thereof |
| CN113329546B (en) * | 2021-06-03 | 2024-04-23 | 陕西科技大学 | Landscape lighting control system with loop type data transmission function and working method thereof |
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Effective date of registration: 20210422 Address after: Unit 3401, unit a, building 6, Shenye Zhongcheng, No. 8089, Hongli West Road, Donghai community, Xiangmihu street, Futian District, Shenzhen, Guangdong 518040 Patentee after: Honor Device Co.,Ltd. Address before: 518057 HUAWEI Service Center building, 1 hair Road, Nanshan District Science Park, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |
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