CN1466009A - LCD board - Google Patents
LCD board Download PDFInfo
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- CN1466009A CN1466009A CNA021411077A CN02141107A CN1466009A CN 1466009 A CN1466009 A CN 1466009A CN A021411077 A CNA021411077 A CN A021411077A CN 02141107 A CN02141107 A CN 02141107A CN 1466009 A CN1466009 A CN 1466009A
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- vernier
- lcd panel
- panel according
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- substrat structure
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention is an active matrix LCD board with a pair of substrates and the liquid crystal limited between the substrates: the opaque signal leads and opaque linkers form in the frame region of one substrate, and the film transistor and pixel electrode together with the scanning and data signal lines form in the substrate; as the sealing layer forms along the preset route in the frame region, the maker checks the negative vernier which forms in the linkers to determine if the sealing layer extends along the preset route before assembly, improving the reliability of the product and not sacrificing the pixel matrix.
Description
Technical field
The present invention relates to LCD panel, particularly, relate to LCD panel with the wiring diagram that forms in its outer peripheral areas.
Background technology
The common example of LCD panel all has a pair of transparent substrates structure.Sealant makes on the transparent substrates structure space and is separated from each other, and liquid crystal is full of the space between the transparent substrates structure.On inside surface at the bottom of at least one transparent substrates structure, form conductive electrode and thin film transistor (TFT), and they form PEL matrix with liquid crystal.Oriented film covers two inside surfaces.Each oriented film grinds by predetermined direction.Grinding directional ray in the oriented film suitably is orientated liquid crystal molecule.Signal lead and signal wire also form on the transparent substrates structure with conductive electrode, and signal arrives electrode by lead-in wire and signal wire selectively.When signal arrives the electrode of selecting, just in liquid crystal, set up internal field, thereby make the pixel that is associated transparent.Then, light forms image by transparent pixel.
Fig. 1 shows the inside surface of above-mentioned transparent substrates structure.Reference number 21 shows glass substrate, and inside surface divides imaging zone 30a and frame area 30b.Fig. 2 shows the part of frame area 30b.
Imaging region 30a distributes to PEL matrix and signal wire, and frame area 30b distributes to concentric line 29, terminal block 31
1To 31
3, 32
1To 32
3, 33
1To 33
3With common lead 36 and connector 35
A1, 35
A2, 35
B1, 35
B2, 37
A1, 37
A2, 37
B1, 37
B2, 38
A1, 38
A2, 38
B1With 38
B2 Concentric line 29 prolongs along a pair of side line and an end line of glass substrate 21, and the label of 29 3 parts of concentric line is respectively 29a, 29b, 29c.
A connector 35
A1Amplify in Fig. 2 with the terminal block that links to each other.Connector 35
A1Make by opaque conductive material, and occupy delta- shaped region.Connector 35
A1, 35
A2, 35
B1, 35
B2, 37
A1, 37
A2, 37
B1, 37
B2, 38
A1, 38
A2, 38
B1With 38
B2The zone that occupies broad is to reduce resistance. Opaque connector 35
A1, 35
A2, 35
B1, 35
B2, 37
A1, 37
A2, 37
B1, 37
B2, 38
A1, 38
A2, 38
B1With 38
B2Also serve as light shield.Connector 35
A1The outer end be connected in common lead 36 and the inner is connected in concentric line 29a.Signal lead 34 is formed at the both sides of common lead 36, and distributes to sweep signal.Signal lead 34 is connected in sweep trace 22 by internal wiring 22a, and sweep trace 22 is parallel to each other and extends through central area 30a.Data line 23 is parallel to each other along the direction vertical with sweep trace 22 and extends through central area 30a.Fig. 2 only illustrates a data line 23.
Pixel is pressed row and column and is arranged, and each pixel is all by reference number 24 expressions.Pixel 24 is equal to the series combination of thin film transistor (TFT) 26 and the parallel connection combination of capacitor 25/28.A slice liquid crystal between capacitor 25 expression pixel capacitors and the public electrode, and another capacitor 28 is referred to as " common storage ".Sweep trace 22 is connected to the grid of thin film transistor (TFT) 26 in pixel 24 row, and data line 23 is connected to the drain electrode of thin film transistor (TFT) in pixel 24 row.
When producing image on PEL matrix 24, sweep trace 22 sequentially becomes significant level, and supplies with pixel 24 row by data line 23 with being loaded with visual signal Synchronization.Pixel 24 becomes transparent selectively, and back-lighting consequently produces image by transparent pixel 24 on pixel 24 matrixes.
As hereinafter described, sealant 10a extends to frame area 30b, and pixel 24 matrixes change with oriented layer 11a.Sealant 10a is by opaque three corner connectors 35
A1, 35
A2, 35
B1, 35
B2, 37
A1, 37
A2, 37
B1, 37
B2, 38
A1, 38
A2, 38
B1With 38
B2, and the periphery of oriented layer 11a extends to nontransparent three corner connectors 35
A1, 35
A2, 35
B1, 35
B2, 37
A1, 37
A2, 37
B1, 37
B2, 38
A1, 38
A2, 38
B1With 38
B2
Sealant 10a will have predetermined width and pass through predetermined path at outer peripheral areas 30b.If sealant 10a is too narrow or deviate from predetermined path, liquid crystal just is easy to leak.On the other hand, oriented layer 11a will correctly aim at the matrix of pixel 24.If oriented layer departs from the matrix of pixel 24, liquid crystal just can not correct orientation, and the image that produces on it will be degenerated.
In this case, propose to form vernier (Vernier) at frame area.Whether vernier is open in the Japanese Laid-Open Patent Application of NO.8-106100 at application number, and the fabricator checks vernier, suitable at frame area to see the sealant path.Whether another kind of vernier is open in the Japanese Laid-Open Patent Application of NO.11-024079 at application number, and the fabricator checks vernier, aim at PEL matrix to see oriented layer.Therefore, consider the high reliability of product, vernier is comparatively desirable.
But the vernier of prior art needs the additional areas in the frame area, and frame area is broadened.Framework is narrow more, and imaging region is just wide more.Therefore, consider the width of imaging region, vernier is not to be desirable.
Summary of the invention
Therefore important goal of the present invention provides LCD panel, and it very reliably and not sacrifices imaging region.
The inventor has considered the intrinsic problem of prior art LCD panel, and notices that vernier should be formed in the connector.At first, the inventor is from connector 35
A1The zone 36 of normally rectangle in remove opaque material, and in as shown in Figure 3 rectangular area 36
A1The middle direct vernier (Positive Vernier) that forms.Scale 2a and numeral "+1 "/" 0 "/" 1 " is opaque, so that at connector 35
A1The regional 36a of normally rectangle in still remain with wide transparent region 36b.Scale 2a is convenient to the fabricator and specifies the occupied path of sealant 11.In this case, the width of sealant is from+0.5 to-0.5, and the fabricator can make the correct decision that forms of sealant.At connector 35
A1Middle formation direct vernier, and direct vernier 2 need not any additional areas.
But, because connector 35
A1The cause of middle narrower part 36c, direct vernier 2 causes big resistance.In addition, back-lighting can pass the transparent region 36b of broad, and can see through imaging region with being out of favour.Big resistance has caused brightness disproportionation and interference.Leak the brightness disproportionation that light causes image.In this case, the inventor reaches a conclusion:, consider from the visual aspect of fineness that negative vernier (Negative Vernier) is gratifying although form vernier in the connector that has reduced frame area.
According to an aspect of the present invention, a kind of LCD panel that produces sensed image is provided, described LCD panel comprises: first substrat structure, described first substrat structure comprises the transparent substrates with central area and frame area, conducting wire and element are distributed in described central area, be used to form sensed image, described frame area is around described central area and distribute to the opaque bus that links to each other with the conducting wire selectively, is used for exciting element selectively; Second substrat structure relative with first substrat structure; Sealant forms between first substrat structure and second substrat structure, so that it can extend along certain path in described frame area; Liquid crystal is used for filling the slit of being determined by the inside surface and the sealant of first and second substrat structures respect to one another.And at least one opaque bus, form at least one vernier, be used for stipulating the path of determining.
According to another aspect of the present invention, a kind of LCD panel that is used for producing sensed image is provided, described LCD panel comprises: first substrat structure, described first substrat structure comprises having the central area, the transparent substrates of frame area and oriented layer, conducting wire and element are distributed in described central area, be used to form sensed image, described frame area is around described central area and distribute to the opaque bus bus that links to each other with the conducting wire selectively, be used for exciting element selectively, described oriented layer is in the central area and adjoin on the inboard subregion of frame area of central area and form; Second substrat structure relative with first substrat structure; Sealant forms between first substrat structure and second substrat structure, so that it can extend along certain path in described frame area; Liquid crystal is used for filling the slit of being determined by the inside surface and the sealant of first and second substrat structures respect to one another.And at least one opaque bus, form at least one vernier, determine the whether correctly standard of location of oriented layer so that provide.
Description of drawings
Will make the characteristic of LCD panel and advantage clearer below with reference to accompanying drawing to explanation of the present invention.
Fig. 1 is lead-in wire and the internal wiring planimetric map that is presented on the substrat structure inside surface that forms a part of LCD panel;
Fig. 2 shows the conspectus between the lead-in wire/internal wiring/connector and signal wire on the substrat structure inside surface.
Fig. 3 is the planimetric map that is presented at the direct vernier that forms in the connector;
Fig. 4 is lead-in wire and the internal wiring planimetric map that shows on the substrat structure inside surface that forms part LCD panel according to the present invention;
Fig. 5 shows the conspectus between the lead-in wire/internal wiring/connector and signal wire on the substrat structure inside surface.
Fig. 6 is the layout planimetric map that is presented at the negative vernier that forms for potted line in the connector;
Fig. 7 is the layout planimetric map that is presented at the negative vernier that forms for oriented layer in the connector.
Embodiment
First embodiment
With reference to figure 4, imbody active matrix color LCD board of the present invention mainly comprises: the first substrat structure 21a, the second substrat structure 21b and be full of the first substrat structure 21a and the second substrat structure 21b between the liquid crystal in space.Four liquid crystal molecules in four ellipse representation liquid crystal, and the liquid crystal molecule label is 21c.First substrat structure has transparent substrates 21d, and transparent substrates 21d is divided into imaging region 31a and frame area 30c.Fig. 5 shows a part and the pixel 24 of frame area 30c, the sweep trace that forms in an imaging region 30a part of adjoining with the part of frame area 30c 22, a data line 23 and a common signal line 27.Periphery along transparent glass substrate 21d forms sealant 11, and extends with predetermined path.Oriented layer 12 forms the inside surface of the first and second substrat structure 21a/21b, and liquid crystal 21c is sealed in by in oriented layer 12 and the sealant 11 formed spaces.
Imaging region 30a distributes to the matrix and the public/data/scan signal line 27/23/22 of pixel 24, and frame area 30b distributes to concentric line 29, terminal block 31
1To 31
3, 32
1To 32
3, 33
1To 33
3With common lead 36 and connector 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1With 38 '
B2 Concentric line 29 prolongs along a pair of side line and an end line of transparent glass substrate 21d, and the label of 29 3 parts of concentric line is respectively 29a, 29b, 29c.
A connector 35 '
A1Amplify in Fig. 5 with the terminal block that links to each other.Connector 35 '
A1Make by opaque conductive material, and occupy delta-shaped region.In opaque Elecrical connector, form negative vernier 1, will elaborate to it below.
Connector 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1With 38 '
B2Have bigger zone, so that reduce resistance.Opaque three corner connector connectors 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1With 38 '
B2Also serve as shade.Most connector is similar each other, thereby only to a connector 35 '
A1Be described.
Connector 35 '
A1The outer end be connected in common lead 36 and the inner is connected in concentric line 29a.Signal lead 34 is formed at the both sides of common lead 36, and distributes to sweep signal.Common lead 36 and signal lead 34 are opaque.Signal lead 34 is by internal wiring 22
aBe connected in sweep trace 22, and sweep trace 22 is parallel to each other and extends through central area 30a.Data line 23 is parallel to each other along the direction vertical with sweep trace 22 and extends through central area 30a.Although be formed with many data lines 23 in the central area, Fig. 5 only illustrates a data line 23.
Pixel 24 is pressed row and column and is arranged.And each pixel 24 all is equivalent to the series combination of thin film transistor (TFT) 26 and the parallel connection combination of capacitor 25/28.Public electrode, pixel capacitors and a slice liquid crystal between them form each pixel, and another capacitor 28 is referred to as " common storage ".Sweep trace 22 is connected to the grid of thin film transistor (TFT) 26 in pixel 24 row, and data line 23 is connected to the drain electrode of thin film transistor (TFT) in pixel 24 row.In this case, on the first substrat structure 21a, form concentric line 27, data line 23, sweep trace 22, thin film transistor (TFT) 26, pixel capacitors and public electrode, and on the second substrat structure 21b, form color filter and black matrix".
When producing image on the matrix of pixel 24, sweep trace 22 sequentially becomes significant level, and supplies with pixel 24 row by data line 23 with being loaded with visual signal Synchronization.Pixel 24 becomes transparent selectively, and allows back-lighting by consequently produce image on the matrix of pixel 24.
As mentioned below, in opaque three corner connectors, form negative vernier, and Fig. 6 shows opaque bus 35 '
A1In one.Partly from connector 35 '
A1In remove opaque material and at connector 35 '
A1The middle clear area that forms.Transparent glass substrate 21d is exposed to the clear area.Negative vernier 1 is served as in the clear area, so that negative vernier is transparent.Thereby, connector 35 '
A1The broad remainder conducts electricity.Certain constant voltage is by connector 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1With 38 '
B2Broad remainder and concentric line 27 propagate into public electrode.The broad remainder makes concentric line 27 and the resistance that goes between between 36 lower, and therefore, the electromotive force on the public electrode can make us welcoming ground to raise.In addition, back-lighting can not leak by clear area extremely narrowly, and can not pass imaging region 30a.
In the process of making the first substrat structure 21a, sealant 11 is printed among the frame area 30c.Lead-in wire 34/36 and connector 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1With 38 '
B2On frame area 30c, form.When forming sealant 11 in frame area 30c, the fabricator checks negative vernier 1, sees whether sealant extends along predetermined path.Sealant 11 occupies from-0.5 millimeter to+0.5 millimeter zone.Center line passes scale " 0 ", and its width is 1 millimeter.The fabricator determines sealant 11 accurately to form along predetermined path.Predetermined path will be dropped within the scope of scale " 0 " both sides.Then, the fabricator assembles first and second substrat structure 21a and the 21b, and liquid crystal 21c is injected the space of being determined by oriented layer 12 and sealant 11.Therefore, before using negative vernier 1 assembling, the fabricator checks sealant 11, and is discarded in first substrat structure that departs from predefined paths greatly that forms in the sealant and first substrat structure that forms with narrow sealant.Sealant 11 at predefined paths does not allow back-lighting to pass imaging region 30a, and in the image that forms on the matrix of pixel 24 any brightness disproportionation phenomenon can not take place.
As what will be understood that from following explanation, the resistance that negative vernier 1 neither can reduce connector can not make back-lighting leak into imaging region 30a yet.In nontransparent Elecrical connector, form negative vernier 1, and negative vernier 1 need not any additional areas.Frame area 30c is the same narrow with the framework of as depicted in figs. 1 and 2 substrat structure, and because the cause of the vernier that forms in the opaque Elecrical connector, has improved the reliability of active color liquid crystal plate.Therefore, the invention solves the intrinsic problem of prior art.
Negative vernier is more favourable than direct vernier.Opaque connector has been avoided the light leak of imaging region 30a fully, as mentioned above.In addition, negative vernier 1 is more durable than direct vernier.Direct vernier forms by a plurality of opaque little, and opaque little be very easy to come off from transparent glass substrate.On the other hand, negative vernier 1 is determined by bigger opaque connector.Bigger opaque connector is not easy to come off.Therefore, negative vernier is more durable.
Second embodiment
Fig. 7 shows another the negative vernier 1A that forms in the frame area of substrat structure.The similar of the substrat structure and the first substrat structure 21a, and formed another active matrix color LCD board and second substrat structure and liquid crystal.Except negative vernier 1A, identical in the substrat structure, second substrat structure and liquid crystal and first embodiment.Therefore, in order to simplify, only vernier 1A is born in explanation.
Negative vernier 1A still has scale 1b and numeral "+1 ", " 0 ", " 1 ".Scale 1b distributes to oriented layer 12, and represents the impact point that the object-line of oriented layer 12 passes through by the scale of " 0 " indication.
When the fabricator made oriented layer 12, the fabricator checked oriented layer 12 with negative vernier.The fabricator checks negative vernier 1A, sees whether the object-line of oriented layer 12 aims at scale " 0 ".In this case, object-line is aimed at scale " 0 ", and the fabricator determines the matrix of oriented layer 12 complete matching pixels 24.
Because the cause of negative vernier 1A realizes that the active matrix color LCD board of second embodiment has all advantages of first embodiment.
In the above-described embodiment, concentric line 27, sweep trace 22 and data line 23 serve as the conducting wire, and thin film transistor (TFT) 26 and the parallel connection of electric capacity 25/28 are made up, and the two is corresponding with element.Lead-in wire and non-conductive three corner connectors 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1With 38 '
B2And 35 "
A1Serve as opaque bus.
Although shown and specific embodiments of the invention have been described, the variations and modifications that do not break away from marrow of the present invention and scope are conspicuous to one skilled in the art.
Can in opaque Elecrical connector, form negative vernier 1 and 1a successively.
If rectangular aperture 36a is narrower than remaining opaque section usually, LCD panel can be used direct vernier 2 according to the present invention.
Negative vernier can only be made of scale.Otherwise, can in opaque connector, only form the slit of indicating the boundary line.
Can in being formed at the opaque electrode of frame area, form negative vernier.
Can in another kind of LCD panel, form vernier.
Claims (20)
1, a kind of LCD panel that produces sensed image comprises:
First substrat structure (21a), it comprises the transparent substrates (21d) of have the central area (30a) and frame area (30c), conducting wire (22,23,27,29) and element (24) are distributed in described central area (30a), be used to form sensed image, described frame area (30c) is around described central area (30a) and distribute to the opaque bus (34,36,35 that is connected in described conducting wire (22,23,27,29) selectively
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2), be used for the described element of driver element (24) selectively;
Second substrat structure (21b) relative with first substrat structure (21a);
Sealant (11) forms between first substrat structure (21a) and second substrat structure (21b), so that it can extend along certain path in described frame area (30c);
Liquid crystal (21c) is used for filling the slit of being determined by the inside surface and the sealant (11) of first and second substrat structures (21a/21b) that face with each other;
It is characterized in that,
And at least one vernier (1) is at least one opaque bus (34,36,35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) in form, be used for stipulating the path of determining.
2, LCD panel according to claim 1 is characterized in that described at least one vernier (1) comprises the scale (1a) that is provided with at interval with rule.
3, LCD panel according to claim 2 is characterized in that described at least one vernier (1) also comprises the numeral (+1,0 ,-1) of the described scale position that expression is selected.
4, LCD panel according to claim 1 is characterized in that described at least one vernier (1) passes through at described at least one described opaque bus (34,36,35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) realize the middle clear area that forms, so that described transparent substrates (21d) partly is exposed to described at least one vernier (1).
5, LCD panel according to claim 4 is characterized in that the scale (1a) that described clear area regulation is provided with at interval with rule.
6, LCD panel according to claim 5 is characterized in that the also numeral (+1,0 ,-1) of the described scale position of regulation indication selection of described clear area.
7, LCD panel according to claim 1, it is characterized in that described element (24) is multiple combination, wherein each makes up the capacitor (28) that all has described thin film transistor (TFT) (26) and be series at described thin film transistor (TFT) (26), and wherein said opaque bus (34,36,35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) be signal lead (34) and Elecrical connector (35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2), described signal lead (34) is connected in the described thin film transistor (TFT) (26) of described a plurality of combinations selectively by signal wire (22),) described Elecrical connector is electrically connected on described capacitor (25), wherein said at least one vernier (1) is at a described Elecrical connector (35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) middle formation.
8, LCD panel according to claim 7 is characterized in that described at least one vernier (1) passes through at described at least one described Elecrical connector (35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) realize the middle clear area that forms, so that described transparent substrates (21d) partly is exposed to described at least one vernier (1).
9, LCD panel according to claim 8 is characterized in that the scale (1a) that described clear area regulation is provided with at interval with rule.
10, LCD panel according to claim 9 is characterized in that the also numeral (+1,0 ,-1) of the described scale position of regulation indication selection of described clear area.
11, a kind of LCD panel that produces sensed image comprises:
First substrat structure (21a), it comprises the transparent substrates (21d) of have the central area (30a), frame area (30c) and oriented layer (12), conducting wire (22,23,27,29) and element (24) are distributed in described central area (30a), be used to form sensed image, described frame area (30c) is around described central area (30a) and distribute to the opaque bus (34,36,35 that is connected in described conducting wire (22,23,27,29) selectively
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2), being used for encouraging selectively described element (24), described oriented layer (12) is at central area (30a) and adjoin on the inboard subregion of frame area (30c) of central area and form;
Second substrat structure (21b) relative with first substrat structure (21a);
Sealant (11) form between first substrat structure (21a) and second substrat structure (21b), so that it can extend in described frame area (30c);
Liquid crystal (21c) is used for filling the slit of being determined by the inside surface and the sealant (11) of upright toward each other first and second substrat structures (21a, 21b);
It is characterized in that,
And at least one vernier (1A) is at least one opaque bus (34,36,35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2), middle formation, so that provide the standard of determining whether described oriented layer (12) correctly locatees.
12, LCD panel according to claim 11 is characterized in that described at least one vernier (1A) comprises the scale (1b) that is provided with at interval with rule.
13, LCD panel according to claim 12 is characterized in that described at least one vernier (1A) also comprises the numeral (+1,0 ,-1) of the described scale position that expression is selected.
14, LCD panel according to claim 11 is characterized in that described at least one vernier (1A) passes through at described at least one described opaque bus (34,36,35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) in the clear area that forms realize so that described transparent substrates (21d) partly is exposed to described at least one vernier (1A).
15, LCD panel according to claim 14 is characterized in that the scale (1b) that described clear area regulation is provided with at interval with rule.
16, LCD panel according to claim 15 is characterized in that the also numeral (+1,0 ,-1) of the described scale position of regulation indication selection of described clear area.
17, LCD panel according to claim 11, it is characterized in that described element (24) is multiple combination, wherein each makes up the capacitor (25) that all has described thin film transistor (TFT) (26) and be connected in series with described thin film transistor (TFT) (26), and wherein said opaque bus (34,36,35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) be signal lead (34) and Elecrical connector (35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2), described signal lead (34) is connected in the described thin film transistor (TFT) (26) of described a plurality of combinations selectively by signal wire (22), described Elecrical connector is electrically connected on described capacitor (25), and wherein said at least one vernier (1A) is at a described Elecrical connector (35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) middle formation.
18, LCD panel according to claim 17 is characterized in that described at least one vernier (1A) passes through at described at least one described Elecrical connector (35
A1, 35 '
A1, 35 '
A2, 35 '
B1, 35 '
B2, 37 '
A1, 37 '
A2, 37 '
B1, 37 '
B2, 38 '
A1, 38 '
A2, 38 '
B1, 38 '
B2) realize the middle clear area that forms, so that described transparent substrates (21d) partly is exposed to described at least one vernier (1A).
19, LCD panel according to claim 18 is characterized in that the scale (1b) that described clear area regulation is provided with at interval with rule.
20, LCD panel according to claim 19 is characterized in that the also numeral (+1,0 ,-1) of the described scale position of regulation indication selection of described clear area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02141107 CN1244844C (en) | 2002-07-04 | 2002-07-04 | LCD board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02141107 CN1244844C (en) | 2002-07-04 | 2002-07-04 | LCD board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1466009A true CN1466009A (en) | 2004-01-07 |
| CN1244844C CN1244844C (en) | 2006-03-08 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02141107 Expired - Lifetime CN1244844C (en) | 2002-07-04 | 2002-07-04 | LCD board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1244844C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7447427B2 (en) | 2004-06-25 | 2008-11-04 | Casio Computer Co., Ltd. | Digital camera image display apparatus and digital camera provided with the apparatus |
| CN101191969B (en) * | 2006-12-02 | 2010-10-13 | 龙腾光电（控股）有限公司 | Liquid crystal panel for liquid crystal display |
-
2002
- 2002-07-04 CN CN 02141107 patent/CN1244844C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7447427B2 (en) | 2004-06-25 | 2008-11-04 | Casio Computer Co., Ltd. | Digital camera image display apparatus and digital camera provided with the apparatus |
| CN100449400C (en) * | 2004-06-25 | 2009-01-07 | 卡西欧计算机株式会社 | Digital camera image display apparatus and digital camera provided with the apparatus |
| CN101191969B (en) * | 2006-12-02 | 2010-10-13 | 龙腾光电（控股）有限公司 | Liquid crystal panel for liquid crystal display |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1244844C (en) | 2006-03-08 |
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