CN1464690A - Discrete Fourier transform equipment of ADSL system - Google Patents

Abstract

The invention provides a fourier transformation apparatus in the ADSL system that can be used for the modems of 256 communication channels, Being capable of accomplishing the 512 point DFT (I-DFT AND F-DFT) processing, the apparatus comprises a double port RAM, rotational factor module, sequential control module, read-write address producing module and butterfly-type calculation module. After the data preparation of the front level input double port RAM is ready, the sequential control module starts the read-write address producing module to begin to read-write data and the rotational factor, the butterfly-type calculation module performs the butterfly-type computation according to data and the rotational factor, the immediate data is stored in the double port RAM. The invention solves the problem of insufficient hardware resources, nearly 50% of operand can be saved

Description

Discrete Fourier transform equipment in the ADSL (Asymmetric Digital Subscriber Line) system

Technical field

The present invention relates to data communication field, specifically, relate to discrete Fourier transform (DFT) device in ADSL (Asymmetric Digital Subscriber Line) (Asymmetrical Digital Subscriber Loop the is called for short ADSL) system.

Background technology

The ADSL system adopts advanced digital modulation and signal processing technology, when ordinary telephone line is uploaded the transmission of electricity call business, provide up-downgoing speed can reach simultaneously 640kbit s and 8Mbit high-speed broadband data service and video traffic about s, its key technology is Discrete multi-tone (DMT) modulation technique of IA High Speed Channel.In the ADSL system, by the DMT technology 1MHz bandwidth is divided into 256 subchannels, the bandwidth of each subchannel is 4.3125kHz, then according to fading channel characteristic and noise condition, being assigned in each subchannel with importing data adaptive.

In the ADSL system structure chart of DMT system as shown in Figure 1, the direction of arrow is the transmission direction of data.In modulation direction, after signal process Bit Allocation in Discrete, constellation encoder and the gain adjustment that needs to send, (I-DFT) modulates through inverse discrete Fourier transform, and the signal after the modulation sends after Cyclic Prefix and slicing are handled through adding again; In the demodulation direction, the signal of reception is earlier through time domain equalization with remove Cyclic Prefix, and (F-DFT) carries out demodulation by the discrete fourier direct transform, carries out frequency domain equalization, constellation decoder then and joins than particular solution.In fact, demodulation is the inverse process of modulation, and wherein discrete Fourier transform DFT (I-DFT, F-DFT) is a key point of finishing 256 Channel Modulation demodulation.According to the regulation of American National Standard ANSIT1.413, a frame period is 68/69*250 ≈ 246 μ s, and the time of carrying out 512 DFT processing must be less than a frame period.

Present DFT device is in order to improve arithmetic speed, the general modes that adopt parallel processings more, and each butterfly processing element that is about to the DFT that N orders carries out computing simultaneously.If adopt conventional decimation in time (DIT) or decimation in frequency (DIF) method to carry out N point FFT butterfly computation, then need 6Nlog ₂ ^2NIndividual real add musical instruments used in a Buddhist or Taoist mass and 4Nlog ₂ ^2NIndividual real multipliers can take sizable hardware resource like this, is hard-wired one big drawback.In order to save hardware, United States Patent (USP) 6,157,938 " FAST FOURIER TRANSFORMDEVICE AITH PARALLEL LATTICE ARCHITECTURE " have proposed a kind of new fast Fourier transform device.Fig. 2 is the schematic diagram of above-mentioned fast Fourier transform device in the DMT system, it is converted into 2N data with N parallel frequency domain data by conjugation, pass through inverse fast Fourier transform (IFFT) computing again and obtain 2N data, convert itself and string to time domain data then, by the time domain data of the 2N after the transmission channel flow through the string and the conversion, again the data after string and the conversion are carried out fast Fourier transform (FFT) computing, to obtain the top n frequency domain data.Fig. 3 is the structure chart of the IFFT of above-mentioned United States Patent (USP) proposition, 1 pair of N data of multiplication process module are carried out multiplication process simultaneously, obtain two groups of data M DCT and MDST respectively, after the oversampling circuit expansion module 2 and the module that moves to left, obtain 2N data then through IFFT.Learn that thus adopting this United States Patent (USP) to handle IFFT needs the individual real multipliers of 4 (N-1) and [5 (N-1)+2] individual real add musical instruments used in a Buddhist or Taoist mass, still needs more hardware resource.In the ADSL system, because the module that DMT relates to is very many, how to save hardware resource and become one of sixty-four dollar question, and prior art can not meet the demands well, therefore press for the DFT device that is fit to the ADSL system, to reach effective control hardware resource and to finish the purpose of modulation real-time.

Summary of the invention

Technical problem to be solved by this invention is to provide the discrete Fourier transform equipment in the ADSL system, can be used for the modulation and demodulation of 256 channels of DMT system, and the DFT (I-DFT and F-DFT) that finishes at 512 handles.

Discrete Fourier transform equipment of the present invention comprises 1 dual port RAM, twiddle factor module, time-sequence control module, read/write address generation module and butterfly operation module;

Described dual port RAM: be subjected to the control of described read/write address generation module, the intermediate operations data of described butterfly operation module are read and write;

Described twiddle factor module: be used for depositing the required twiddle factor W of butterfly computation process _2N ^{± k}, read by described read/write address generation module, export described butterfly operation module to;

Described time-sequence control module: be used to control the read-write of described read/write address generation module, and control the work schedule of each module;

Described read/write address generation module: controlled by described time-sequence control module, read the data among described dual port RAM and the outside dual port RAM A, and the twiddle factor in the described twiddle factor module gives described butterfly operation module, and control result of calculation writes among described dual port RAM and the outside dual port RAM C;

Described butterfly operation module: be used to carry out butterfly and calculate, gained result of calculation writes under the control of described read/write address generation module among the dual port RAM C of described dual port RAM and outside.

Discrete Fourier transform equipment of the present invention, the mode of employing serial process only needs just can realize with less hardware, saves 511 complex multipliers and a plurality of adder than existing DFT device, thereby has solved the problem of hardware resource anxiety; Utilize the conjugate symmetry of system in addition, adopt the hermitian algorithm that the calculating of leaf transformation in 512 point discrete Fouriers is further simplified, reduce nearly 50% operand, saved operation time, reduced power consumption.

Description of drawings

Fig. 1 is the structured flowchart of DMT system in the ADSL system.

Fig. 2 is a United States Patent (USP) 6,157, the schematic diagram of 938 FFT (I-FFT, F-FFT) in the DMT system.

Fig. 3 is the circuit structure diagram of FFT among Fig. 2.

Fig. 4 is the schematic diagram of discrete Fourier transform equipment of the present invention in the DMT system.

Fig. 5 is the structural representation of discrete Fourier transform equipment of the present invention.

Fig. 6 is the process chart of inverse discrete Fourier transform among Fig. 4 (I-DFT) device.

Fig. 7 is the process chart of discrete fourier direct transform (F-DFT) device among Fig. 4.

Fig. 8 is the schematic diagram of used butterfly computation rule in the preprocessing process.

Fig. 9 is an inverse fast Fourier transform butterfly computation rule schematic diagram at different levels.

Figure 10 is the circuit diagram of butterfly operation module 13 among Fig. 5.

Figure 11 is the cut-away view of butterfly processing element 300 among Figure 10.

Embodiment

Below in conjunction with drawings and Examples, the present invention is done further introduction in detail.

DMT system in the ADSL system comprises the modulation and demodulation both direction, as shown in Figure 1.In modulation direction, the data that needs send are carried out Bit Allocation in Discrete earlier, press on data allocations to 256 channel of transmission performance difference with different bits of channel, data after Bit Allocation in Discrete are being carried out constellation encoder, then to its adjustment that gains, again signal is modulated on 256 channels through I-DFT, sends through after adding processing such as Cyclic Prefix, slicing again; In the demodulation direction, signal that will receive removes Cyclic Prefix through behind the time domain equalization, the signal of 256 channels is handled demodulation through F-DFT come out, again to its demodulation of carrying out frequency domain equalization, constellation decoder, joining etc. the DMT that finishes dealing with than particular solution.From said process as can be seen, demodulation is the inverse process of modulation.

Fig. 2 and Fig. 3 are the structural representations of United States Patent (USP), introduce in detail in front, and as can be seen, this patent has adopted the mode of parallel processing to finish the processing procedure of IFFT (FFT), need more hardware resource.

Fig. 4 is the schematic diagram of the present invention in the DMT system, depositing gain successively in through the adjusted frequency domain data X of gain (k) adjusts among the RAM, after the data of 256 channels are all finished the gain adjustment, read X (k) successively, X (N-k) carries out 512 I-DFT computings, wherein N=512/2=256 represents the number of channel.Calculate resulting time-domain signal and export to and add buffer memory among the Cyclic Prefix RAM, finish the data-modulated of 256 channels.Modulation signal transmits through transmission channel.At receiver side, go a frame time domain data behind the Cyclic Prefix to be ready to after, the time domain data of reading successively among the Cyclic Prefix RAM carries out the F-DFT computing, last resulting frequency-region signal exports among the frequency domain equalization RAM, finishes the data demodulates of 256 channels.

Fig. 5 is the structure chart of discrete Fourier transform equipment of the present invention, comprises dual port RAM 12, twiddle factor module 14, time-sequence control module 10, read/write address generation module 11 and butterfly operation module 13.Because each butterfly computation of each grade all is applicable to this rule of location computing, so only need adopt 1 dual port RAM 12 just can finish read-write to the butterfly computation intermediate data.Twiddle factor module 14 is required twiddle factor W in the storage butterfly computation _2N ^{± k}, under the control of read/write address generation module 11, export to butterfly operation module 13.Time-sequence control module 10 starts read/write address generation module 11 and begins to carry out reading and writing data behind the DSR of prime input dual port RAM A, also controls the work schedule of each module simultaneously.Read/write address generation module 11 is subjected to the control of time-sequence control module 10, reads corresponding twiddle factor in the data of different addresses among the different RAM and the twiddle factor module 14 constantly in difference, and the butterfly computation result is write among the corresponding RAM.Butterfly operation module 13 carries out butterfly computation according to data and twiddle factor.Read/write address generation module 11 also links to each other with dual port RAM C with the dual port RAM A of outside with butterfly operation module 13.

Dual port RAM A is the buffer memory of prime input data, is that RAM is adjusted in gain among Fig. 4 at modulation direction dual port RAM A, is to remove Cyclic Prefix RAM among Fig. 4 at demodulation direction dual port RAM A.Dual port RAM C is the storage DFT computing operation result of one-level to the end, is to add Cyclic Prefix RAM among Fig. 4 at modulation direction dual port RAM C, is frequency domain equalization RAM among Fig. 4 at demodulation direction dual port RAM C.

Because demodulation is the inverse process of modulation, so conciliating the F-DFT that calls, the I-DFT of modulation usefulness can adopt above-mentioned identical structure shown in Figure 5, just different on the flow process of handling.To specifically introduce the processing procedure of I-DFT and F-DFT below.

Require according to the processing sequential to 2N point DFT in the ADSL system: the DFT usable frequency is 35.328MHZ in the ADSL system, and maximum 512 DFT should finish in 68/69*250us.If adopt the FFT mode of 2N point DIF or DIT, then need through Nlog ₂ ^2NInferior dish-shaped computing, 512 FFT computings just need 2304 times butterfly computation so.

The present invention adopts the hermitian symmetry algorithm according to the time-frequency domain data characteristics of system, can make operand reduce one times.The formula of hermitian symmetry algorithm is seen formula (1). $x_c\left(n\right)=x\left(2n\right)+i\&CenterDot;x(2n+1)$ $=\frac{1}{2N}\underset{k=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\left\{\right[X\left(k\right)+X^{*}(N-k)]+j[X\left(k\right)-X^{*}(N-k)]\&CenterDot;{\mathrm{<figure-callout\; id="2N"\; label="W"\; filenames="A0211218800132.png,A0211218800141.png"\; state="\{\{state\}\}">W</figure-callout>}}_{2N}^{-k}\}\&CenterDot;W_N^{-\mathrm{nk}}---\left(1\right)$

Wherein, x _c(n) be the time domain data sequence, its real part is continuously the even sequence x (2n) of the time domain data of input, and imaginary part is continuously the odd sequence x (2n+1) of the time domain data of input, wherein n=0,1,2,3...N-1; X (k) is the frequency domain data sequence, wherein k=0,1,2,3...N-1; N represents the total channel number modulated to equal 256; X ^*Expression conjugation data; W _2N ^-kAnd W _N ^-nkIt is twiddle factor.

Can be when modulation direction be carried out the I-DFT processing by formula (1), X (k) converts X ' operational formula (2) and (3) (k) to: $X^{\&prime;}\left(k\right)=[X\left(k\right)+X^{*}(N-k)]+j[X\left(k\right)-X^{*}(N-k)]\&CenterDot;{\mathrm{<figure-callout\; id="2N"\; label="W"\; filenames="A0211218800132.png,A0211218800141.png"\; state="\{\{state\}\}">W</figure-callout>}}_{2N}^{-k}---\left(2\right)$ $X^{\&prime;}(N-k)={\left\{\right[X\left(k\right)+X^{*}(N-k)]-j[X\left(k\right)-X^{*}(N-k)]\&CenterDot;{\mathrm{<figure-callout\; id="2N"\; label="W"\; filenames="A0211218800132.png,A0211218800141.png"\; state="\{\{state\}\}">W</figure-callout>}}_{2N}^{-k}\}}^{*}---\left(3\right)$

In modulation direction, I-DFT handles and comprises two steps, preliminary treatment and IFFT butterfly computation, promptly earlier frequency domain data is carried out preliminary treatment, with X (k), X (N-k) carry out 128 butterfly computations obtain X ' (k), X ' (N-k), again it is carried out 8 grades of (128*8 time) butterfly computations of 256 IFFT, can obtain time-domain signal, finish 512 I-DFT like this and only need carry out 1152 times butterfly computation, finishing 512 I-DFT only needs 65us, well below the sequential requirement of ADSL system.

Fig. 6 promptly is the process chart of I-DFT device among Fig. 4, needs altogether through 9 grades of computings, i.e. stage=1,2,3,4,5,6,7,8,9.The 1st grade of (stage=1) computing is that 256 the data X (k) with frequency domain finish X (k) to X ' conversion (k) through preliminary treatment, i.e. 128 butterfly computations of perfect (2) and formula (3) successively; (stage=2～9) are eight grades of computings of 256 IFFT from the 2nd grade to the 9th grade, obtain data X after finishing the preliminary treatment that X (k) (k) changes to X ' ₁(m), enter the first order of IFFT computing, through obtaining X behind 128 butterfly computations ₂(m), enter the second level of IFFT, enter the third level, the fourth stage successively, obtain time domain data X (n), so just finished the modulation of 256 channels until the 8th grade.

Equally, can obtain the demodulation direction by formula (1) and carry out F-DFT when handling, the operational formula that X ' (k) converts X (k) to is seen formula (4) and formula (5): $X\left(k\right)=\frac{1}{4}\left\{\right[X^{\&prime;}\left(k\right)+X^{\&prime;*}(N-k)]-j[X^{\&prime;}\left(k\right)-X^{\&prime;*}(N-k)]\&CenterDot;{\mathrm{<figure-callout\; id="2N"\; label="W"\; filenames="A0211218800132.png,A0211218800141.png"\; state="\{\{state\}\}">W</figure-callout>}}_{2N}^k---\left(4\right)$ $X(N-k)=\frac{1}{4}\{X^{\&prime;}\left(k\right)+X^{{\&prime;}^{*}}(N-k)]+j[X^{\&prime;}\left(k\right)-X^{{\&prime;}^{*}}(N-k)]\&CenterDot;{\mathrm{<figure-callout\; id="2N"\; label="W"\; filenames="A0211218800132.png,A0211218800141.png"\; state="\{\{state\}\}">W</figure-callout>}}_{2N}^k{\}}^{*}---\left(5\right)$

Like this, in the demodulation direction, F-DFT handles and also comprises two steps, FFT butterfly computation and reprocessing, promptly 8 grades of (128*8 time) butterfly computations that earlier time domain data carried out 256 FFT obtain X (k), X ' (N-k), according to formula (4) and formula (5) it are carried out reprocessing again and obtain X (k), X (N-k), and finishing 512 F-DFT so only needs 1152 dish-shaped computings, finishing 512 F-DFT equally only needs 65us, satisfies the sequential requirement of ADSL system.

Fig. 7 is the process chart of F-DFT device among Fig. 4, also need altogether through 9 grades of computings, be stage=1,2,3,4,5,6,7,8,9, at first the eight grades of computings (stage=1～8) through 256 FFT convert time domain data X (n) to X ' (k), i.e. x among the figure ₈(m), carry out 128 butterfly computations of reprocessing perfect (4) and formula (5) then, (k) convert 256 data X ' to frequency domain data X (k), thereby finished the signal demodulation of 256 channels.

Fig. 8 is the schematic diagram of butterfly computation rule in the explanation preprocessing process.Preprocessing process is the computing of perfect (2) and formula (3), since X ' (k) and X ' value (N-k) be butterfly processing element computing gained of X (k) and X (N-k) composition, so during N=256, have X (0) and X (256), X (1) and X (255), X (2) and Z (254) ..., Z (128) and Z (128) totally 129 butterfly computations, wherein X (0) and X (256) are zero-frequency subchannel and nyquist frequency subchannel, its data and result all are 0, do not carry out butterfly computation, therefore only need 128 butterfly computations get final product the value of X ' (1)～X ' (255).

Identical in butterfly computation rule in the last handling process and the preprocessing process, just direction is opposite, and promptly the arrow among Fig. 8 is reverse.And reprocessing is the computing of perfect (4) and formula (5), (k) obtain X (k) from X ', in like manner each X ' (k) and X ' (N-k) form butterfly processing element, obtain the value of X (k) and X (N-k), X ' (0) and X ' (256), X ' (1) and X ' (255), X ' (2) and X ' (254) ..., up to X ' (128) and X ' (128) totally 129 butterfly computations, wherein the result of X ' (0) and X ' (256) does 0 processing, therefore also only needs 128 butterfly computations can obtain the value of X (0)～X (255).

Fig. 9 is to be 256 butterfly computation rules that IFFT is at different levels of example explanation with 16 IFFT.For N=2 ^MPoint IFFT (FFT), need altogether through M level butterfly computation, and each level has N/2 butterfly processing element, and the component law of butterfly processing element at different levels is: the inverted sequence sense data is carried out first order butterfly computation, wherein inverted sequence is meant data sequence number k=[a: b] convert k to _Instead=[b: a], k=0,1,2 ..., 127, with pretreated butterfly computation each time as a result inverted sequence write in the appropriate address of dual port RAM 12, each X ' is (2k) _Instead) and X ' ((2k+1) _Instead) promptly form a butterfly processing element, the operation result of gained is x ₁(2k) and x ₁Value (2k+1), promptly pass through X (0) and X (128), X (64) and X (192) ..., X (127) and X (255) totally 128 butterfly computations, and the result of each butterfly computation deposits in the appropriate address of dual port RAM 12 respectively in order; Also there are 128 butterfly processing elements the second level, is divided into 64 groups, and every group has two butterfly processing element: x ₁(4k) and x ₁(4k+2) and x ₁(4k+1) and x ₁(4k+3), wherein k=0,7,2 ..., 63, obtain the x as a result of butterfly computation respectively ₂(4k) and x ₂(4k+2) and x ₂(4k+1) and x ₂(4k+3), the result of each butterfly computation deposits in the appropriate address of dual port RAM 12 respectively in order; The third level also has 128 butterfly processing elements, is divided into 32 groups, and every group has 4 butterfly processing element: x ₂(16k) and x ₂(16k+4), x ₂(16k+1) and x ₂(16k+5), x ₂(16k+2) and x ₂(16k+6), x ₂(16k+3) and x ₂(16k+7), wherein k=0,7,2 ..., 31, obtain the x as a result of butterfly computation respectively ₃(16k) and x ₃(16k+4), x ₃(16k+1) and x ₃(16k+5), x ₃(16k+2) and x ₃(16k+6), x ₃(16k+3) and x ₃(16k+7), the result of each butterfly computation deposits in the appropriate address of dual port RAM 12 respectively in order; And the like, have only 1 group of 128 butterfly processing elements, i.e. x up to the 8th grade of 128 butterfly processing elements ₈(k) and x ₈(k+128), wherein k=0,1,2 ..., 127, obtain the time domain data x behind the butterfly computation respectively _c(n) and x _c(n+128), n=k wherein deposits the result of butterfly computation in the appropriate address that adds Cyclic Prefix RAM respectively in order.

256 FFT butterfly computation rule at different levels and 256 IFFT butterfly computation rule at different levels is identical, just because F-DFT is different with the handling process of I-DFT, and causes the first order read data of FFT and last the 8th grade of write data different.The first order computing of FFT is an inverted sequence sense data from remove Cyclic Prefix RAM, each x _c((2n) _Instead) and x _c((2n+1) _Instead) form a butterfly processing element, the gained operation result is x ₁(2k) and x ₁Value (2k+1) is promptly passed through x _c(0) and x _c(128), x _c(64) and x _c(192) ..., x _c(127) and x _c(255) totally 128 butterfly computations; The 8th grade of computing of FFT is that the result is deposited in the dual port RAM 12, and butterfly computation is x as a result ₈(k) and x ₈(k+128) (wherein k=0,1,2 ..., 127) promptly be data X ' (k) and X ' (k+128), the result of each butterfly computation is deposited in respectively in the appropriate address of dual port RAM 12, treat the reprocessing of next stage.Other computings at different levels are all identical with the IFFT computing.

Figure 10 has provided the structure chart of butterfly operation module 13, comprise selector 301, selector 302 and butterfly processing element 300, the data that selector 301 receives from dual port RAM A or dual port RAM 12, and export to butterfly processing element 300, twiddle factor in the twiddle factor module 14 is also delivered to butterfly processing element 300 and is calculated, and result of calculation is exported to dual port RAM C or dual port RAM 12 through selector 302.When beginning the first order (stage=1) computing of I-DFT or F-DFT, reading of data from dual port RAM A (gain is adjusted RAM or removed Cyclic Prefix RAM), other (stage=2～9) at different levels computing is reading of data from dual port RAM 12 then, through alternative selector 301 output X _l(m1) mouthful X _l(m2), X wherein _l(m1) mouthful X _l(m2) be the data of representing the l level, obtain l+1 level operation result X through the computing of butterfly processing element 300 _L+1(m1) and X _L+1(m2), its result deposits data among dual port RAM 12 or the dual port RAM C in through an alternative selector 302 again, wherein the operation results at different levels of progression stage＜9 o'clock deposit in the dual port RAM 12, the operation result of progression stage=9 deposits among the dual port RAM C (adding Cyclic Prefix RAM or frequency domain equalization RAM), wherein m1 and m2 be meant each grade butterfly processing element two the input data sequence number.

Figure 11 is the structure chart of butterfly processing element 300 among Figure 10, and butterfly processing element 300 comprises 3006,3009 and 1 complex multipliers 3002 of 3007,3008,2 subtracters of 3003,3004,3005,2 adders of 3001,3 selectors of 1 conjugator.Two data X of selector 301 outputs _l(m1) and X _l(m2), X wherein _l(m1) enter adder 3007 and subtracter 3009 respectively; X _l(m2) data and the X that exports through conjugator 3001 backs _l(m2) enter selector 3003, when stage=1, selector 3003 output X _l(m2) conjugation data, when stage＞1, selector 3003 output X _l(m2).Data X _l(m1) and the dateout of selector 3003 simultaneously in adder 3007 and subtracter 3009, carry out plural plus and minus calculation, the difference of subtracter 3009 outputs multiplies each other in complex multiplier 3002 with corresponding twiddle factor, the multiplication of complex numbers of gained is carried out plural plus and minus calculation respectively with the output of adder 3007 again in adder 3008 and subtracter 3006, gained and deliver in the selector 3004 with the result of adder 3007 again, the result of the difference of gained and complex multiplier 3002 delivers in the selector 3005, when stage=1, selector 3005 output X _L+1(m1) equal the result of adder 3008, selector 3005 output X _L+1(m2) equal the result of subtracter 3006; When stage＞1, selector 3004 output X _L+1(m1) equal the result of adder 3007, selector 3005 output X _L+1(m2) equal the result of complex multiplier 3002.

Claims (5)

1, the discrete Fourier transform equipment in a kind of ADSL (Asymmetric Digital Subscriber Line) system, it is characterized in that, comprise 1 dual port RAM (12), twiddle factor module (14), time-sequence control module (10), read/write address generation module (11) and butterfly operation module (13);

Described dual port RAM (12): be subjected to the control of described read/write address generation module (11), the intermediate operations data of described butterfly operation module (13) are read and write;

Described twiddle factor module (14): be used for depositing the required twiddle factor W of butterfly computation process _2N ^{± k}, read by described read/write address generation module (11), export described butterfly operation module (13) to;

Described time-sequence control module (10): be used to control the read-write of described read/write address generation module (11), and control the work schedule of each module;

Described read/write address generation module (11): be subjected to described time-sequence control module (10) control, read the data among described dual port RAM (12) and the outside dual port RAM A, and the twiddle factor in the described twiddle factor module (14) gives described butterfly operation module (13), and control result of calculation writes among the dual port RAM C of described dual port RAM (12) and outside;

Described butterfly operation module (13): be used to carry out butterfly and calculate, gained result of calculation writes under the control of described read/write address generation module (13) among the dual port RAM C of described dual port RAM (12) and outside.

2, the discrete Fourier transform equipment in the ADSL (Asymmetric Digital Subscriber Line) according to claim 1 system, it is characterized in that, described butterfly operation module (13) also comprises selector (301), selector (302) and butterfly processing element (300), selector (301) receives the data from dual port RAM A or dual port RAM (12), export to butterfly processing element (300), twiddle factor in the twiddle factor module (14) is also delivered to butterfly processing element (300) and is used for calculating, and result of calculation is exported to dual port RAM C or dual port RAM (12) through selector (302).

3, the discrete Fourier transform equipment in the ADSL (Asymmetric Digital Subscriber Line) according to claim 2 system, it is characterized in that, described butterfly processing element (300) comprises 1 conjugator (3001), 3 selectors (3003,3004,3005), 2 adders (3007,3008), 2 subtracters (3006,3009) and 1 complex multiplier (3002); Two data X of selector (301) output _l(m1) and X _l(m2), data X wherein _l(m1) enter adder (3007) and subtracter (3009), data X respectively _l(m2) through data and data X behind the conjugator (3001) _l(m2) enter in the selector (3003); Data X _l(m1) and the dateout of selector (3003) simultaneously in adder (3007) and subtracter (3009), carry out plural plus and minus calculation, the difference of subtracter (3009) output multiplies each other in complex multiplier (3002) with corresponding twiddle factor, the multiplication of complex numbers of gained is carried out plural plus and minus calculation respectively with the output of adder (3007) again in adder (3008) and subtracter (3006), gained and deliver in the selector (3004) with the result of adder (3007), the result of the difference of gained and complex multiplier (3002) delivers in the selector (3005).

4, the discrete Fourier transform equipment in the ADSL (Asymmetric Digital Subscriber Line) according to claim 2 system is characterized in that described selector (301,302) all is alternative selectors, controls its output result according to computing progression stage;

When carrying out the first order computing of progression stage=1, the data among selector (301) the output dual port RAM A, and other computings at different levels, i.e. progression stage=2～9 o'clock, the data in selector (301) the output dual port RAM (12);

When progression stage＜9, selector (302) exports result of calculation in the dual port RAM (12) to, and when progression stage=9, selector (302) deposits result of calculation among the dual port RAM C in.

5, the discrete Fourier transform equipment in the ADSL (Asymmetric Digital Subscriber Line) according to claim 3 system is characterized in that described selector (3003,3004,3005) all is alternative selectors, controls its output result according to computing progression stage;

When progression stage=1, selector (3003) output X _l(m2) conjugation data, when stage＞1, selector (3003) dateout X _l(m2);

When stage=1, selector (3004) output X _L+1(m1) equal the result of adder (3008), selector (3005) output X _L+1(m2) equal the result of subtracter (3006); When stage＞1, selector (3004) output X _L+1(m1) equal the result of adder (3007), selector (3005) output X _L+1(m2) equal the result of complex multiplier (3002).

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