CN1464551A - Multi-chip packaging - Google Patents
Multi-chip packaging Download PDFInfo
- Publication number
- CN1464551A CN1464551A CN02123060A CN02123060A CN1464551A CN 1464551 A CN1464551 A CN 1464551A CN 02123060 A CN02123060 A CN 02123060A CN 02123060 A CN02123060 A CN 02123060A CN 1464551 A CN1464551 A CN 1464551A
- Authority
- CN
- China
- Prior art keywords
- transparency carrier
- polycrystalline sheet
- wafer
- encapsulation
- sheet encapsulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
The invention discloses a multi-chip packaging comprising a transparent substrate, two chips, a plurality of connecting ends and a packing colloid. The transparent substrate at least arranges a conductive layer for electrical interconnection, the chips are arranged on the substrate and forms together with the conductive layer a circuit system, and the connecting ends are linked electrically with the circuit system through a plurality of conducting wires, to facilitate the circuit system to link electrically with the outside through the conducting wires and the connecting ends, and the packing colloid covers at least the conducting wires. The transparent substrate can be glass substrate to form the conducting layer with fine patterns thereon and to provide extreme high insulativity and extreme low dielectric constant.
Description
Technical field
The present invention relates to polycrystalline sheet encapsulation technology, particularly about a kind of polycrystalline sheet encapsulation with transparency carrier.
Background technology
When the function of electronic system is become stronger day by day, and its volume is constantly pursued when compact, known integrated circuit encapsulation (IC package) and printed circuit board (PCB) (printed circuit board) packaging technology can not satisfy the demand of reduced volume, therefore, it is most obvious the function of more complexity to be integrated (integrate) trend in single IC for both wafer (IC chip).
Yet, present ic manufacturing technology has the processing procedure that differs widely at the wafer of difference in functionality, for example, logical integrated circuit (logic IC) is very big with the processing procedure otherness of memory integrated circuit (memory IC), therefore be not easy logical integrated circuit and memory integrated circuit are incorporated in the same wafer, and can make two integrated circuits performance best-of-breed functionality simultaneously, so with different chips be encapsulated in the same packaging body technology just thereby produce, it is so-called polycrystalline sheet encapsulation (MCP, multi-chip package).
From the above, when the technical development of polycrystalline sheet encapsulation after to a certain degree, the joint dysfunction that is positioned between each wafer of same packaging body can be considered as a system, and this promptly is called SIP (system inpackage).
At present, the polycrystalline sheet is packaged with many types, and its manufacture method also is not quite similar, and below enumerates structure and shortcoming thereof that two kinds of polycrystalline sheet encapsulated types illustrate known polycrystalline sheet encapsulation.
A kind of polycrystalline sheet encapsulation that utilizes lead frame (lead frame) to carry a plurality of wafers at first is described, please refer to polycrystalline sheet encapsulation 1 shown in Figure 1, known and comprise a lead frame 11, at least two wafers 13, plural conductive line 15 and an adhesive body (molding compound) 17.Wherein, each wafer 13 is arranged on the lead frame 11, and conductor wire 15 engages the metal wire of (bonding) each wafer 13 and lead frame 11 respectively, and adhesive body 17 coated wire framves 11, each wafer 13 and each conductor wire 15.In polycrystalline sheet encapsulation 1, utilize the metal wire in the lead frame 11 to be connected to each other (interconnect) between each wafer 13, that is be, each wafer 13 is engaged to lead frame 11 by conductor wire 15 earlier, and the metal wire via lead frame 11 allows each wafer 13 be connected to each other then.Yet, being familiar with this operator all understands, the processing procedure of making known polycrystalline sheet encapsulation 1 and the processing procedure of making traditional single-chip encapsulation are much at one, wherein, lead frame 11 is subject to traditional manufacturing technology and can't has superfine pattern (fine pattern), so it can't be applied to connect the wafer of the high pin number of tool (highpin-count).In addition, because lead frame 11 is a single layer structure, so can't forming the form of intersection, limited its metal wire the complexity of the circuit layout (layout) that metal wire can provide, therefore, for solving the problem that metal wire can't intersect, have to utilize the metal wire of conductor wire short circuit that jumper connection is desired again, yet, just make processing procedure complicated more thus, but also can increase the volume of prepared polycrystalline sheet encapsulation 1.
Next illustrates a kind of BGA of utilization (spherical grid array type, ball grid array) substrate carries the polycrystalline sheet encapsulation of a plurality of wafers, please refer to shown in Figure 2ly, another known polycrystalline sheet encapsulation 2 comprises a BGA substrate 21, at least two wafers 23, plural conductive line 25 and an adhesive body 27.Wherein, the material of BGA substrate 21 is generally the resinousness material, and the last plane of BGA substrate 21 is formed with a plurality of fingers (finger) and interior pin (inner lead), the lower plane of BGA substrate 21 is formed with a plurality of tin balls (solder ball) 211, each wafer 23 is arranged on the last plane of BGA substrate 21, conductor wire 25 engages each finger of each wafer 23 and BGA substrate 21 respectively, and adhesive body 27 coats BGA substrates 21, each wafer 23 and each conductor wire 25.In polycrystalline sheet encapsulation 2, utilize the finger and the interior pin of BGA substrate 21 to be connected to each other between each wafer 23, that is be, each wafer 23 is engaged to the finger of BGA substrate 21 earlier by conductor wire 25, allow each wafer 23 be connected to each other via the interior pin that is connected with each finger then, and each wafer 23 electrically connect with outside via finger, interior pin and tin ball.Allly be familiar with this operator and all understand, BGA substrate 21 has the plural conductive layer and forms interior pin, so can between each wafer 23, provide than complicated circuit and superfine pattern, and each wafer 23 can be to be arranged on the BGA substrate to cover crystalline substance (flip-chip) mode, so can reduce, need not use conductor wire 25 even, and then can simplify the processing procedure of making polycrystalline sheet encapsulation 2, and effectively control its volume.Yet, the cost of BGA substrate is higher, and because the thermal coefficient of expansion of the BGA substrate 21 of resinousness material is big than the thermal coefficient of expansion that is the wafer 23 of material with silicon usually, so when wafer 23 was arranged on the BGA substrate 21 to cover crystal type, the reliability (reliability) of prepared polycrystalline sheet encapsulation 2 just can reduce.
In addition, because the insulating properties of BGA substrate 21 is limited, so the finger of BGA substrate 21 and interior pin when transmitting high-frequency signal, just can cause the decay of high-frequency signal because of the parasitic capacitance that is produced and parasitic leakage resistance.
In sum, because the encapsulation of known polycrystalline sheet normally utilizes lead frame or BGA substrate to carry a plurality of wafers and the circuit that connects each wafer is provided, so the encapsulation of known polycrystalline sheet is not the pattern (when using lead frame) that can't provide superfine, need higher cost (when using the BGA substrate) exactly, and known polycrystalline sheet encapsulation (when particularly using the BGA substrate) also has high-frequency signal and can decay because of parasitic capacitance and parasitic leakage resistance, and the different problems such as reliability reduction that cause with the thermal coefficient of expansion of BGA substrate of wafer.Therefore, how can solve the problem of the above-mentioned use lead frame or the polycrystalline sheet of BGA substrate encapsulation, real is one of important topic of current polycrystalline sheet encapsulation technology.
Summary of the invention
At the problems referred to above, purpose of the present invention is for providing a kind of polycrystalline sheet encapsulation that superfine pattern can be provided.
Another object of the present invention is for providing a kind of polycrystalline sheet encapsulation that can effectively reduce the phenomenon that high-frequency signal decays because of parasitic capacitance and parasitic leakage resistance.
Another purpose of the present invention is for providing a kind of polycrystalline sheet encapsulation that can avoid the reliability that caused because of internal material thermal coefficient of expansion difference to reduce.
For achieving the above object, the technical solution used in the present invention is as follows:
A kind of polycrystalline sheet encapsulation comprises a transparency carrier, at least two wafers (chip), a plurality of link and an adhesive body.At least be laid with one on this transparency carrier as the conductive layer that electrically interconnects (electrical inter-connection) usefulness, and these wafers are arranged on the transparency carrier and constitute a Circuits System jointly with conductive layer, and these links electrically connect via plural conductive line (wire) and Circuits System, so that Circuits System can electrically connect with outside by these conductor wires and these links, and adhesive body coats these conductor wires at least.
Owing to utilize transparency carrier to carry these wafers according to polycrystalline sheet encapsulation of the present invention, and transparency carrier can be a glass substrate, so can use present manufacturing technology forms superfine pattern on transparency carrier conductive layer; In addition, transparency carrier, especially glass substrate, high insulating properties and extremely low dielectric constant can be provided, to reduce the phenomenon that high-frequency signal is decayed because of parasitic capacitance and parasitic leakage resistance, and glass substrate material and semiconductor wafer material coefficient of thermal expansion coefficient are approaching, so can avoid reducing because of the reliability that polycrystalline sheet encapsulation internal material thermal coefficient of expansion difference is caused.
Description of drawings
Fig. 1 is the schematic diagram of known polycrystalline sheet encapsulation, and it utilizes the lead frame bearing wafer;
Fig. 2 is the schematic diagram of another known polycrystalline sheet encapsulation, and it utilizes BGA base plate carrying wafer;
Fig. 3 is that wherein wafer electrically connects by the conductive layer of conductor wire and transparency carrier according to the schematic diagram of the polycrystalline sheet encapsulation of preferred embodiment of the present invention;
Fig. 4 is the schematic diagram according to the encapsulation of the polycrystalline sheet of another preferred embodiment of the present invention, and wherein the wafer utilization covers that crystal type is glutinous to be placed on the conductive layer of transparency carrier.
Embodiment
Below enumerate preferred embodiment, and with reference to relevant drawings, technical scheme of the present invention, feature and effect are described in further detail, wherein components identical is marked with identical reference marks.
Polycrystalline sheet encapsulation according to preferred embodiment of the present invention comprises a transparency carrier, at least two wafers, a plurality of link and an adhesive body.
In the present invention, each wafer can utilize conductor wire joining technique, Flip Chip or other encapsulation technologies to be arranged on the transparency carrier, below is the example explanation with conductor wire joining technique and Flip Chip respectively.
Please refer to shown in Figure 3ly, comprise a transparency carrier 31, two wafers 33, a plurality of link 35, plural conductive line 37 and an adhesive body 39 according to the polycrystalline sheet of preferred embodiment of the present invention encapsulation 3.In the present embodiment, transparency carrier 31 is a glass substrate, and the last plane of transparency carrier 31 forms a conductive layer 311, and it is laid with the circuit pattern of required circuit layout.Because the material of transparency carrier 31 is a glass, forms superfine pattern so can use present technology, that is is that conductive layer 311 can have superfine circuit pattern.Allly be familiar with this operator and should understand, in known wire-frame type encapsulation, lead frame the minimum feature that can provide usually more than 100 μ m; In the encapsulation of known BGA substrate-type, the BGA substrate the minimum feature that can provide usually more than 30 μ m; And in the polycrystalline sheet encapsulation 3 of present embodiment, the minimum feature that is provided on the glass substrate can utilize present manufacturing technology to reach 3 μ m, even 1 μ m.In the present embodiment, the material of conductive layer 311 can be the material of tool conductivity such as metal or alloy.
In addition, utilize present manufacturing technology can on glass substrate, form plural layer conductive layer (multi-layer metal pattern) (not shown), it forms an insulating barrier respectively between each conductive layer, for example silicon nitride (Silicon Nitride), silica (Silicon Oxide) etc., and form plurality of openings in each insulating barrier, therefore, each conductive layer can be connected to each other by these perforates, so just can access more complicated circuit layout, so that produce the polycrystalline sheet encapsulation of powerful SIP.
From the above, can more be formed with a pad portion (pad), in order to carrying transparency carrier 31 (not shown) at the downside of transparency carrier 31.
These wafers 33 utilize viscose to stick and place on the transparency carrier 31, and each wafer 33 is electrically connected to the conductive layer 311 of transparency carrier 31 respectively by conductor wire 37, it is aforesaid conductor wire joining technique, therefore, each wafer 33 just can be connected to each other by the circuit layout of conductive layer 311 and transmission signals, so that constitute required Circuits System jointly by wafer 33 and conductive layer 311, and then given play to the power of required Circuits System.Wherein, each wafer 33 can be respectively logical integrated circuit element, memory integrated circuit element or optoelectronic IC element, as optical diode (photo diode).
These links 35 can be to be positioned at around the transparency carrier 31, and electrically connect by the conductive layer 311 of plural conductive line 37 with transparency carrier 31, therefore, each wafer 33 just can electrically connect with transmission signals with outside by circuit and these links 35 of conductive layer 311.In addition, as shown in Figure 3, each wafer 33 also can directly electrically connect with these links 35 by these conductor wires 37 according to the demand that connects, and therefore, each wafer 33 just can electrically connect with outside by conductor wire 37 and these links 35.In the present embodiment, link 35 can be known finger (finger) or pin (lead) etc.
As mentioned above, polycrystalline sheet encapsulation 3 according to preferred embodiment of the present invention is an independent and powerful system, its function depends on the design of employed each wafer, and by these links, polycrystalline sheet encapsulation 3 can receive from the signal of outside carrying out logical operation or to store data, and can output signal use for extraneous other system or equipment.
In addition, please refer to shown in Figure 4ly, comprise a transparency carrier 41, two wafers 43, a plurality of link 45, plural conductive line 47 and an adhesive body 49 according to the polycrystalline sheet of another preferred embodiment of the present invention encapsulation 4.In the present embodiment, the last plane of transparency carrier 41 forms a conductive layer 411, and it is laid with the circuit pattern of required electrical interconnective circuit layout.Relevant for the explanation of transparency carrier 41 transparency carrier 31 (as shown in Figure 3) as the aforementioned, so no longer set forth.
What these wafers 43 utilizations were at present common covers crystal type with anisotropy conducting film (ACF, AnisotropicConducting Film) glutinous placing on the transparency carrier 41, the weld pad conductive layer 411 direct respectively and transparency carrier 41 that is each wafer 43 electrically connects, therefore, each wafer 43 just can electrically connect mutually and transmission signals by the circuit layout of conductive layer 411, so that constitute required Circuits System jointly by wafer 43 and conductive layer 411, and then given play to the power of required system.Wherein, each wafer 43 can be respectively logical integrated circuit element, memory integrated circuit element or optoelectronic IC element, as optical diode.
These links 45 can be to be positioned at around the transparency carrier 41, and electrically connect by the conductive layer 411 of plural conductive line 47 with transparency carrier 41, therefore, each wafer 43 just can electrically connect and switching signal with outside by circuit and these links 45 of conductive layer 411.In the present embodiment, link 45 can be known finger (finger) or pin (lead) etc.
Adhesive body 49 utilizes manufacture procedure of adhesive to form, so that coat these conductor wires 47 at least.In the present embodiment, adhesive body 49 coats the link 45 and the conductor wire 47 of transparency carrier 41, wafer 43, part.
As mentioned above, be packaged in transparency carrier (as glass substrate) according to polycrystalline sheet of the present invention and go up formation conductive layer (or even plural conductive layer), and be applied to the successful example of industry from the technology that forms conductive layer at glass substrate, can on glass substrate, form superfine pattern according to present technology, and 30 μ m that its live width can be provided much smaller than the BGA substrate and the degree that reaches 3 μ m, so be enough to deal with the demand that high pin number connects (high pin count interconnection) according to polycrystalline sheet encapsulation of the present invention; And along with the development of industry, the technology that forms conductive layer on glass substrate has been the technology of low cost and high maturity, and it is will be than known BGA substrate more cheap and reliability is high therefore to utilize this technology to make required glass substrate.
From the above, because glass substrate is the material of high-insulativity and low-k, especially under high frequency, still can keep this characteristic, so when the conductive layer on the glass substrate during at transmitting high-frequency signal, more can not cause the decay of signal, thereby can improve the performance of circuit because of parasitic capacitance, parasitic leakage resistance etc.When particularly including RF chip (RF chip) in the encapsulation of polycrystalline sheet, above-mentioned characteristics are more remarkable.
In addition, because glass substrate material and semiconductor wafer material coefficient of thermal expansion coefficient are approaching, therefore wafer is being sticked the reliability that still can keep product when placing on the glass substrate to cover crystal type.
In addition, use transparency carrier according to polycrystalline sheet encapsulation of the present invention, so when sticking crystalline substance (dieattaching) processing procedure, as cover brilliant processing procedure, can more easily carry out the action of wafer aligned transparency carrier, and it is also most simple to utilize optical check to test process results.In addition, use transparency carrier can also increase the range of application of polycrystalline sheet encapsulation, for example, when the wafer of polycrystalline sheet encapsulation is photoinduction element (optical sensor) or photocell (light emitter), wafer can utilize light signal to do the signal transmission with the external world, at this moment, because the light-permeable of transparency carrier, so light signal can directly penetrate transparency carrier and directly transmit between the wafer and the external world, and the encapsulation of polycrystalline sheet just can be to link up interface (optical communication interface) as a light signal.For example, polycrystalline sheet encapsulation 4 as shown in Figure 4 can allow adhesive body 49 only be covered in transparency carrier 41 upsides, so can only be separated with transparency carrier 41 between the wafer 43 and the external world, so light signal can directly transmit between wafer 43 and outside through transparency carrier 41.In addition, as previously mentioned, transparency carrier 41 downsides can be provided with a pad portion (not shown) in order to carrying transparency carrier 41, and its material can be transparent material, so that light signal can transmit smoothly.
In sum, owing to utilize transparency carrier to carry these wafers according to polycrystalline sheet encapsulation of the present invention, and transparency carrier can be a glass substrate, so can use present manufacturing technology forms superfine pattern on transparency carrier conductive layer; In addition, use transparency carrier, especially glass substrate, high insulating properties and extremely low dielectric constant can be provided, to reduce the phenomenon that high-frequency signal is decayed because of parasitic capacitance and parasitic leakage resistance, and glass substrate material and semiconductor wafer material coefficient of thermal expansion coefficient are approaching, so can avoid reducing because of the reliability that polycrystalline sheet encapsulation internal material thermal coefficient of expansion difference is caused.
The above only is an illustrative, but not is restricted.Anyly do not break away from spirit of the present invention and category, and, all should be included within the claim scope of this case its equivalent modifications of carrying out or change.
Claims (11)
1. polycrystalline sheet encapsulation is characterized in that: this polycrystalline sheet encapsulation comprises:
One transparency carrier, it is laid with one at least as the conductive layer that electrically interconnects usefulness;
At least two wafers, it is arranged on this transparency carrier, and constitutes a Circuits System jointly with this conductive layer;
A plurality of links, it electrically connects via plural conductive line and this Circuits System, and in order to electrically connect this Circuits System with outside; And
One adhesive body, it coats these conductor wires at least.
2. polycrystalline sheet encapsulation as claimed in claim 1 is characterized in that: more comprise:
One pad portion, it is positioned at this transparency carrier one side to carry this transparency carrier.
3. polycrystalline sheet encapsulation as claimed in claim 1, it is characterized in that: wherein this transparency carrier is a glass substrate.
4. polycrystalline sheet encapsulation as claimed in claim 1, it is characterized in that: wherein this adhesive body more covers these wafers.
5. polycrystalline sheet encapsulation as claimed in claim 1, it is characterized in that: wherein this adhesive body more coats this transparency carrier.
6. polycrystalline sheet as claimed in claim 1 encapsulation is characterized in that: wherein this adhesive body more covers these links to small part.
7. polycrystalline sheet encapsulation as claimed in claim 1, it is characterized in that: wherein at least one wafer is arranged on this transparency carrier to cover crystal type.
8. polycrystalline sheet encapsulation as claimed in claim 7 is characterized in that: wherein carry out optical signal transmission with this wafer that covers the crystal type setting through this transparency carrier and outside.
9. polycrystalline sheet encapsulation as claimed in claim 1 is characterized in that: wherein at least one wafer engages (wire bonding) mode with routing and is arranged on this transparency carrier.
10. polycrystalline sheet encapsulation as claimed in claim 1 is characterized in that: wherein at least one link electrically connects via the conductive layer of this conductor wire and this Circuits System, to electrically connect this Circuits System with outside.
11. polycrystalline sheet encapsulation as claimed in claim 1 is characterized in that: wherein at least one link electrically connects via at least one wafer of this conductor wire and this Circuits System, to electrically connect this Circuits System with outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02123060A CN1464551A (en) | 2002-06-11 | 2002-06-11 | Multi-chip packaging |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02123060A CN1464551A (en) | 2002-06-11 | 2002-06-11 | Multi-chip packaging |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1464551A true CN1464551A (en) | 2003-12-31 |
Family
ID=29743413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN02123060A Pending CN1464551A (en) | 2002-06-11 | 2002-06-11 | Multi-chip packaging |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1464551A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9190393B1 (en) | 2013-09-10 | 2015-11-17 | Delta Electronics, Inc. | Low parasitic capacitance semiconductor device package |
-
2002
- 2002-06-11 CN CN02123060A patent/CN1464551A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9190393B1 (en) | 2013-09-10 | 2015-11-17 | Delta Electronics, Inc. | Low parasitic capacitance semiconductor device package |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3762844B2 (en) | Opposite multichip package | |
| US20020066952A1 (en) | Semiconductor device having an interconnecting post formed on an interposer within a sealing resin | |
| US6759753B2 (en) | Multi-chip package | |
| CN1702861A (en) | Semiconductor device with a plurality of ground planes | |
| CN1602548A (en) | Semiconductor package device and method of manufacturing and testing the same | |
| KR930004244B1 (en) | Hybrid type resin sealed semiconductor device | |
| JP2001250836A (en) | Semiconductor device and its manufacturing method | |
| KR20070005745A (en) | Semiconductor package having dual interconnection form and manufacturing method thereof | |
| US20070130554A1 (en) | Integrated Circuit With Dual Electrical Attachment Pad Configuration | |
| US7307352B2 (en) | Semiconductor package having changed substrate design using special wire bonding | |
| KR20050021905A (en) | Package for a semiconductor device | |
| US20040058477A1 (en) | Integrated circuit package and manufacturing method therefor | |
| CN101266955B (en) | Semiconductor device and its making method | |
| US20060138613A1 (en) | Integrated circuit package with inner ground layer | |
| KR100632469B1 (en) | Semiconductor chip package | |
| WO1997037374A2 (en) | Method of packaging multiple integrated circuit chips in a standard semiconductor device package | |
| US7851899B2 (en) | Multi-chip ball grid array package and method of manufacture | |
| CN1464551A (en) | Multi-chip packaging | |
| US20080283982A1 (en) | Multi-chip semiconductor device having leads and method for fabricating the same | |
| KR100207902B1 (en) | Multi chip package using lead frame | |
| US11309288B2 (en) | Electronic system, die assembly and device die | |
| Yu et al. | Integrated Circuit Package Types | |
| CN218447901U (en) | Semiconductor packaging structure | |
| CN211208440U (en) | Three-dimensional packaging structure integrating chip and antenna | |
| KR100349561B1 (en) | Lsi package and inner lead wiring method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: QIMENG TECHNOLOGY CO., LTD. Free format text: FORMER OWNER: ZHAO YUANREN Effective date: 20060324 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20060324 Address after: 2, building 3, No. three, section 88, Chongqing North Road, Taipei, Taiwan Applicant after: Qimeng Science & Technology Co., Ltd. Address before: Kaohsiung city of Taiwan Province Applicant before: Zhao Yuanren |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |