CN1459869A - Single layer multisilicon crystal electro erasible programmable read-only storage - Google Patents
Single layer multisilicon crystal electro erasible programmable read-only storage Download PDFInfo
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- CN1459869A CN1459869A CN 02120387 CN02120387A CN1459869A CN 1459869 A CN1459869 A CN 1459869A CN 02120387 CN02120387 CN 02120387 CN 02120387 A CN02120387 A CN 02120387A CN 1459869 A CN1459869 A CN 1459869A
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- grid
- programmable read
- electro
- memory
- pmos transistor
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Abstract
A single-layer polysilicon EEPROM has the serially connected two PMOS transistor formed on N trap of P substrate. The first PMOS transistor has a float gate, a doped P drain region and a doped P source region used also as the drain of the second PMOS transistor. The second PMOS transistor has a gate, and a doped P source region. An erasing grid is formed in P-type substrate.
Description
Technical field
The present invention relates to a kind of semiconductor storage and method of operation thereof, be particularly related to a kind of single level polysilicon (single-poly) electro-erasable programmable read-only memory (Electrically ErasableProgrammable Read Only Memory, be designated hereinafter simply as EEPROM), it has, and power consumption is low, write/erase efficient height, can repeat to write and plurality of advantages such as density height.Single level polysilicon EEPROM of the present invention can be compatible with standard CMOS process especially.In addition, single level polysilicon EEPROM of the present invention utilizes channel hot electron to inject (channel hot electron injection, CHEI) mechanism is carried out write operation, and have the grid of wiping (erase gate), can utilize edge Fule nuohan (edge FN) mechanism to carry out quick erase operation.
Background technology
EEPROM or quickflashing EEPROM (flash EEPROM) belong to nonvolatile memory, and it has to cut off the electricity supply still can possess the advantage of memory content, and has the function that repeatable read is gone into data, add transmission fast, so application is very extensive.In many information, communication and consumption electronic products, all nonvolatile memory is treated as necessary element.And along with small size portable type electronic product personal digital assistant (personal digital assistant for example, PDA) or the demand of mobile phone increase day by day, (system on a chip, demand SOC) also increases thereupon to include the embedded chip (embedded chip) of EEPROM and logical circuit or system combination chip simultaneously.For this reason, EEPROM certainly will write efficient, low cost and highdensity direction towards CMOS process compatible, low power consumption, height in the future to be developed, and just can meet the demand of product in the future.
Fig. 1 is the generalized section of existing EEPROM unit 10.As shown in Figure 1, existing EEPROM unit 10 includes a NMOS structure 28 and a PMOS structure 30, and both separate by an insulation field oxide 24.NMOS structure 28 is formed on the P type substrate 12, includes one first floating grid (floating gate), 32, one N
+A source doping region 14 and a N
+Drain doping region 16.PMOS structure 30 is formed on the N type ion trap 18, includes one second floating grid 34, a P
+A source doping region 20 and a P
+Drain doping region 22.In addition, at next-door neighbour P
+Source doping region 20 1 sides are injected with a heavy doping (heavily doped) N type raceway groove Resistance (channel stop region) 38, and this N type raceway groove Resistance 38 is positioned at the below of second floating grid 34.First floating grid 32 and second floating grid 34 also are connected by a floating grid lead 36, make first floating grid 32 and second floating grid 34 keep same potential.When producing corresponding current potential when first floating grid 32 response one control-grid voltages, second floating grid 34 will have the current potential identical with first floating grid 32 owing to the connection of floating grid lead 36, and use attraction via P
+The accelerated electron that exhaustion region produced of source doping region 20 and N type raceway groove Resistance 38 and electronics is limited in second floating grid 34.
Existing EEPROM unit 10 has following shortcoming.At first, existing EEPROM unit 10 is made of a PMOS transistor 30 and a nmos pass transistor 28, and shared chip unit are is bigger; Secondly, existing EEPROM unit 10 needs extra N type raceway groove Resistance 38; Moreover existing EEPROM unit 10 must be electrically connected first floating grid 32 and second floating grid 34 with floating grid lead 36; In addition, needing field oxide 24 between NMOS structure 28 and PMOS structure 30 isolates.As from the foregoing, it is excessive that existing EEPROM unit 10 consumes chip area, adds complex structure, increases technology cost and degree of difficulty.
Summary of the invention
In view of the above, main purpose of the present invention is to provide the single level polysilicon eeprom structure of a kind of high density and low power consumption.
Another object of the present invention is to provide a kind of power saving high-density single layer polysilicon eeprom structure and method of operation thereof, simultaneously its manufacture method can with the traditional cmos process compatibility.
In a preferred embodiment of the invention, a kind of single layer multisilicon crystal electro erasible programmable read-only storage is disclosed, include one the one PMOS transistor and one the 2nd PMOS transistor series connection the one PMOS transistor, wherein a PMOS transistor and the 2nd PMOS transistor are formed on the N type trap of a P type substrate, and a PMOS transistor includes a floating grid, one the one P
+Drain doping region and one the one P
+Source doping region, the 2nd PMOS transistor include a grid and one the 2nd P
+Source doping region, and the transistorized P of a PMOS
+Source doping region is used as the transistorized drain electrode of the 2nd PMOS simultaneously; And one wipe grid (erase gate) and be formed in this P type substrate, and in abutting connection with this floating grid.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the generalized section of existing EEPROM unit;
Fig. 2 is the part top view of single level polysilicon EEPROM layout according to the preferred embodiment of the invention;
Fig. 3 A is along the section enlarged diagram of tangent line AA ' among Fig. 2;
Fig. 3 B is the corresponding circuits figure of EEPROM unit among Fig. 3 A;
Fig. 4 represents to write the operational instances schematic diagram of " 1 ";
Fig. 5 grid voltage that to be the 2nd PMOS transistor obtained under to N type trap bias condition in different drain electrodes is to grid current figure; And
Fig. 6 is the part top view according to the single level polysilicon EEPROM layout of second embodiment of the invention.
Description of reference numerals in the accompanying drawing is as follows:
10 EEPROM unit, 12 P type substrates
14 N
+Source doping region 16 N
+Drain doping region
18 N type ion traps, 20 P
+Source doping region
22 P
+Drain doping region 24 field oxides
28 nmos pass transistors, 30 PMOS transistors
32 first floating grids, 34 second floating grids
36 floating grid leads, 38 N type raceway groove Resistance
100a single level polysilicon EEPROM unit
100c EEPROM unit, 100b EEPROM unit
101 the one PMOS transistors 102 the 2nd PMOS transistor
110 N type traps 120 are wiped grid
122 floating grids, 124 grids
132 P
+Drain doping region 134 P
+Doped region
136 P
+ Source doping region 150a contact plunger
160 contact plungers, 162 dielectric layers
170 bit lines, 200 P type substrates
122a floating grid oxide layer 124a gate oxide
Embodiment
Below promptly by Fig. 2 to Fig. 5 and table one explanation the preferred embodiments of the present invention.
At first see also Fig. 2, Fig. 2 is the part top view according to the single level polysilicon EEPROM layout of the preferred embodiment of the present invention.As shown in Figure 2, in a preferred embodiment of the invention, single level polysilicon EEPROM unit 100a includes one the one PMOS transistor 101 and one the 2nd PMOS transistor 102 is serially connected with a PMOS transistor 101.The one PMOS transistor 101 and the 2nd PMOS transistor 102 are formed on the N type trap 110 of a P type substrate 200 (zone shown in dotted line).The one PMOS transistor 101 includes a floating grid 122, a P
+A drain doping region 132 and a P
+Doped region 134.The 2nd PMOS transistor 102 includes a grid 124, a P
+A doped region and a P
+ Source doping region 136, and the P of a PMOS transistor 101
+ Doped region 134 is used as the drain electrode of the 2nd PMOS transistor 102 simultaneously.Floating grid of the present invention 122 is formed by single level polysilicon, and its top does not need yet, and is formed with control electrode.P
+Drain doping region 132 is electrically connected P via a contact plunger 150a with a bit line (not showing among Fig. 2)
+ Source doping region 136 is electrically connected one source pole line (source line) 142.In a preferred embodiment of the invention, source electrode line 142 is a P
+Doped region is with P
+ Source doping region 136 forms in same ion implantation step.Show EEPROM unit 100b and the EEPROM unit 100c of a similar among Fig. 2 in addition in EEPROM unit 100a, wherein EEPROM unit 100b has a contact plunger 150b and contact plunger 150a and is electrically connected on same bit lines (showing among Fig. 2), and EEPROM unit 100c has a contact plunger 150c and is electrically connected on another adjacent bit line (showing among Fig. 2).
Still consult Fig. 2, single level polysilicon EEPROM of the present invention unit 100 includes in addition to be wiped grid (erase gate) 120 and is formed in the P type substrate 200, and in abutting connection with floating grid 122.In a preferred embodiment of the invention, wiping grid 120 is a N
+Doped region.Wipe grid 120 via a contact plunger 160 external an erase gate pole tension (erase gate voltage, V
EG).The edgeFN effect that the erase operation utilization of single level polysilicon EEPROM of the present invention unit 100 is wiped between grid 120 and the floating grid 122 is carried out, and its detailed operation sequence is in following explanation.Be noted that in a preferred embodiment of the invention, wipe floating grid 122 definition that is infused in of grid 120 and carry out after finishing, therefore, it is overlapping with it not have the erase gate utmost point 120 in essence below floating grid 122.If have, also be after injection, to cause because of slight spread that thermal process produces owing to wiping grid 120.In addition, because floating grid 122 must adjacency be wiped grid 120, so floating grid 122 need leap N type trap 110 and P type substrates 200, extend to and wipe grid 120.In addition, between floating grid 122 and grid 124, do not need lead and link to each other, keep same potential person.
See also Fig. 3 A, Fig. 3 A is along the section enlarged diagram of tangent line AA ' among Fig. 2.As shown in Figure 3A, a PMOS transistor 101 is serially connected with the 2nd PMOS transistor 102.The one PMOS transistor 101 includes floating grid 122, P
+Drain doping region 132, P
+A source doping region 134 and a floating grid oxide layer 122a are located at floating grid 122 belows.The 2nd PMOS transistor 102 includes grid 124, gate oxide 124a and P
+ Source doping region 136, and via P
+ Source doping region 134 is connected with a PMOS transistor 101.P
+Drain doping region 132 is electrically connected with a bit line 170 via contact plunger 150, and contact plunger 150 is formed in the dielectric layer 162, for example BPSG, PSG, silicon dioxide or other similar dielectric material, and bit line 170 is formed on the dielectric layer 160.Floating grid oxide layer 122a of the present invention and gate oxide 124a can be identical with the thickness of grid oxide layer in the logical circuit, or optionally increase thickness.Anyway, eeprom structure of the present invention all can be compatible with the standard CMOS semiconductor technology.
See also Fig. 3 B and Fig. 3 A, Fig. 3 B is the corresponding circuits figure of EEPROM unit among Fig. 3 A.Shown in Fig. 3 B, during operation, the P of a PMOS transistor 101
+ Source doping region 134 imposes a bit-line voltage (bit line voltage, V
BL), floating grid 122 does not impose any voltage, that is keeps floating state.N type trap 110 imposes N type trap voltage (N-Well voltage, a V
NW).The 2nd PMOS transistor 102 is used as one and is selected transistor when operation, its grid 124, and (select gate SG), imposes one and selects grid voltage (select gate voltage, V maybe can be called the selection grid
SG) or word line voltage (word line voltage, V
WL), its P
+ Source doping region 136 imposes one source pole line voltage (source linevoltage, V
SL).In addition, 200 of P type substrates impose P type trap voltage (P-Well voltage, a V
PW).
Then, according to shown in the table 1, the method for operation of EEPROM of the present invention is described.See Table 1 first row, when carrying out a coding or programming operation (is example to write data " 1 "), word line voltage V
WLBe a low level voltage, for example import V
WL=0V.Bit-line voltage V
BLBe a level and word line voltage V
WLIdentical voltage, that is V
BL=0V.Non-selected word line then imposes a level and source electrode line voltage V
SLIdentical voltage, that is V
WL (un-selected)=5-7V.Non-selected bit line then imposes a level and source electrode line voltage V
SLIdentical voltage, that is V
BL (un-selected)=5-7V.Floating grid 122 keeps floating state.Source electrode line voltage V
SLBe a high level voltage, for example import V
SL=5-7V.N type trap voltage V
NWAlso be the voltage that a level is relatively higher than word line voltage, for example import V
NW=5-7V.P type trap voltage V
PWBe a level and word line voltage V
WLIdentical voltage, that is V
PW=0V.Erase gate pole tension V
EGBe a level word line voltage V
WLIdentical voltage, that is V
EG=0V.See Table 1 secondary series,, choose and bit-line voltage V for choosing as if being example to write data " 0 "
BLBe all a level and be higher than word line voltage V
WLVoltage, for example import V
BL=5-7V, other condition is the same.
See also Fig. 4, Fig. 4 represents to write the operational instances schematic diagram of " 1 ".As shown in Figure 4, be example with following operating condition: word line voltage V
WL=0V, bit-line voltage V
BL=0V, floating grid 122 keeps suspended state, source electrode line voltage V
SL=5V, N type trap voltage V
NW=5V, P type trap voltage V
PW=0V, erase gate pole tension V
EG=0V.Under above-mentioned operating condition, because floating grid 122 can obtain a low-voltage by capacitance coupling effect, for example-1～-2V, and the P type raceway groove of floating grid 122 belows is opened, hot electron can be via the P type raceway groove of opening, tunnelling is crossed floating grid oxide layer 122a, and is trapped in the floating grid 122.See also Fig. 5, Fig. 5 be the 2nd PMOS transistor 102 in different drain electrodes to N type trap 110 bias voltage (V
d=V
BL-V
NW) grid voltage that obtained under the condition is to grid current figure.As shown in Figure 5, at bias voltage V
dFor under-5V the condition, floating grid 122 by capacitance coupling effect obtain approximately-1～-the 2V low-voltage, at this moment, the raceway groove of the 2nd PMOS transistor 102 is just opened, and grid current is near maximum.In other words, under operator scheme of the present invention, grid current is to the ratio (I of drain current
g/ I
d) bigger, therefore when programming, can obtain preferred usefulness.
See Table 1 the 3rd row, when carrying out a read operation, the word line voltage V that chooses
WLBe a low level voltage, for example input voltage is 0V, the non-selected word line voltage V that arrives
WLBe a higher level voltage, for example input voltage is 3.3V.The bit-line voltage V that chooses
BLBe a low level voltage, for example input voltage is 1.8V, the non-selected bit-line voltage V that arrives
BLWith the non-selected word line voltage V that arrives
WLBe a higher level voltage, for example input voltage is 3.3V.Source electrode line voltage V
SL, N type trap voltage V
NWAnd erase gate pole tension V
EGAll with the non-selected word line voltage V that arrives
WLBe a higher level voltage, for example input voltage is 3.3V.P type trap voltage V
PWBe a level and the word line voltage V that chooses
WLIdentical voltage, that is V
PW=0V.
See Table 1 the 4th row, when (Erase) operation is wiped in execution one, word line voltage V
WLBe a low level voltage, for example input voltage is 0V.Bit-line voltage V
BLBe a low level voltage, for example input voltage is 0V.Source electrode line voltage V
SL, N type trap voltage V
NWAnd P type trap voltage V
PWBe a low level voltage, for example input voltage be 0～-5V.Erase gate pole tension V
EGThen import a high level voltage, for example input voltage is 5-7V.
In addition, another feature of the present invention is the erasing move initial stage, because the electronics in the floating grid causes the voltage V of bit line
BLReach whole channel region by raceway groove, and make the electronics in the floating grid be easy to wipe by wiping grid, and after erasing move continues for some time, electronics in the floating grid reduces and the raceway groove disappearance, erasing move slows down thereupon, this memory element no longer exists a large amount of electronics and is drawn out, and then avoids over-erasure (over-erase) phenomenon.
Fig. 6 shows second preferred embodiment of the present invention.As shown in Figure 6, the present invention also can be array architecture shown in Figure 6 except array architecture shown in Figure 2.Claim that at this framework shown in Figure 2 is framework I, and the array architecture among Fig. 6 is framework II.Framework I is applicable to the erasing move of the page/section (page/sector), and framework II then is applicable to the erase operation of byte/word joint (Byte/Byte).Framework II compared to Fig. 6 can obviously find out, framework I wipes grid N
+The zone) total by four floating grids, the trend of wiping grid is for parallel with bit line, framework II to wipe grid then shared with two floating grids, and these two floating grids adhere to different bit lines separately, therefore can adopt byte/word joint (Byte-by-Byte) mode to wipe.
According to the above, compare with existing skill, the present invention can operate under low-voltage, and because unique design of the present invention makes the 2nd PMOS transistor when raceway groove is just opened, grid current I
gNear maximum, under operator scheme of the present invention, grid current is to the ratio (I of drain current
g/ I
d) bigger, therefore have the advantage that power saving economizes energy, and when programming, can obtain preferred usefulness, and save the time of programming.In addition, utilize the design of wiping grid, make memory can carry out erase operation effectively.And, because the present invention uses two PMOS transistor series connections, significantly reduce the usable floor area of chip, make the present invention can apply to the high-density storage field.Moreover the present invention is simple in structure, can with traditional CMOS process compatible, more reduced cost of manufacture.
The above only is the preferred embodiments of the present invention, and all equalizations that claim is done according to the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
| Operation table | ?????????V SG | ??????????V BL | ????V EG | ????V SL | ??V NW | ?V PW | |||
| Selected WL | Not selected WL | Selected BL | Not selected BL | ||||||
| Programming | ”1” | ????0V | ???5～7V | ????0V | ???5～7V | ????0V | ????5～7V | ??5～7V | ??0V |
| ”0” | ????0V | ???5～7V | ????5～7V | ???5～7V | ????0V | ????5～7V | ??5～7V | ??0V | |
| Read | ????0V | ???3.3V | ????1.8V | ???3.3V | ????3.3V | ????3.3V | ??3.3V | ??0V | |
| Wipe | ??????????0V | ?????????0～5V | ????5～7V | ????0V | ??0V | ??0V | |||
Table one
Claims (10)
1. single layer multisilicon crystal electro erasible programmable read-only storage includes:
One the one PMOS transistor and one the 2nd PMOS transistor series connection the one PMOS transistor, wherein a PMOS transistor and the 2nd PMOS transistor are formed on the N type trap of a P type substrate, and a PMOS transistor includes a floating grid, one the one P
+Drain doping region and one the one P
+Source doping region, the 2nd PMOS transistor include a grid and one the 2nd P
+Source doping region, and the transistorized P of a PMOS
+Source doping region is used as the transistorized drain electrode of the 2nd PMOS simultaneously; And
One wipes grid is formed in this P type substrate, and in abutting connection with this floating grid.
2. electro-erasable programmable read-only memory as claimed in claim 1, wherein this to wipe grid be a N type doped region, be formed at this floating grid below.
3. electro-erasable programmable read-only memory as claimed in claim 2, wherein this N type doped region and this floating grid are not overlapping in essence.
4. electro-erasable programmable read-only memory as claimed in claim 2, wherein this is wiped and is provided with a floating grid oxide layer between grid and this floating grid.
5. electro-erasable programmable read-only memory as claimed in claim 1 is wherein at a predetermined drain bias V
dDown, this floating grid can obtain a low-voltage by a capacitance coupling effect, causes the transistorized P type raceway groove of the 2nd PMOS to be opened, and produces one near peaked grid current.
6. electro-erasable programmable read-only memory as claimed in claim 5, wherein this predetermined bias is about-5V.
7. electro-erasable programmable read-only memory as claimed in claim 1, wherein this floating grid top is not provided with a control grid.
8. electro-erasable programmable read-only memory as claimed in claim 1, wherein when operation during this electro-erasable programmable read-only memory, a predetermined grid bias of wiping can make the electronics of this floating grid wipe grid by the tunnelling mode from this with first a drain doping region voltage of being scheduled to pull out.
9. the operation of electro-erasable programmable read-only memory as claimed in claim 8, it can make this electro-erasable programmable read-only memory avoid the phenomenon of over-erasure to take place when erasing move.
10. the operation of electro-erasable programmable read-only memory as claimed in claim 8 should the predetermined grid bias of wiping be positive bias wherein, and should the first predetermined drain doping region voltage be back bias voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02120387 CN1229869C (en) | 2002-05-24 | 2002-05-24 | Single layer multisilicon crystal electro erasible programmable read-only storage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02120387 CN1229869C (en) | 2002-05-24 | 2002-05-24 | Single layer multisilicon crystal electro erasible programmable read-only storage |
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| Publication Number | Publication Date |
|---|---|
| CN1459869A true CN1459869A (en) | 2003-12-03 |
| CN1229869C CN1229869C (en) | 2005-11-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02120387 Expired - Lifetime CN1229869C (en) | 2002-05-24 | 2002-05-24 | Single layer multisilicon crystal electro erasible programmable read-only storage |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465662A (en) * | 2014-12-16 | 2015-03-25 | 无锡来燕微电子有限公司 | Monolayer polycrystalline EEPROM and preparation method thereof |
-
2002
- 2002-05-24 CN CN 02120387 patent/CN1229869C/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465662A (en) * | 2014-12-16 | 2015-03-25 | 无锡来燕微电子有限公司 | Monolayer polycrystalline EEPROM and preparation method thereof |
| CN104465662B (en) * | 2014-12-16 | 2017-04-12 | 无锡来燕微电子有限公司 | Monolayer polycrystalline EEPROM and preparation method thereof |
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|---|---|
| CN1229869C (en) | 2005-11-30 |
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