CN1455448A - Phase transformation memory and manufacturing method thereof - Google Patents
Phase transformation memory and manufacturing method thereof Download PDFInfo
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- CN1455448A CN1455448A CN 02119036 CN02119036A CN1455448A CN 1455448 A CN1455448 A CN 1455448A CN 02119036 CN02119036 CN 02119036 CN 02119036 A CN02119036 A CN 02119036A CN 1455448 A CN1455448 A CN 1455448A
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- epitaxial layer
- phase
- memory element
- change memory
- isolation structure
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Abstract
First, an N+polycrystal layer and an N- polycrystal layer are formed on a semiconductor substrate. The first shallow-channel isolation structure is formed in the N+ layer in order to isolate the prearranged character line region; and the second shallow-channel isolation structure is formed in the N- layer in order to isolate the prearranged P+ adulteration region. Next, the defined insulation layer is formed. N+ adulterating is carried out for the part of N- polycrystal layer in order to connect N+ adulteration region in N+ polycrystal layer. P+ is adulterated in the N+ polycrystal layer so as to form a P+ adulteration region. The, the contact plug across the insulation layer is formed on the N+ adulteration region and the P+ adulteration region respetively. Finally, an upper electrode, a phase change layer and a lower electrode are formed on the contact plug being as an electrod.
Description
Technical field
The present invention relates to a kind of internal memory, particularly relevant phase-change memory element and manufacture method thereof.
Background technology
Fig. 1 is for showing traditional phase-change memory element structure.This phase-change memory element structure comprises that semiconductor substrate 10, a N+ doped layer 12 are formed at at semiconductor-based the end 10, a N-doped layer 14 is formed on the N+ doped layer 12, a N+ doped region 16 is formed in the N-doped layer 14, a P+ doped region 18 is formed in the N-doped layer 14, an insulating barrier 20 is formed at at semiconductor-based the end 10, and insulating barrier 20 can be oxide skin(coating).Contact plunger 22 comprises a barrier layer 24 and a metal level 26.Electrode 28 is formed at respectively on each contact plunger 22, and electrode 28 has top electrode 34, phase change layer 32 and bottom electrode 30.
The N+ doped region in above-mentioned traditional phase-change memory element structure and the thickness of N-doped region and doping content are difficult to control to cause to adjust breakdown voltage (BDV).And easily puncture between adjacent P+/P+ interval and adjacent character line/character line (punch).Therefore size of components is difficult for dwindling.
Because semiconductor subassembly is towards the development of large scale integrated circuit assembly more, so dwindle characteristic line breadth and multiple stratification is necessary.
Summary of the invention
The object of the present invention is to provide a kind of phase-change memory element and manufacture method thereof, it is by using epitaxial layer and STI isolation structure of shallow trench (shallow trench isolation; STI) replace traditional implanting ions.The use epitaxial layer can increase the thickness of N+ doped region and N-doped region and control uniform doping content to adjust breakdown voltage (BDV).Use STI isolation structure of shallow trench can prevent the puncture (punch) between adjacent P+/P+ interval and adjacent character line/character line, thereby can significantly dwindle size of components.
According to above-mentioned purpose, the invention provides a kind of manufacture method of phase-change memory element, be applicable to the semiconductor substrate, at first on the above-mentioned semiconductor-based end, form a N+ epitaxial layer and a N-epitaxial layer.Then, in above-mentioned N+ epitaxial layer and N-epitaxial layer, form one first isolation structure of shallow trench to isolate predetermined character line district and in above-mentioned N-epitaxial layer, to form one second isolation structure of shallow trench to isolate predetermined P+ doped region.Secondly, form and define an insulating barrier and implement a N+ for the above-mentioned N-epitaxial layer of part and mix and electrically connect the N+ doped region of above-mentioned N+ epitaxial layer and implement a P+ for above-mentioned N+ epitaxial layer and mix to form a P+ doped region to form one.Then, on above-mentioned N+ doped region and above-mentioned P+ doped region, form a contact plunger that passes above-mentioned insulating barrier respectively.At last, on each above-mentioned contact plunger, form electrode with top electrode, phase change layer and bottom electrode.
The present invention provides a kind of phase-change memory element in addition, comprising: the semiconductor substrate; One N+ epitaxial layer was formed on this semiconductor-based end; One N-epitaxial layer is formed on this N+ epitaxial layer; One first isolation structure of shallow trench is formed in this N+ epitaxial layer and the N-epitaxial layer to isolate predetermined character line district; One P+ doped region is formed in this N-epitaxial layer; One second isolation structure of shallow trench is formed in this N-epitaxial layer to isolate this P+ doped region; One N+ doped region is formed in this N-epitaxial layer and electrically connects this N+ epitaxial layer; Contact plunger is formed at this N+ doped region and P+ doped region respectively; And electrode, be formed at respectively respectively on this contact plunger, have top electrode, phase change layer and bottom electrode.This first isolation structure of shallow trench also can be formed at this N+ epitaxial layer, N-epitaxial layer and at semiconductor-based the end.
Description of drawings
Fig. 1 shows the profile of traditional phase-change memory element structure.
Fig. 2 shows the top view according to the phase-change memory element structure of the embodiment of the invention.
Fig. 3 to Fig. 8 is the processing procedure profile according to the phase-change memory element of the embodiment of the invention.The semiconductor-based end of symbol description 100--; The 102--N+ epitaxial layer; The 104--N-epitaxial layer; 106--first isolation structure of shallow trench; 110--second isolation structure of shallow trench; The 114--N+ doped region; The 117--P+ doped region; The 118--contact plunger; The 128--electrode; The character line district that 108--is predetermined; The 126--top electrode; The 124--phase change layer; The 122--bottom electrode; The 119--barrier layer; The 120--metal level; The 111--insulating barrier; 200 character lines; The 300--bit line.
Embodiment
At first, please refer to Fig. 2, show top view according to the phase-change memory element structure of the embodiment of the invention.This phase-change memory element structure comprises semiconductor substrate 100; One insulating barrier 111 is formed at at semiconductor-based the end 100, and insulating barrier 111 can be oxide skin(coating).This phase-change memory element structure comprises a P+ doped region 117, a character line 200, a bit line 300, one first isolation structure of shallow trench 106, one second isolation structure of shallow trench 110.
Fig. 3 to Fig. 4 shows the AA ' profile according to Fig. 2, and Fig. 5 to Fig. 8 shows the BB ' profile according to Fig. 2.Please refer to Fig. 3, the embodiment of the invention at first provides semiconductor substrate 100, one N+ epitaxial layers 102 and a N-epitaxial layer 104 to continue and is formed at at semiconductor-based the end 100.N+ epitaxial layer 102 and N-epitaxial layer 104 can be implemented selectivity brilliant method of heap of stone and form, and the thickness of N+ epitaxial layer 102 is preferably 400 to 600 dusts, and the thickness of N-epitaxial layer 104 is preferably 800 to 1200 dusts.
Please refer to Fig. 4, in the semiconductor-based end 100, N+ epitaxial layer 102 and N-epitaxial layer 104, form one first isolation structure of shallow trench 106 to isolate predetermined character line district 108.The semiconductor-based end of the common first selective etch of the manufacture method of isolation structure of shallow trench to be forming shallow channel, and then insulating material is utilized chemical vapour deposition technique (chemical vapor deposition; CVD), aumospheric pressure cvd method (atmospheric pressure chemical vapor deposition for example; APCVD) or inferior aumospheric pressure cvd method (sub-atmospheric pressure chemicalvapor deposition; SACVD) or high density plasma enhanced chemical vapor deposition method (highdensity plasma CVD; HDP-CVD) materials such as silicon dioxide are inserted above-mentioned shallow channel, impose the above-mentioned earth silicon material of chemical mechanical milling method (CMP) planarization then, and stay isolation structure of shallow trench.
Please refer to Fig. 5, in N-epitaxial layer 104, form one second isolation structure of shallow trench 110 to isolate predetermined P+ doped region 109.Second isolation structure of shallow trench 110 can utilize said method to make.
Please refer to Fig. 6, on N-epitaxial layer 104, form an insulating barrier 111, utilize photoresistance 112 definition insulating barriers 111 afterwards.Insulating barrier 111 is preferably and uses Low Pressure Chemical Vapor Deposition to deposit tetraethyl-metasilicate (tetra-ethyl-ortho-silicate; TEOS).The thickness of insulating barrier 111 is preferably 2000 to 3000 dusts.Then use the anisotropic reactive ion etching to come etching isolation layer 111, implement a N+ via first opening 113 for N-epitaxial layer 104 again and mix to form the N+ doped region 114 of an electric connection N+ epitaxial layer 102 to form one first opening 113.The N+ doping is preferably execution arsenic or phosphonium ion cloth is planted, and concentration is preferably 10
15To 2 * 10
16Atoms/cm
2, energy is preferably 10 to 30keV.
Please refer to Fig. 7, utilize photoresistance 115 definition insulating barriers 111, then use the anisotropic reactive ion etching to come etching isolation layer 111, implement a P+ via second opening 116 for N-epitaxial layer 104 again and mix to form a P+ doped region 117 to form one second opening 116.P+ mixes to be preferably and implements the boron implanting ions, and concentration is preferably 10
15To 1 * 10
16Atoms/cm
2, energy is preferably 1 to 3keV.
Please refer to Fig. 8, form a contact plunger 118 respectively in first opening 113 and second opening 116, contact plunger 118 comprises a barrier layer 119 and a metal level 120.Barrier layer 119 is preferably and uses chemical vapour deposition technique to come depositing titanium nitride.Metal level 120 is preferably and uses physical vaporous deposition to come deposition of aluminum or copper.Then on contact plunger 118, form electrode 128 with top electrode 126, phase change layer 124 and bottom electrode 122.
Fig. 8 shows the phase-change memory element structure according to the embodiment of the invention, and this phase-change memory element structure comprises semiconductor substrate 100, a N+ epitaxial layer 102, a N-epitaxial layer 104, one first isolation structure of shallow trench 106 (being presented at Fig. 4), one second isolation structure of shallow trench 110, a N+ doped region 114, a P+ doped region 117, contact plunger 118 and electrode 128.
First isolation structure of shallow trench 106 is formed in the semiconductor-based end 100, N+ epitaxial layer 102 and the N-epitaxial layer 104 to isolate predetermined character line district 108 (being presented at Fig. 4).P+ doped region 117 is formed in the N-epitaxial layer 104.Second isolation structure of shallow trench 110 is formed in the N-epitaxial layer 104 to isolate P+ doped region 117.N+ doped region 114 is formed in the N-epitaxial layer 104 and electrically connects N+ epitaxial layer 102.Contact plunger 118 is formed at respectively on N+ doped region 114 and the P+ doped region 117.Electrode 128 is formed at respectively on each contact plunger 118, and electrode 128 has top electrode 126, phase change layer 124 and bottom electrode 122.
The thickness of N+ epitaxial layer 102 is preferably 400 to 600 dusts, and the thickness of N-epitaxial layer 104 is preferably 800 to 1200 dusts.First isolation structure of shallow trench 106 and second isolation structure of shallow trench 110 can utilize said method to make.
The present invention can increase the thickness of N+ doped region and N-doped region and control uniform doping content to adjust breakdown voltage (BDV) by using epitaxial layer.Use STI isolation structure of shallow trench can prevent the puncture (punch) between adjacent P+/P+ interval and adjacent character line/character line.Thereby can significantly dwindle size of components.
Though the present invention with preferred embodiment openly as above; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is as the criterion with claim.
Claims (20)
1. the manufacture method of a phase-change memory element is applicable to the semiconductor substrate, it is characterized in that, comprises the following steps:
On this semiconductor-based end, form a N+ epitaxial layer;
On this N+ epitaxial layer, form a N-epitaxial layer;
In this N+ epitaxial layer and this N-epitaxial layer, form one first isolation structure of shallow trench to isolate predetermined character line district;
In this N-epitaxial layer, form one second isolation structure of shallow trench to isolate predetermined P+ doped region;
On this N-epitaxial layer, form an insulating barrier;
Define this insulating barrier to form one first opening and to implement a N+ via this first opening for this N-epitaxial layer and mix to form the N+ doped region of this N+ epitaxial layer of electric connection;
Define this insulating barrier to form one second opening and to implement P+ doping to form a P+ doped region via this second opening and for this N-epitaxial layer;
In this first opening and this second opening, form a contact plunger respectively; And
In respectively forming electrode on this contact plunger with top electrode, phase change layer and bottom electrode.
2. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, the thickness of this N+ epitaxial layer is 400 to 600 dusts.
3. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, the thickness of this N-epitaxial layer is 800 to 1200 dusts.
4. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, this first isolation structure of shallow trench is to be formed in this N-epitaxial layer and this N+ epitaxial layer.
5. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, this first isolation structure of shallow trench is that execution dry type or Wet-type etching form.
6. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, this second isolation structure of shallow trench is that execution dry type or Wet-type etching form.
7. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, it is that execution arsenic or phosphonium ion cloth are planted that this N+ mixes.
8. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, the concentration that this N+ mixes is 10
15To 2 * 10
16Atoms/cm
2, energy is 10 to 30keV.
9. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, it is to implement the boron implanting ions that this P+ mixes.
10. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, the concentration that this N+ mixes is 10
15To 1 * 10
16Atoms/cm
2, energy is 1 to 3keV.
11. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, this insulating barrier is tetraethyl-metasilicate (tetra-ethyl-ortho-silicate; TEOS).
12. the manufacture method of phase-change memory element as claimed in claim 1 is characterized in that, the thickness of this insulating barrier is 2000 to 3000 dusts.
13. a phase-change memory element is characterized in that, comprising:
The semiconductor substrate;
One N+ epitaxial layer was formed on this semiconductor-based end;
One N-epitaxial layer is formed on this N+ epitaxial layer;
One first isolation structure of shallow trench is formed in this N+ epitaxial layer and this N-epitaxial layer to isolate predetermined character line district;
One P+ doped region is formed in this N-epitaxial layer;
One second isolation structure of shallow trench is formed in this N-epitaxial layer to isolate this P+ doped region;
One N+ doped region is formed in this N-epitaxial layer and electrically connects this N+ epitaxial layer;
Contact plunger is formed at respectively on this N+ doped region and the P+ doped region; And
Electrode is formed at respectively respectively on this contact plunger, has top electrode, phase change layer and bottom electrode.
14. phase-change memory element as claimed in claim 13 is characterized in that, the thickness of this N+ epitaxial layer is 400 to 600 dusts.
15. phase-change memory element as claimed in claim 13 is characterized in that, the thickness of this N-epitaxial layer is 800 to 1200 dusts.
16. phase-change memory element as claimed in claim 13 is characterized in that, this first isolation structure of shallow trench is to be formed in this N-epitaxial layer and this N+ epitaxial layer.
17. phase-change memory element as claimed in claim 13 is characterized in that, this first isolation structure of shallow trench is that execution dry type or Wet-type etching form.
18. phase-change memory element as claimed in claim 13 is characterized in that, this second isolation structure of shallow trench is that execution dry type or Wet-type etching form.
19. phase-change memory element as claimed in claim 13 is characterized in that, this N+ epitaxial layer is to implement selectivity brilliant method of heap of stone to form.
20. phase-change memory element as claimed in claim 13 is characterized in that, this N-epitaxial layer is to implement selectivity brilliant method of heap of stone to form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02119036 CN1284227C (en) | 2002-04-29 | 2002-04-29 | Phase transformation memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02119036 CN1284227C (en) | 2002-04-29 | 2002-04-29 | Phase transformation memory and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN1455448A true CN1455448A (en) | 2003-11-12 |
| CN1284227C CN1284227C (en) | 2006-11-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02119036 Expired - Fee Related CN1284227C (en) | 2002-04-29 | 2002-04-29 | Phase transformation memory and manufacturing method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026178B (en) * | 2006-02-25 | 2011-06-15 | 尔必达存储器股份有限公司 | Heat efficiency reduced minimum phase change memory and its making method |
-
2002
- 2002-04-29 CN CN 02119036 patent/CN1284227C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101026178B (en) * | 2006-02-25 | 2011-06-15 | 尔必达存储器股份有限公司 | Heat efficiency reduced minimum phase change memory and its making method |
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| Publication number | Publication date |
|---|---|
| CN1284227C (en) | 2006-11-08 |
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