CN1449033A - Metal welding pad of integrated circuit and method for making the same - Google Patents
Metal welding pad of integrated circuit and method for making the same Download PDFInfo
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- CN1449033A CN1449033A CN02108569A CN02108569A CN1449033A CN 1449033 A CN1449033 A CN 1449033A CN 02108569 A CN02108569 A CN 02108569A CN 02108569 A CN02108569 A CN 02108569A CN 1449033 A CN1449033 A CN 1449033A
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- metal pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The metal pad for IC locates on the metal pad window formed on the protecting layer via microphotographic and etching process. The present invention aims at raising the soldering reliability in soldering leads. Improved design is adopted and the metal soldering pad is extended properly on the protecting layer for wiring.
Description
Technical field
The invention relates to a kind of metal pad of integrated circuit, particularly about a kind of metal pad that is applicable to copper wiring/dielectric layer with low dielectric constant processing procedure and preparation method thereof.
Background technology
In order to pursue operation rate and bigger productive set density faster, the research unit of integrated circuit and manufacturer design with exerting one's heart and strength to the utmost and make critical size (Critcal Dimension invariably; CD) littler element.Show according to experiment, after the processing procedure of integrated circuit entered the technical field of 0.18 micron even 0.13 micron, the key factor that influences the element operation rate had been converted to resistance-capacitance sluggishness (RCdelay) effect of metal interconnecting (metal interconnection) from the width of gate.
Because of resistance and its sectional area of lead is inversely proportional to, along with the raising of the productive set density of integrated circuit, the live width and the thickness of metal interconnecting all dwindle thereupon, so its resistance just improves thereupon; Especially bad, the raising along with the kind collection density of integrated circuit also makes the line-spacing of metal interconnecting dwindle thereupon, thereby causes the coupling capacitance between the lead to raise.Therefore after the processing procedure of integrated circuit entered the deep-sub-micrometer field, resistance one capacitance hysteresis of metal interconnecting significantly improved, and also therefore influenced the arithmetic speed and the access rate of integrated circuit.In order to improve the productive set density of integrated circuit, under the condition that live width and line-spacing all should not improve, the material of changing metal interconnecting and interlayer dielectric layer is best selection.
Aspect metal interconnecting, metal material changes the copper metal into by original aluminium silicon copper alloy or aluminium copper, except having low-resistance characteristic, have more good anti-electron transfer and good anti-stress, except the operation rate that can improve element, reliability that simultaneously can lift elements; On the other hand, interlayer dielectric layer then must select the material of low-k (DielectricConstant) to replace original silicon, to reduce the coupling capacitance between the metal interconnecting.The dielectric constant of silicon is about 3.9, therefore must choose dielectric constant less than 3.9 dielectric medium as interlayer dielectric layer, can reach the effect that reduces the resistance-capacitance sluggishness, for example: the low-k dielectric medium of silicon (SiOF), organic spin-coating glass (HSQ), black diamond (black diamond) or Silk that fluorine mixes or the like.
In the technology of copper wiring, because of the copper metal can't carry out etching with chlorine as aluminium alloy, so industry develops the manufacturing method thereof that a kind of inlaying (damascene).The process technique of inlaying can be with reference to the Boeck of motorola inc; People such as Bruce Allen are at No. the 5880018th, United States Patent (USP) disclosed " Method for manufacturing a low dielectric constantinter-level integrated circuit structure ".At first please refer to Figure 1A, finished one and to have formed time top layer metallic layer 11 on the semiconductor substrate 10 of FEOL, form first dielectric layer with low dielectric constant 12 and second dielectric layer with low dielectric constant 13 more successively, after carrying out the planarization processing procedure, utilize little shadow and etching technique to form the opening of dual damascene (dual damascene).Next utilize and electroplate or chemical vapor deposition technology formation interlayer hole connector (via plug) 14 and top layer metallic layer 15.Follow-up formation protective layer 16, and utilize little shadow and etching technique to form the window 17 of metal pad.
Next please refer to Figure 1B, utilize sputtering method or chemical vapour deposition technique to form barrier layer (barrie layer) 18 and aluminium/copper metal layer 19 successively, utilize little shadow and etching technique that described barrier layer 18 and aluminium/copper metal layer 19 are carried out etching at last, to form metal pad (bonding pad) 20.Shown in Fig. 1 C, described metal pad 20 is to be formed directly on the described metal pad window 17.
Next please refer to Fig. 2, it is the vertical view of the metal pad on integrated circuit in the prior art.As shown in Figure 2, integrated circuit all includes main element district 30 and periphery circuit region 40, and utilizes the contact point of a plurality of metal pads 20 as when encapsulation plain conductor.
Next please refer to Fig. 3, it carries out the schematic diagram of gold thread connection process when encapsulating for integrated circuit in the prior art.After integrated circuit forms described metal pad 20, can cut and carry out encapsulation procedure.In the gold thread connection process of encapsulation procedure, gold thread 50 need be bonded on the described metal pad 20, to form the electrical couplings between integrated circuit and the base plate for packaging.
The denominator of dielectric layer with low dielectric constant is that the compactness of its physical structure is lower, thermodynamics conduction intensity is lower, and the degree of sticking together between itself and the lower metal layer is relatively poor.In the gold thread connection process that encapsulates, gold thread can impose great stress to metal pad, because of metal pad is should connect to be formed on the metal pad window, this stress down transmits, cause the be full of cracks of dielectric layer with low dielectric constant easily, and the peeling off of interface (the arrow place of Fig. 3) (peeling) between dielectric layer with low dielectric constant and the metal conducting layer, and cause declining to a great extent of process rate.
Therefore, in order to improve the yield of product, at copper wiring/dielectric layer with low dielectric constant processing procedure, develop a kind of metal pad with solve above-mentioned be full of cracks with peel off problem, just become very important problem of semiconductor industry.
Summary of the invention
Main purpose of the present invention is for providing a kind of metal pad of integrated circuit.
Secondary objective of the present invention is for providing a kind of metal pad that is applicable to copper wiring/dielectric layer with low dielectric constant processing procedure.
A further object of the present invention is for providing a kind of manufacture method that is applicable to the metal pad of copper wiring/dielectric layer with low dielectric constant processing procedure.
The present invention discloses a kind of metal pad of integrated circuit, and it is positioned on the metal pad window, and described metal pad window is to utilize little shadow and etching technique to form on a protective layer.Of the present invention focusing on, described metal pad more comprises an extension, and it extends on the described protective layer, engages in order to the gold thread with the gold thread connection process in the encapsulation procedure.Wherein said extension is to extend towards the direction in the main element district of described integrated circuit, or extends to the direction of adjacent metal weld pad.
The present invention more discloses a kind of method of making the metal pad of integrated circuit, has at first finished forming time top layer metallic layer on the semiconductor substrate of FEOL one.Next form first dielectric layer with low dielectric constant and second dielectric layer with low dielectric constant successively, and utilize little shadow and etching technique to form the opening of dual damascene (dual damascene).Utilize galvanoplastic or chemical vapor deposition method to form interlayer hole connector (via plug) and top layer metallic layer, follow-up formation protective layer, and utilize little shadow and etching technique to form the window of metal pad.Next form barrier layer (barrierlayer) and aluminium/copper metal layer successively, and utilize little shadow and etching technique that described barrier layer and aluminium/copper metal layer are carried out etching, to form metal pad.Of the present invention focusing on, the layout of employed light shield makes formed metal pad have more one section extension when changing the micro-photographing process that carries out metal pad, and the understructure of wherein said extension is a protective layer.
After forming described metal pad, more comprise an encapsulation procedure, comprise a gold thread connection process in the wherein said encapsulation procedure, be that gold thread is engaged to described extension.
Thus; effect of the present invention is: metal pad of the present invention has more an extension than prior art; make the gold thread connection process of encapsulation procedure beat on described extension; because of its understructure is to bear the protective layer of extremely strong stress (normally nitrogenize layer of sand or nitrogen silicon oxide layer), therefore can avoid the be full of cracks of prior art and the phenomenon of peeling off.And technology of the present invention only need be changed the light shield of metal pad window, and process conditions needn't be changed fully, can be compatible fully with the processing procedure on the present production line.
Description of drawings
Figure 1A forms protective layer in the prior art, utilize little shadow and etching technique to form the generalized section of the window of metal pad;
Figure 1B is the generalized section that forms barrier layer (barrier layer) and aluminium/copper metal layer in the prior art;
Fig. 1 C utilizes little shadow and etching technique to form the generalized section of metal pad in the prior art;
Fig. 2 is the vertical view of the metal pad on integrated circuit in the prior art;
Fig. 3 is the schematic diagram that carries out the gold thread connection process when integrated circuit encapsulates in the prior art;
Fig. 4 is the schematic cross section of the metal pad of integrated circuit of the present invention;
Fig. 5 A is the vertical view of the metal pad of integrated circuit in the first embodiment of the invention;
Fig. 5 B is the vertical view of the metal pad of integrated circuit in the second embodiment of the invention.
The figure number explanation:
The 10-semiconductor substrate;
11-top layer metallic layer;
12-first dielectric layer with low dielectric constant;
13-second dielectric layer with low dielectric constant;
14-interlayer hole connector;
The 15-top layer metallic layer;
The 16-protective layer;
The window of 17-metal pad;
The 18-barrier layer;
19-aluminium/copper metal layer;
The 20-metal pad;
The extension of 20A-metal pad;
30-main element district;
The 40-periphery circuit region;
The 50-gold thread.
Embodiment
The present invention is the metal pad that discloses a kind of integrated circuit, particularly about a kind of metal pad that is applicable to copper wiring/dielectric layer with low dielectric constant processing procedure and forming method thereof.The present invention is applicable to the integration processing procedure of the copper conductor/dielectric layer with low dielectric constant of the logic element of various kenels and memory cell.
At first please refer to Fig. 4, it is the schematic cross section of the metal pad of integrated circuit of the present invention.Finished one and to have formed time top layer metallic layer 11 on the semiconductor substrate 10 of FEOL, form first dielectric layer with low dielectric constant 12 and second dielectric layer with low dielectric constant 13 successively, after carrying out the planarization processing procedure, utilize little shadow and etching technique to form the opening of dual damascene (dual damascene).Next utilize and electroplate or chemical vapor deposition technology formation interlayer hole connector (via plug) 14 and top layer metallic layer 15.Follow-up formation protective layer 16 utilizes little shadow and etching technique to form the window 17 of metal pad.Next utilize sputtering method or chemical vapour deposition technique to form barrier layer (barrier layer) 18 and aluminium/copper metal layer 19 successively, utilize little shadow and etching technique that described barrier layer 18 and aluminium/copper metal layer 19 are carried out etching at last, to form metal pad (bonding pad) 20.Different with prior art is that the layout of employed light shield made formed metal pad have more one section extension 20A than prior art when the present invention changed the micro-photographing process that carries out metal pad 20.The understructure of described extension 20A is protective layer 19 and barrier layer 18; wherein said protective layer 19 is generally silicon nitride layer or nitrogen silicon oxide layer; its rerum natura structure is come fine and closely far beyond dielectric layer with low dielectric constant, and mechanical strength yet comes by force than dielectric layer with low dielectric constant.
Next please refer to Fig. 5 A, it is the vertical view of the metal pad of integrated circuit in the first embodiment of the invention.Can get by Fig. 5 A, big (metal pad of prior art is represented by dotted lines) that the area of described metal pad comes than the area of the metal pad of prior art, its extension 20A is the direction extension to adjacent metal weld pad 20.In prior art, the area of metal pad is about 100 microns * 100 microns.In the present embodiment metal pad is extended 80 microns to 300 microns to the direction of adjacent metal weld pad, and be principle not touch the adjacent metal weld pad.
Next please refer to Fig. 5 B, it is the vertical view of the metal pad of integrated circuit in the second embodiment of the invention.Can learn by Fig. 5 B, big (metal pad of prior art is to be represented by dotted lines) that the area of described metal pad is next than the area of the metal pad of prior art, its extension 20A extends 80 microns to 300 emblem rice to the direction in main element district 30.In the present embodiment metal pad is extended to the direction in the main element district 30 of integrated circuit, its advantage is the scruple of avoiding overlapping with the adjacent metal weld pad.
Next please refer again to Fig. 4, the present invention is except described metal pad 20 extends an extension 20A, in the gold thread connection process of encapsulation procedure, must change the position that gold thread engages, make that gold thread 50 is to be bonded on the extension 20A of described metal pad 20, as described in Figure 4.Because of the sectional area of described gold thread 50 between 70 microns to 80 microns, it is little that the length of more described extension is come, and therefore gold thread 50 can be beaten fully on described extension 20A in the gold thread connection process.As previously mentioned, no matter be the first embodiment of the present invention or second embodiment, the understructure of described extension 20A is protective layer 19 and barrier layer 18, can bear extremely strong mechanical stress.Therefore the be full of cracks that is taken place in the routing processing procedure of encapsulation procedure, just can not causing as prior art and peel off phenomenon.Therefore the problem that causes yield to decline to a great extent in the prior art also achieves a solution.
Disclosed metal pad that is applicable to copper wiring/dielectric layer with low dielectric constant processing procedure of the present invention and preparation method thereof has following advantage:
One, metal pad of the present invention has more an extension than prior art; make the gold thread connection process of encapsulation procedure beat on described extension; because of its understructure is to bear the protective layer of extremely strong stress (normally nitrogenize layer of sand or nitrogen silicon oxide layer), therefore can avoid the be full of cracks of prior art and the phenomenon of peeling off.
Two, technology of the present invention only need be changed the light shield of metal pad window, and process conditions needn't be changed fully, can be compatible fully with the processing procedure on the present production line.
The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the described claim scope.
Claims (10)
1. the metal pad of an integrated circuit, it is positioned on the metal pad window, and described metal pad window is to utilize little shadow and etching technique to form on a protective layer; It is characterized in that: described metal pad more comprises an extension, and it extends on the described protective layer, engages in order to the gold thread with the gold thread connection process in the encapsulation procedure.
2. the metal pad of integrated circuit according to claim 1 is characterized in that: described extension is to extend towards the direction in the main element district of described integrated circuit.
3. the metal pad of integrated circuit according to claim 2, it is characterized in that: the length of described extension is between 80 microns to 300 microns.
4. the metal pad of integrated circuit according to claim 1 is characterized in that: described extension is to extend towards the direction of adjacent metal weld pad.
5. the metal pad of integrated circuit according to claim 4, it is characterized in that: the length of described extension is between 80 microns to 300 microns.
6. method of making the metal pad of integrated circuit, it comprises:
A. finished one and formed time top layer metallic layer on the semiconductor substrate of FEOL;
B. form first dielectric layer with low dielectric constant and second dielectric layer with low dielectric constant successively;
C. utilize little shadow and etching technique to form the opening of dual damascene (dual damascene);
D. form interlayer hole connector (via plug) and top layer metallic layer;
E. form protective layer, and utilize little shadow and etching technique to form the window of metal pad;
F. form metal level;
G. utilize little shadow and etching technique that described barrier layer and aluminium/copper metal layer are carried out etching, to form metal pad; It is characterized in that:
The layout of employed light shield makes formed metal pad have more one section extension when changing the micro-photographing process that carries out metal pad, and the understructure of wherein said extension is a protective layer.
7. the method for the metal pad of making integrated circuit according to claim 6, it is characterized in that: after forming described metal pad, more comprising an encapsulation procedure, comprise a gold thread connection process in the wherein said encapsulation procedure, is that gold thread is engaged to described extension.
8. the method for the metal pad of making integrated circuit according to claim 6 is characterized in that: described metal level is that barrier layer (barrier layer) adds aluminium/copper metal layer.
9. the method for the metal pad of making integrated circuit according to claim 6 is characterized in that: described extension is to extend towards the direction in the main element district of described integrated circuit.
10. the method for the metal pad of making integrated circuit according to claim 6 is characterized in that: described extension is to extend towards the direction of adjacent metal weld pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021085692A CN1265452C (en) | 2002-04-02 | 2002-04-02 | Metal welding pad of integrated circuit and method for making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021085692A CN1265452C (en) | 2002-04-02 | 2002-04-02 | Metal welding pad of integrated circuit and method for making the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1449033A true CN1449033A (en) | 2003-10-15 |
| CN1265452C CN1265452C (en) | 2006-07-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021085692A Expired - Lifetime CN1265452C (en) | 2002-04-02 | 2002-04-02 | Metal welding pad of integrated circuit and method for making the same |
Country Status (1)
| Country | Link |
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| CN (1) | CN1265452C (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100336211C (en) * | 2004-01-06 | 2007-09-05 | 华宇电脑股份有限公司 | Radiating assembly of integrated circuit for portable computer |
| CN100378981C (en) * | 2004-11-02 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Structure for integrated circuit wafer |
| CN100449743C (en) * | 2005-09-29 | 2009-01-07 | 南茂科技股份有限公司 | Chip structure and stacked chip packing structure |
| CN100517668C (en) * | 2004-11-02 | 2009-07-22 | 台湾积体电路制造股份有限公司 | Bond pad structure |
| CN103803483A (en) * | 2012-11-13 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Method for forming welding pad |
| CN111128770A (en) * | 2019-12-16 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for forming aluminum pad and device containing aluminum pad |
-
2002
- 2002-04-02 CN CNB021085692A patent/CN1265452C/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100336211C (en) * | 2004-01-06 | 2007-09-05 | 华宇电脑股份有限公司 | Radiating assembly of integrated circuit for portable computer |
| CN100378981C (en) * | 2004-11-02 | 2008-04-02 | 台湾积体电路制造股份有限公司 | Structure for integrated circuit wafer |
| CN100517668C (en) * | 2004-11-02 | 2009-07-22 | 台湾积体电路制造股份有限公司 | Bond pad structure |
| US7741714B2 (en) | 2004-11-02 | 2010-06-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bond pad structure with stress-buffering layer capping interconnection metal layer |
| CN100449743C (en) * | 2005-09-29 | 2009-01-07 | 南茂科技股份有限公司 | Chip structure and stacked chip packing structure |
| CN103803483A (en) * | 2012-11-13 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Method for forming welding pad |
| CN103803483B (en) * | 2012-11-13 | 2016-03-16 | 中芯国际集成电路制造(上海)有限公司 | Form the method for weld pad |
| CN111128770A (en) * | 2019-12-16 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Method for forming aluminum pad and device containing aluminum pad |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1265452C (en) | 2006-07-19 |
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Granted publication date: 20060719 |