CN1448865A - Method for implementing digit filter group structure - Google Patents

Abstract

The digital filter combination structure includes input signal selecting unit, filter combination unit and frequency band selecting unit; and has combined discrete sampling multiple rate system and distributive mathematical algorithm. The discrete sampling multiple rate system operates on discrete sampling principle and has dendritic structure, time division multiplexing and circulative feedback to reduce hardware size of the digital filter combination structure. The digital filter combination with distributive mathematical algorithm, table look-up technique and hardware with memory is used in processing language, music tone, image, etc.

Description

The implementation method of digital wave filter set structure

The application be that May 15, application number in 1996 are 96107412.4 the applying date, denomination of invention divides an application for the application for a patent for invention of " digital wave filter set structure and implementation method thereof ".

Technical field

The invention relates to a kind of implementation method of digital wave filter set structure, particularly the two combines about a kind of at interval sampling multiple rate system (Decimation in Multi-Rate System) and distributed arithmetic algorithm (Distributed Arithmatic Algorithm), realizes reducing the implementation method of the digital wave filter set structure of dimensioned area.

Background technology

General voice (speech), musical sound (audio) and image (video) are handled through regular meeting and are used bank of filters (filter bank), so that an extraneous input signal is divided into the signal cohort of several narrow-bands.The signal cohort of these narrow-bands is according to different application, as the compression of musical sound, synthetic or speech recognition etc., and has various algorithm (Algorithm) corresponding.The generation of these narrow-band signal cohorts, need finish by the wave filter of corresponding number, therefore the signal number of narrow-band the more, these with hard-wired number of filter also the more, so also be linear increase according to the required dimensioned area that takies of this existing structure, perhaps have only the expensive DSP chip of use (DSPChip) to realize them with firmware (firmware) with the signal number of narrow-band.

In addition, the hardware of generally existing digital filter is realized forming nothing more than multiplier, totalizer and three kinds of elements combination of register, wherein the hardware configuration of multiplier many than totalizer and register complexity then.

Existing bank of filters (filter bank) hardware configuration, as shown in Figure 1, not overlapping or a small amount of overlapping wave filter such as N combine by several frequency bands, N is a natural number, its median filter can be analog filter or digital filter, it is divided into N (narrow) band signal output in order to band signal, so after accepting this input signal, will produce output signal 1～output signal N with an input.Digital filter then has finite impulse response (FIR) (FIR) by different specification requirements, as Fig. 2; And two kinds of forms of infinite impulse response (IIR), infinite impulse response then has direct type I (Direct form I) again, as Fig. 3, and direct type II (Direct form II), as different network structures such as Fig. 4, its theory is all records to some extent on general textbook, cooperate above-mentioned diagram to describe with a cutline here.

Shown in Fig. 2,3,4, h ₀～h _M, a ₁～a _N-1, c ₀～c _N-1Be the digital filter bank coefficient, be used for signal multiplication on the corresponding node with, be added on the next node Z again ^-1Then be delay function, in order to postpone signal on the last node to next node.With Fig. 3 is example, suppose that the current time is n, each chronomere of postponing forward is 1～(N-1) simultaneously, and each chronomere has the signal of a correspondence, be current extraneous input signal X (n), current limit (pole) input signal W (n), reach current output signal Y (n), its relational expression is

W(n)＝b ₀*X(n)+b ₁*X(n-1)+b ₂*X(n-2)+…+b _N-1*X(n-(N-1))

Y(n)＝W(n)+a ₁*Y(n-1)+a ₂*Y(n-2)+…+a _N-1*Y(n-(N-1))

And be example with Fig. 4, W (n) also is current limit input signal, and Y (n) is current output signal, and its relational expression then is

W(n)＝X(n)+a ₁*W(n-1)+a ₂*W(n-2)+…+a _N-1*W(n-(N-1))

Y(n)＝c ₀*W(n)+c ₁*W(n-1)+c ₂*W(n-2)+…+c _N-1*W(n-(N-1))

Wherein, know by the above-mentioned relation formula, if realize the expansion of its product term and addition merely with hardware, this structure certainly will need many multipliers, totalizer and shift register, and its quantity will linearity increase with the increase of digital filter exponent number (order), when these digital filter bank are synthesized digital filter bank (digital filter bank) and are applied in voice, in the time of in the processing of musical sound and image, in case the interior number of filter of bank of filters (filterbank) requires to increase, the spectrum number of promptly cutting apart requires to increase, then will produce the many multipliers of numbers of poles, totalizer and shift register, so huge hardware is with the viewpoint of integrated circuit, and is quite uneconomical.

Summary of the invention

In view of this, the objective of the invention is to, the two combines and realizes reducing the digital filter bank hardware configuration and the circuit thereof of dimensioned area by at interval sampling multiple rate system (Decimation in Multi-Rate System) and distributed arithmetic algorithm (Distributed ArithmaticAlgorithm).

The interval sampling multiple rate system that the present invention adopts has multiple stage condition, every stage condition operates in different speed, and several wave filters of repeated use minority, one extraneous input signal filtering can be gone out a plurality of signals in different frequency bands cohorts, and deal with different algorithms according to the different application field.

The present invention utilizes the distributed arithmetic algorithm to handle the computing of product term and (sum of product), can be applicable on the digital filter.

Interval of the present invention sampling multiple rate system is to adopt sampling (Decimation) principle at interval, and finishes the hardware realization of digital wave filter set structure with tree structure, time multiplexing, circulation feedback (recursive feed-back).

Interval of the present invention sampling (Decimation) principle be with the input signal after the sampling behind the set of number filter filtering, select the special frequency band signal, output as low-pass signal, and a bit every M sampling spot taking-up, the transfer rate that makes signal is through reducing to original 1/M after the sampling at interval, is referred to as M point-score take a sample at interval (M-fold Decimation).

In the present invention, in the tree structure of Q digital filter bank, definable is gone out Q stage condition, Q is a natural number, and according to M point-score sampling theorem at interval, previous stage state the ensemble operation rate be the latter half state the ensemble operation rate M doubly.

In the present invention, plan the sequential of each stage condition in the tree structure of digital filter bank in the time multiplexing mode.

The hardware of digital wave filter set structure of the present invention realizes, can cooperate the mode of circulation feedback and reuses a few digital filter.

Digital wave filter set structure of the present invention is made up of three unit, comprises the input signal selected cell, frequency band selected cell, and bank of filters unit.

The bank of filters unit of digital wave filter set structure of the present invention comprises high pass, a low pass and N bandpass filter, and it is finished hardware with the distributed arithmetic algorithm and realizes that N is a positive integer.

In the present invention, utilize the digital filter bank unit of distributed arithmetic algorithm, the circuit of its each wave filter has eight unit, it is first selector, second selector, limit processing unit, the parallel serial transfer unit that changes, shift register, first memory, second memory reaches the processing unit at zero point.

The distributed arithmetic algorithm that digital filter of the present invention is used is to utilize look-up table to cooperate storer to carry out hard-wired.

For realizing above-mentioned purpose of the present invention and characteristics, the invention provides a kind of implementation method of digital wave filter set structure, comprise the following steps: that a. uses sampling multiple rate system at interval, makes this digital filter bank have multiple stage condition; B. plan the sequential of described each stage condition according to the time multiplexing mode, make each stage condition operate in different rates; C. by this digital filter bank one extraneous input signal is carried out filtering, produce a plurality of non-overlappings or a small amount of overlapping band signal group; Reach the part that d. selects above-mentioned band signal group, this digital filter bank of circulation feedback is to produce the band signal group of the multiple stage condition of tool.

Adopt above-mentioned digital wave filter set structure of the present invention and implementation method thereof, can reduce number of filter in the required bank of filters, thereby realize reducing the digital wave filter set structure of dimensioned area, more economical.

Description of drawings

Fig. 1 shows existing bank of filters (filer bank) hardware configuration block scheme;

Fig. 2 illustrates the block scheme of a finite impulse response (FIR) (FIR) digital filter;

Fig. 3 illustrates the directly block scheme of the digital filter of type I (Direct form I) of another infinite impulse response (IIR);

Fig. 4 illustrates the directly block scheme of the digital filter of type II (Direct form II) of another infinite impulse response (IIR);

Fig. 5 illustrates the tree structure of the digital filter bank of sampling theorem at interval that adopts of the present invention;

Fig. 6 illustrates the sequential of planning each stage condition among the present invention according to the time multiplexing mode;

Fig. 7 shows the hardware embodiment that the present invention has the digital wave filter set structure 10 of circulation feedback;

Fig. 8 illustrates the circuit that adopts the digital filter bank unit of distributed arithmetic algorithm among the present invention;

Fig. 9 a, 9b show the circuit of the input signal selected cell among the present invention;

Figure 10 shows the circuit of frequency band selected cell circuit of the present invention;

Figure 11,12 shows the circuit and the sequential chart thereof of the selector switch among the present invention respectively;

Figure 13,14 shows the circuit and the sequential chart thereof of selector switch of the present invention respectively;

Figure 15,16 shows limit processing unit circuit of the present invention and sequential chart thereof respectively;

Figure 17,18 shows parallel commentaries on classics serial transfer element circuit of the present invention and sequential chart thereof respectively;

Figure 19,20 shows shift-register circuit of the present invention and sequential chart thereof respectively; And

Figure 21,22 shows processing unit circuit and sequential chart thereof at zero point of the present invention;

For making above-mentioned purpose of the present invention and advantage more clear, the preferred embodiments of the present invention are described in detail below in conjunction with accompanying drawing.

Embodiment

At first, digital wave filter set structure and implementation method thereof according to the preferred embodiments of the present invention are described successively referring to Fig. 5 to Figure 10.

Principle of work of the present invention is that the two combination of sampling multiple rate system (Decimation inMulti-Rate System) and distributed arithmetic algorithm (Distributed Arithmatic Algorithm) realizes reducing the digital filter bank hardware configuration and the circuit thereof of dimensioned area at interval.The sampling multiple rate system has multiple stage condition at interval, each stage condition operates in different speed, and reuse a few wave filter, it can leach a plurality of signals in different frequency bands cohorts with an extraneous input signal, and adopts different algorithms to deal with according to the different application field.And the distributed arithmetic algorithm is used for handling the computing of product term and (sum of product), can be applicable on the digital filter.

Wherein the sampling multiple rate system adopts sampling (Decimation) principle at interval at interval, and the hardware that adopts tree structure, time multiplexing, circulation feedback (recursive feedback) to finish digital wave filter set structure is realized.Adopt tree structure one Fig. 5 of the digital filter bank of sampling theorem at interval:

Referring to Fig. 5, at interval sampling (Decimation) principle be with the input signal after the sampling behind the set of number filter filtering, get the output of special frequency band signal such as low-pass signal, and a bit every M sampling spot taking-up, the transfer rate that makes signal is through reducing to original 1/M after the sampling at interval, is referred to as M point-score take a sample at interval (M-fold Decimation).

With five digital filter bank bank0～bank4 is example, when extraneous input signal passes through first digit bank of filters bank0, can be by a Hi-pass filter HPF, a low-pass filter LPF and N bandpass filter BPF1～BPF-N, come filtering to go out N+2 non-overlapping or a small amount of overlapping ensemble, state at this moment is defined as the phase one state.The ensemble that filtering goes out be defined as respectively phase one high communication number, phase one low-pass signal, phase one bandpass signal 1 ..., and phase one bandpass signal N, wherein the phase one high communication number is exported by Hi-pass filter HPF, the phase one low-pass signal is by low-pass filter LPF output, phase one bandpass signal 1 by bandpass filter BPF-1 output ..., and phase one bandpass signal N is exported by bandpass filter BPF-N.

Select the phase one low-pass signal to make the M point-score this moment and take a sample at interval, the signal after again this M point-score being taken a sample at interval exports the second digit bank of filters bank1 of next stage to, to leach N+2 ensemble.Will this moment state be defined as the subordinate phase state, the signal that leaches then be defined as subordinate phase high communication number, subordinate phase low-pass signal, subordinate phase bandpass signal 1 ..., and subordinate phase bandpass signal N.Similarly, the subordinate phase high communication number is by Hi-pass filter HPF output, and the subordinate phase low-pass signal is by low-pass filter LPF output, and subordinate phase bandpass signal 1 is exported by bandpass filter BPF-1,, and subordinate phase bandpass signal N is exported by bandpass filter BPF-N.

The phase III state that so repeats work to go down and third digit bank of filters bank2 is arranged, comprise phase III signal high communication number, phase III low-pass signal, phase III bandpass signal 1 ..., and phase III bandpass signal N, five-stage state until the 5th digital filter bank bank4, comprise five-stage signal high communication number, five-stage low-pass signal, five-stage bandpass signal 1 ..., and five-stage bandpass signal N etc.

And from the above, in the tree structure of Q digital filter bank, definable is gone out Q stage condition, and according to M point-score sampling theorem at interval, the ensemble operation rate of phase one state be the subordinate phase state the ensemble operation rate M doubly; The ensemble operation rate of subordinate phase state be the phase III state the ensemble operation rate M doubly; The rest may be inferred, the ensemble operation rate of Q-2 stage condition be the Q-1 stage condition the ensemble operation rate M doubly.Plan sequential-Fig. 6 of each stage condition according to the time multiplexing mode:

Referring to Fig. 6, it is the sequential with each stage condition in the tree structure of the digital filter bank of time multiplexing mode planning chart 5.As shown in Figure 6, cooperate Fig. 5, be planned to example with take a sample the at interval sequential of (2-fold Decimation) of five-stage state, 2 point-scores, wherein the time may be partitioned into a plurality of time slots (time slot), as time slot 0, time slot 1, and time slot 23 or the like, this tree structure adopts the stage condition control signal row L[l of Fig. 6]～L[5], and according to the size (logical zero or 1 pulse) of this control signal, judge which stage condition each time slot belongs to, to carry out the action of this stage condition in view of the above.

These stage condition control signals L[1 wherein]～L[5] non-overlapping, L[q] when being logical one, represent the tree structure of digital filter bank to be in the q stage condition, q=1 ..., 5, the L[1 during time slot 0 for example]=1, time slot 0 belongs to the phase one state as can be known; L[2 during time slot 1]=1, time slot belongs to the subordinate phase state as can be known; L[1 during time slot 2]=1, time slot 2 belongs to the phase one state as can be known; The rest may be inferred, the L[5 during time slot 15]=1, time slot 15 belongs to the five-stage state as can be known.

From the above, according to the planning of time multiplexing mode, at time slot 0,2,4 ... 22 o'clock is the phase one state, time slot 1,5,9 ... 21 o'clock is the subordinate phase state, time slot 3,11,19 o'clock is the phase III state, time slot 7,23 o'clock is quadravalence section state, then is the five-stage state during time slot 15.Hardware embodiment-Fig. 7 with digital wave filter set structure 10 of circulation feedback:

Referring to Fig. 7, digital wave filter set structure 10 comprises an input signal selected cell 20, one frequency band selected cell 40, an and bank of filters unit 30, the function of this bank of filters unit 30, be five digital filter bank bank0～bank4 that are equivalent in the tree structure of Fig. 5 digital filter bank, and the stage condition control signal row L[1 of Fig. 6]～L[5] size, can be used to then judge which stage condition the bank of filters unit 30 under each time slot belongs to.Here be described below respectively: a. input signal selected cell 20

Input signal selected cell 20 is selected extraneous input signal 21, phase one low-pass signal 331, subordinate phase low-pass signal 332 ... and five-stage low-pass signal 335 in one of signal enter bank of filters unit 30.Wherein above-mentioned extraneous input signal 21 can be the digital signal after sampling of an extraneous simulating signal, and the stage low-pass signal 331～335 through selecting, then by exporting bank of filters unit 30 again to after this selected cell 20 execution intervals sampling.B. the bank of filters unit 30

A plurality of digital filters are arranged in the bank of filters unit 30, as a Hi-pass filter (HPF) 31, a low-pass filter (LPF) 35 and N bandpass filter (BPF) 33, can be denoted as BPF-1～BPF-N respectively, N is a natural number, and wherein bandpass filter is a selectable elements.

The output signal 23 of input signal selected cell 20 is delivered to the above-mentioned all digital filters in the described unit 30 simultaneously, and according to state control signal L[q] define the stage condition of this unit 30.

Carry out filtering by each digital filter this moment, and export frequency band selected cell 40 to or feed back to input signal selected cell 20, the wherein output 371～375 of high pass, bandpass filter 31,33,381～385 deliver to frequency band selected cell 40, the output of low-pass filter 35 (one of each stage low-pass signal 331～335) then circulation feedback to input signal selected cell 20.C. the frequency band selected cell 40.

Frequency band selected cell 40 is accepted from the high pass of bank of filters unit 30, the output signal 371～375 of bandpass filter 31,33,381～385, as the high communication number and the bandpass signal (1-N) of each stage condition, comprise the low-pass signal of final stage, and determine that a band signal is as output 41.

As take a sample at interval with 2 point-scores (2-fold Decimation) is example, input signal selected cell 20 is selected extraneous input signal 21 and is obtained output signal 23, through the low-pass filter 35 of phase one bank of filters unit (bank0) and output phase one low-pass signal 331, this phase one low-pass signal 331, then relend and help input signal selected cell 20 and get per 2 signals, feeding back 1 signal feeding justice is the bank of filters unit (bank1) of subordinate phase state.In like manner, subordinate phase low-pass signal 332 get per 2 signals again by input signal selected cell 20, feeding back 1 signal feeding justice is the bank of filters unit (bank3) of phase III state, the rest may be inferred.In addition from the above, the ensemble operation rate of phase one state is 2 times of ensemble operation rate of subordinate phase state; The ensemble operation rate of subordinate phase state is 2 times of ensemble operation rate of phase III state.

The frequency band selected cell 40 in addition, according to one of above-mentioned extraneous input signal or each stage low-pass signal 331～335, and by input signal selected cell 20 and circulation feedback result to bank of filters unit 30, and acceptance is from the high pass of bank of filters unit 30, bandpass filter 31,33 output signal 371～375,381～385, high communication number and bandpass signal (1～N) as each stage condition, the low-pass signal (as five-stage) that comprises final stage, and determine that a band signal is as output 41, wherein, stage condition control signal row L[1]～L[5] size, can be used to judge that the bank of filters unit 30 under each time slot belongs to that stage state.Cooperate Fig. 5-Fig. 7, the signal flow of digital wave filter set structure 10 is as follows:

At first will be divided into a plurality of time slots (time slot) time, as time slot 0, time slot 1 ... time slot 23 or the like, and each time slot described.Time slot 0: be in the phase one state

According to the stage condition control signal of Fig. 6, the L[1 during by time slot 0]=1, time slot 0 belongs to the phase one state as can be known.Extraneous input signal 21 after input signal selected cell 20 is selected to take a sample is to bank of filters unit 30.

Bank of filters unit 30 output phase one high communication numbers 371, phase one bandpass signal (1～N) 381, and phase one low-pass signal 331.And the output signal of above-mentioned bank of filters unit 30 can be retained to next phase one state, and promptly time slot 2.Time slot 1: be in the subordinate phase state

According to the stage condition control signal of Fig. 6, by the L[2 of time slot 1]=1 as can be known time slot 1 belong to the subordinate phase state.Input signal selected cell 20 selects phase one low-pass signal 331 to bank of filters unit 30.

Bank of filters unit 30 output subordinate phase high communication numbers 372, subordinate phase bandpass signal (1～N) 382, and subordinate phase low-pass signal 332.And the output signal of above-mentioned bank of filters unit 30 can be retained to next subordinate phase state, as time slot 5.Time slot 2: be in the phase one state

According to the stage condition control signal of Fig. 6, the L[1 during by time slot 2]=1, time slot 2 belongs to the phase one state as can be known.Extraneous input signal 21 after 20 of input signal selected cells are selected to take a sample is to bank of filters unit 30.

Bank of filters unit 30 output phase one high communication numbers 371, phase one bandpass signal (1～N) 381, and phase one low-pass signal 331, and the output signal of above-mentioned bank of filters unit 30 can be retained to next phase one state, promptly time slot 4.

The rest may be inferred, and digital wave filter set structure 10 is the stage condition control signal L[1 according to Fig. 6]～L[5] logic, and define stage condition under each time slot, and the hardware of pressing Fig. 7 structure realizes carrying out the work of this stage condition.

Below respectively with regard to the included input signal selected cell 20 of digital wave filter set structure 10, frequency band selected cell 40, and bank of filters unit 30 are illustrated the preferred embodiments of the present invention.The circuit of input signal selected cell 20-Fig. 9 a, 9b

The input signal selected cell is an example with 5 stage condition, its circuit is shown in Fig. 9 a, 9b, constitute by a plurality of three-state buffers 90, wherein input end comprises: the extraneous input signal in sampling back is XIN[0:15], first, second, third and fourth stage low-pass signal then is respectively FB1[0:15], FB2[0:15], FB3[0:15], FB4[0:15], these input ends are then respectively corresponding to connect first to the 5th three-state buffer group TBUF1[0:15], TBUF2[0:15], TBUF3[0:15], TBUF4[0:15], TBUF5[0:15].Control signal LB[1 wherein]～LB[5], be respectively stage condition control signal L[1]～L[5] anti-phase, can be used to select one of above-mentioned input signal or each stage signal to make output signal OUT23[0:15].

And the extraneous input signal XIN[0:15 after sampling] with first, two, three, quadravalence section low-pass signal FB1[0:15], FB2[0:15], FB3[0:15], FB4[0:15] with 16 bit representations, so [0:15] represents 0 to 15, shown in Fig. 9 b, extraneous input signal XI N[0] to XIN[15] be respectively the input first three-state buffer TBUF1[0] to TBUF1[15], control signal LB[1] then connect the control end of these 15 impact dampers simultaneously, in like manner, each stage low-pass signal such as FB1[0] to FB1[15] and FB4[0] to FB4[15] etc. the also respectively corresponding three-state buffer TBUF1[0 that connects] to TBUF1[15] and TBUF5[0] to TBUF5[15] etc., control signal LB[2] to LB[5] then connect the control end of 15 impact dampers separately of this second to the 5th three-state buffer group TBUF2～TBUF5, output signal OUT23[0 respectively simultaneously] to OUT23[15] promptly select according to above-mentioned signal.

As LB[1]=0 and LB[2:5]=1 the time

OUT23[0：15]＝XIN[0：15]；

As LB[2]=0, LB[1]=1, LB[3:5]=1 the time

OUT23[0：15]＝FB1[0：15]；

In like manner as can be known, can be according to control signal LB[1]～LB[5] select each stage condition signal FB2[0:15]～FB4[0:15] one of output.

As take a sample at interval with 2 point-scores (2-fold Decimation) is example, the digital wave filter set structure 10 that cooperates Fig. 7 circulation feedback, input signal selected cell 20 is selected extraneous input signal XIN21[0:15] and obtain output signal OUT23[0:15], through the low-pass filter 35 of phase one bank of filters unit (bank0) and output phase one low-pass signal 331 (be FB1[0:15]), this phase one low-pass signal 331, then again according to the control signal LB[1 of input signal selected cell 20]～LB[5] (LB[2]=0) select to export OUT23[0:15], get per 2 signals simultaneously, feeding back 1 signal feeding justice is the bank of filters unit (bank1) of subordinate phase state.In like manner, subordinate phase low-pass signal 332 (be FB2[0:15]), control signal LB[1 according to input signal selected cell 20]～LB[5] (LB[3]=0) select output signal OUT23[0:15], get per 2 signals simultaneously, feeding back 1 signal feeding justice is the bank of filters unit (bank3) of phase III state, and the rest may be inferred.

For simplifying narration, circuit structure similar to the above is under the accessible principle of those skilled in the art, in the accompanying drawing of back, as Figure 10,11,13 in addition ... Deng omitting its detailed icon (as 9b), with convenient explanation.Circuit-Figure 10 of frequency band selected cell circuit 30

The frequency band selected cell is with 5 stage condition, and bank of filters unit 30 only comprises a Hi-pass filter, one low-pass filter is that (N bandpass filter BPF-1～BFP-N omits at this for the circuit of example, with convenient explanation), as shown in figure 10, constitute by a plurality of three-state buffers 100, wherein input end comprises: first, two, three, four, the band signal of five-stage high communication number etc. is respectively BAND1[0:15], BAND2[0:15], BAND3[0:15], BAND4[0:15], BAND5[0:15], band signal BAND6[0:15] then be last five-stage low-pass signal, these input ends then connect first to the 6th three-state buffer group TBUF1[0:15 respectively accordingly] to TBUF6[0:15].CHB[1 in addition]～CHB[6] be control signal, be used for selecting one of above-mentioned each stage signal to make output signal OUT41[0:15], as

As CHB[1]=0 and CHB[2:6]=1 the time

OUT41[0：15]＝BAND1[0：15]；

As CHB[2]=0, CHB[1]=1 and CHB[3:6]=1 the time

OUT41[0：15]＝BAND2[0：15]；

In like manner as can be known, can be according to control signal CHB[1]～CHB[6] select band signal BAND1[0:15]～BAND6[0:15] one of output.

The circuit of frequency band selected cell 20, can accept output signal 371～375 from the Hi-pass filter 31 of bank of filters unit 30, the high communication number BAND1[0:15 of respectively corresponding each stage condition of these signals], BAND2[0:15], BAND3[0:15], BAND4[0:15], BAND5[0:15], (the bandpass signal 1-N of N bandpass filter BPF-1～BPF-N omits at this), and determine that a band signal is as exporting OUT41[0:15].Adopt circuit-Fig. 8 of distributed arithmetic algorithm digital filter bank unit

Before the circuit of the digital filter bank unit 30 of narrating Fig. 8, the applied distributed arithmetic algorithm principle of explanation digital filter is as follows earlier at this:

The main difference of high pass (HPF), low pass (LPF) or logical (BFP) digital filter of band is at its coefficient, and product term and formula are suc as formula (A).{ Cj} is the set of number filter coefficient.J=0 wherein, 1,2 ..., N-1.Y (n) is a current output signal, and { W (n-j) } is limit input signal in the past, and when j was 0, { W (n) } represented a current limit input signal.Formula (A):

Y(n)＝c ₀*W(n)+c ₁*W(n-1)+c ₂*W(n-2)+…c _N-1*W(n-(N-1))

If above-mentioned input signal is shown formula (B) with complement code, a K bit table of 2: $W(n-j)={(b_{n-j}^{K-1}{b}_{n-j}^{K-2}...b_{n-j}^0)}_2,$ Wherein $\left\{b_{n-j}^p\right\}\∈\left\{\mathrm{0,1}\right\},p=\mathrm{0,1,2}...K-1;j=\mathrm{0,1},...,N-1;$

Be highest significant position MSB sign bit (sign bit); Be least significant bit (LSB) LSB.

And with { b _N-j ^pSequence represents metric W (n), W (n-j), the codomain of its { W (n-j) } between+1 and-1, promptly-1≤{ W (n-j) }＜1, j=0,1,2 ..., N-1, then W (n-j) is as shown in the formula (C) formula shown (C): $W(n-j)={((-1)b_{n-j}^{K-1}+2^{-1}{b}_{n-j}^{K-2}+...+2^{-(K-1)}{b}_{n-j}^0)}_{10}$ Convolution (A), formula (C) can become formula (D) formula (D) with product term and formula (A): $Y\left(n\right)=(-1){(c_0{b}_n^{K-1}+c_1{b}_{n-1}^{K-1}+c_2{b}_{n-2}^{K-1}+...)}_{10}+$ $\left(2^{-1}\right){(c_0{b}_n^{K-2}+c_1{b}_{n-1}^{K-2}+c_2{b}_{n-2}^{K-2}+...)}_{10}+$

：????????????????????：?????????????????： $\left(2^{-K+2}\right){(c_0{b}_n^1+c_1{b}_{n-1}^1+c_2{b}_{n-2}^1+...)}_{10}+$ $\left(2^{-K+1}\right){(c_0{b}_n^0+c_1{b}_{n-1}^0+c_2{b}_{n-2}^0+...)}_{10}$ Define the above-mentioned various formula (E) that is: the 0th rank item ${(c_0{b}_n^0+c_1{b}_{n-1}^0+c_2{b}_{n-2}^0+...)}_{10}$ Formula (F): the 1st rank item ${(c_0{b}_n^1+c_1{b}_{n-1}^1+c_2{b}_{n-2}^1+...)}_{10}$ Formula (G) in regular turn: K-2 rank item ${(c_0{b}_n^{K-2}+c_1{b}_{n-1}^{K-2}+c_2{b}_{n-2}^{K-2}+...)}_{10}$ Formula (H): K-1 rank item ${(c_0{b}_n^{K-1}+c_1{b}_{n-1}^{K-1}+c_2{b}_{n-2}^{K-1}+...)}_{10}$ The 0th rank item (formula (E)), be input signal LSB (the 0th, b _n ⁰) with the LSB of input signal in the past (the 0th, b _N-1 ⁰, b _N-2 ⁰) and coefficient { C _iCombine.In like manner, p rank item is the p position (b of input signal _n ^p) with the p position (b of input signal in the past _N-1 ^p, b _N-2 ^p), with coefficient { C _jForm and to form, p=0 wherein, 1 ..., so K-1 is total K position.

The running program of this digital filter application distribution arithmetic algorithm is as follows:

A. define an accumulation item, and be set at 0, input signal W (n) is K position of the input of serial in regular turn then, promptly the 0th, the 1st ..., the K-1 position;

When b. the input signal serial is imported the 0th, obtain the 0th rank item value, and be stored in the accumulation item, and the 0th rank item value is ${(c_0{\mathrm{<figure-callout\; id="0"\; label="b\; n"\; filenames="A0310901500291.png,A0310901500312.png"\; state="\{\{state\}\}">b</figure-callout>}}_n^{}+c_1{b}_{n-1}^0+c_2{b}_{n-2}^0+...)}_{10}.$

C. the accumulation item saves as the accumulation item divided by 2.

When d. the input signal serial is imported the 1st, obtain the 1st rank item value and be ${(c_0{\mathrm{<figure-callout\; id="1"\; label="b\; n"\; filenames="A0310901500222.png,A0310901500231.png"\; state="\{\{state\}\}">b</figure-callout>}}_n^{}+c_1{b}_{n-1}^1+c_2{b}_{n-2}^1+...)}_{10}.$

E. the 1st rank item value of steps d adds the accumulation item, saves as the accumulation item.

F. the accumulation item saves as the accumulation item divided by 2.

G. repeat above-mentioned steps, when the m position is imported in the input signal serial, obtain m rank item value, m=2 wherein ..., K-2, m rank item value is ${(c_0{b}_n^m+c_1{b}_{n-1}^m+c_2{b}_{n-2}^m+...)}_{10}.$

H. the m rank item value of step g adds the accumulation item, saves as the accumulation item.

I. the accumulation item saves as the accumulation item divided by 2.

When j. the K-1 position is imported in the input signal serial, obtain K-1 rank item value and be ${(c_0{b}_n^{K-1}+c_1{b}_{n-1}^{K-1}+c_2{b}_{n-2}^{K-1}+...)}_{10}.$

K. the K-1 rank item value of step j adds the accumulation item, saves as the accumulation item.

L. after last position (K-1 position) input, the value of accumulation item is Y (n).

So can finish product term and the calculating of a sample period by the distributed arithmetic algorithm structure.

The distributed arithmetic algorithm used of digital filter again, the hardware that can utilize look-up table to carry out p rank item value realize, p=0 wherein, and 1 ... K-1.According to formula (E)～formula (H), the codomain of each rank item is { C _jCombination, j=0,1,2 ..., N-1 is again because { b _N-j ^P{ 0,1} is so P rank item value has 2 to ∈ ^NIndividual codomain is with (b ^p _nb ^p _N-1b ^p _N-2) ₂Be the address, with 2 ^NThere is storer in individual value, as ROM, and PAL etc.With ROM is example, and its size is 2 ^NIndividual word (WORD), each word have K position.For example: during N=2, j is 0,1, and ROM address and codomain corresponding relation are as follows:

Address=(b n pb n-1 p)	???(0????0)	????(0????1)	????(1????0)	????(1???1)
					Codomain	???0	????C 1	????C 0	????C 0+C 1

According to above-mentioned, see also Fig. 8 and cooperate Fig. 7, in the bank of filters unit 30 of digital wave filter set structure 10, high pass HBF, a low pass LBF and N bandpass filter (BPF_1～BPF_N), can finish the hardware realization of circuit by the distributed arithmetic algorithm.

According to the direct type II of infinite impulse response (Direct form II) as Fig. 4 structure, utilize the circuit of the digital filter bank unit 30 of distributed arithmetic algorithm, have eight unit, it is selector switch 81, selector switch 82, limit processing unit 83, parallel serial transfer unit 84, shift register 85, the storer 91 of changeing, storer 92, zero point, processing unit 86, as shown in Figure 8, and wherein can be with look-up table, cooperating bit address that the bank of filters coefficient is stored in storer 91 and storer 92 in advance, then is formula (A) by the relational expression of Fig. 4:

Y (n)=c ₀* W (n)+c ₁* W (n-1)+c ₂* W (n-2)+... c _N-1* W (n-(N-1)) formula (B)

W(n)＝X(n)+a ₁*W(n-1)+a ₂*W(n-2)+…+a _N-1*W(n-(N-1))

The above-mentioned relation formula also can be reduced to $Y\left(n\right)=\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{c_j}^{*}W(n-j)$ $W\left(n\right)=X\left(n\right)+\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{a_j}^{*}W(n-j)$ Wherein according to the direct type II of infinite impulse response (Direct form II) as Fig. 4 structure, can be divided into the two large divisions, first forms relational expression (A), the shift register 85 of its corresponding diagram 8 is with the part on the right side, as processing unit 86 at zero point, bank of filters coefficient c ₁～c _N-1Combination then be stored in storer 92 in advance; And second portion forms relational expression (B), and the shift register 85 of its corresponding diagram 8 is with the part on a left side, as limit processing unit 83, and bank of filters coefficient a ₁～a _N-1Combination then be stored in storer 91 in advance.

And application distribution arithmetic algorithm and look-up table be at the circuit of digital filter bank unit 30, and its hardware configuration realizes as shown in Figure 8, and each unit institute detailed circuit and the sequential thereof of enforcement according to this shown in Figure 11-12, illustrate that here its sequence of operation is as follows:

A. with the preceding product term that once produces and $\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{a}_j*W(n-j)$ Be stored in the stage registers group 833 (Figure 15) in the limit processing unit 83.

B. control signal CTRL-1 selects input signal XIN (SEL1), by selector switch 81 to limit processing unit 83.

C. limit processing unit 83 with input signal XIN (SEL1) and product term and $\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{a}_j*W(n-j)$ Add up to limit signal POLE, and be stored in register 831 (Figure 15).

D. the register 831 of limit processing unit 83 is exported this limit signal POLE such as W (n) to selector switch 82 and the parallel serial transfer unit 84 that changes.

E. parallel commentaries on classics serial transfer unit 84 is with above-mentioned limit signal POLE such as W (n), be stored in the register 842 in this unit, and begin to highest significant position (Most Significant Bit) MSB by least significant bit (LSB) (Least Significant Bit) LSB, send sequence signal SERIAL to shift register 85 for one one in regular turn.

F. walking abreast changes the 0th of serial transfer unit 84 output W (n) to shift register 85, and shift register 85 is then exported the 0th bit address (b ⁰ _n, b ⁰ _N-1, b ⁰ _N-2) to storer 91, storer 92 gives addressing.

G. according to the 0th bit address (b ⁰ _n, b ⁰ _N-1, b ⁰ _N-2), storer 91 solves the 0th rank item value MEM1, and storer 92 solves its 0th rank item value MEM2.

H. the 0th rank item value MEM1 (SEL2) that solved of control signal CTRL-2 selection memory 91 to limit processing unit 83, and are stored in register 833 (Figure 15) in the limit processing unit 83 with the 0th rank item value MEM1 by this selector switch 82.

I. storer 92 solves its 0th rank item value MEM2, exports processing unit 86 at zero point to, and is stored in the register 213 (Figure 21) in the processing unit at zero point, and then is stored in the stage registers group 212 of processing unit at zero point by these register 213 outputs.

J. parallelly change limit signal value that 84 outputs of serial transfer unit are not updated such as W (n) the 1st to shift register 85, and by shift register 85 outputs the 1st bit address (b ¹ _n, b ¹ _N-2, b ¹ _N-2) to storer 91, storer 92.

K. according to the 1st bit address (b ¹ _n, b ¹ _N-1, b ¹ _N-2), storer 91 solves its 1st rank item value MEM1, and storer 92 solves its 1st rank item value MEM2.

L. the 1st rank item value MEM1 that solved of control signal CTRL-1 selection memory 91, (SEL1) delivers to limit processing unit 83 by selector switch 81.

M. the stage registers group 833 in the limit processing unit 83 is removed 2 backs with the 0th rank item value of above-mentioned steps h and is added up to limit signal POLE with the 1st rank item value MEM1, and is stored in the register 831 in the limit processing unit 83.

N. the limit signal POLE of the 831 output step m of the register in the limit processing unit 83 does not change serial transfer unit 84 to the input of selector switch 82 but do not export to walk abreast.Therefore originally being stored in parallel limit signal value such as the W (n) that changes serial transfer unit 84 can't be updated.

O. storer 92 solves its 1st rank item value MEM2, export processing unit 86 at zero point to, the 0th rank item value signal of stage working storage group 212 feedbacks of step I, at the register 213 that is stored in divided by 2 backs and the 1st rank item value MEM2 addition in the processing unit 86 at zero point, export by register 213 again and be stored in processing unit 86 stage registers group 212 at zero point.

P. continue to carry out to last position (MSB), the output of the stage registers group 212 in the zero point processing unit 86 is Y (n).

Q. wherein the product term in the limit processing unit 83 and $\underset{j=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{a}_j*W(n+1-j)$ Be stored in stage registers group 833, and zero point, processing unit 86 interior stage registers 212 were output as Y (n), at this moment repeating step a..

In the circuit of the digital filter bank unit 30 of above-mentioned employing distributed arithmetic algorithm, each unit detailed circuit and the sequential thereof implemented according to this, all illustrate at Figure 11-22, but do not use it and limit the present invention, and, be not described in detail at this because this technician who has been familiar with electronic applications understands.Here only with main signal of the present invention, content that device is relevant, be illustrated as follows.Circuit-Figure 11 of selector switch 81

Referring to Figure 11, this circuit is made up of a plurality of three-state buffers 110, wherein the sequential of control signal CTRL-1 then as shown in figure 12, be the one-period signal, the circuit of this selector switch 81, be to be used for selecting input signal XIN[0:15 according to the logic of control signal CTRL-1] or rank item value MEM1[0:15] as output SEL1[0:15], when aforementioned signal was the K position, time slot may be partitioned into K sub-slots (0～K-1).Circuit-Figure 13 of selector switch 82

Referring to Figure 13, this circuit is made up of a plurality of three-state buffers 130, wherein the sequential of control signal CTRL-2 as shown in figure 14, be the one-period signal, the circuit of this selector switch 82 is to be used for selecting limit signal POLE[0:15 according to the logic of control signal CTRL-2] be W (n) or rank item value MEM1[0:15] as output SEL2[0:15].When aforementioned signal was the K position, time slot may be partitioned into K sub-slots 0～K-1.Limit processing unit circuit 83-Figure 15

Referring to Figure 15, wherein, CK is the work clock of system, CL[1]～CL[5] be respectively phase one register controlled signal～five-stage register controlled signal, control signal LB[1]～LB[5] then be stage condition control signal L[1]～L[5] anti-phase, selector switch 82 is selected limit signal POLE and is exported (SEL2) according to control signal CTRL-2, and deliver to limit processing unit 83 and be stored in wherein stage registers group 833, this stage registers group 833 comprises phase one register to the five-stage register, whether select signal SEL3 then with deciding this signal SEL2 that inputs to limit processing unit circuit 83 will be divided by 2, work schedule as shown in figure 16.The parallel serial transfer element circuit 84-Figure 17 that changes

Referring to Figure 17, wherein CK is the work clock of system, signal HALF can make the limit signal POLE of input keep a time slots, and pass through register 842 and carry-out bit BIT[0:15], when being written into signal LOAD=0, can make a BIT[0:15] be loaded into sequence signal SERIAL, work schedule is then as shown in figure 18.Shift-register circuit 85-Figure 19

Referring to Figure 19, wherein, control signal LB[1]～LB[5] be respectively L[1]～L[5] anti-phase, SHIF[1]～SHIF[5] be respectively phase one register controlled signal～five-stage register controlled signal, this circuit is in order to receive the sequence signal SERIAL that changes 84 outputs of serial transfer unit from parallel, and work schedule then as shown in figure 20.Storer 91, storer 92

Storer 91 circuit, storer 92 circuit then can be finished by general ROM (read-only memory) (ROM), programmable logic array (PAL) commonly used, can cooperate bit address that the combination of bank of filters coefficient is stored in storer 91 and storer 92 in advance by look-up table.Zero point processing unit circuit-Figure 21

Referring to Figure 21, wherein, CK is the work clock of system.Control signal LB[1]～LB[5] be respectively L[1]～L[5] anti-phase, CL[1]～CL[5] be respectively phase one register controlled signal～five-stage register controlled signal, SEL3 decision input rank item value MEM2[0:15] signal be for 0 or should the stage register output back divided by 2 signal, work schedule is as shown in figure 22.

Though more than disclose a preferred embodiment of the present invention, yet the present invention is not limited thereto.Any those skilled in the art can carry out some changes or modification in not breaking away from spiritual scope of the present invention.Therefore protection scope of the present invention will be as the criterion with the confining spectrum of appended claim.

Claims (9)

1. the implementation method of a digital wave filter set structure comprises the following steps:

A. use sampling multiple rate system at interval, make this digital filter bank have multiple stage condition;

B. plan the sequential of described each stage condition according to the time multiplexing mode, make each stage condition operate in different rates;

C. by this digital filter bank one extraneous input signal is carried out filtering, produce a plurality of non-overlappings or a small amount of overlapping band signal group; And

D. select above-mentioned band signal group's a part, this digital filter bank of circulation feedback is to produce the band signal group of the multiple stage condition of tool.

2. the method for claim 1, wherein digital wave filter set structure comprises a plurality of digital filters, can cooperate look-up table finish hardware with the distributed arithmetic algorithm and realize.

3. the method for claim 1, wherein sampling is with this external world's input signal at interval, and resulting special frequency band signal after a digital filter bank filtering every M taking-up a bit, makes the signal transfer rate reduce to original 1/M, and M is a natural number.

4. method as claimed in claim 3, the multiple stage condition in this digital wave filter set structure wherein, according to M point-score sampling theorem at interval, previous stage state the ensemble operation rate be the latter half state the ensemble operation rate M doubly.

5. the method for claim 1, wherein at described step b, define a plurality of time slots, and, judge the stage condition under each time slot according to the logic that a plurality of stage condition control signals are listed as.

6. method as claimed in claim 5, wherein according to the direct type II of infinite impulse response, each time slot has the signal of a correspondence, promptly current extraneous input signal X (n), current limit input signal W (n), past limit input signal W (n-j), j=0,1,2 ..., N-1, and current output signal Y (n), and { a _j{ c _jBe the set of number filter coefficient, and wherein, N is a natural number, its relational expression can and be made up of following N item product term:

W(n)＝X(n)+a ₁*W(n-1)+a ₂*W(n-2)+…+a _N-1*W(n-(N-1))

Y(n)＝c ₀*W(n)+c ₁*W(n-1)+c ₂*W(n-2)+…+c _N-1*W(n-(N-1))

7. method as claimed in claim 6, wherein, digital filter bank comprises high pass, low pass or bandpass digital filter, finishes hardware with the distributed arithmetic algorithm and realizes that this distributed arithmetic algorithm defines a plurality of rank item value and is

A. formula (A) is current output signal

Y(n)＝c ₀*W(n)+c ₁*W(n-1)+c ₂*W(n-2)+…+c _N-1*w(n-(N-1))

B. above-mentioned input signal is shown formula (B) with complement code, a K bit table of 2, and its Chinese style (B) is $W(n-j)={(b_{n-j}^{K-1}{b}_{n-j}^{K-2}...b_{n-j}^0)}_2,$ Wherein $\left\{b_{n-j}^p\right\}\&Element;\left\{\mathrm{0,1}\right\},p=\mathrm{0,1,2}...K-1;j=\mathrm{0,1},...,N-1,$

Be highest significant position MSB and sign bit,

Be least significant bit (LSB) LSB;

C. and with

Sequence is represented metric W (n), W (n-j), the codomain of its { W (n-j) } between+1 and-1, promptly-1≤{ W (n-j) }＜1, j=0,1,2 ..., N-1, then W (n-j) is following formula (C) $W(n-j)={((-1)b_{n-j}^{K-1}+2^{-1}{b}_{n-j}^{K-2}+...+2^{-(K-1)}{b}_{n-j}^0)}_{10};$ And

D. in convolution (A), formula (C), product term and formula (A) can be become formula (D) $Y\left(n\right)=(-1){(c_0{b}_n^{K-1}+c_1{b}_{n-1}^{K-1}+c_2{b}_{n-2}^{K-1}+...)}_{10}+$ $\left(2^{-1}\right){(c_0{b}_n^{K-1}+c_1{b}_{n-1}^{K-2}+c_2{b}_{n-2}^{K-2}+...)}_{10}+$

：?????????????????：????????????????： $\left(2^{-K+2}\right){(c_0{b}_n^1+c_1{b}_{n-1}^1+c_2{b}_{n-1}^1+...)}_{10}+$ $\left(2^{-K+1}\right){(c_0{b}_n^0+c_1{b}_{n-1}^0+c_2{b}_{n-1}^0+...)}_{10}$ P=0 wherein, 1 ..., K-1, and can get the 0th rank item ${(c_0{b}_n^0+c_1{b}_{n-1}^0+c_2{b}_{n-2}^0+...)}_{10},$ The 1st rank item ${(c_0{b}_n^1+c_1{b}_{n-1}^1+c_2{b}_{n-2}^1+...)}_{10},$ K-2 rank item in regular turn ${(c_0{b}_n^{K-2}+c_1{b}_{n-1}^{K-2}+c_2{b}_{n-2}^{K-2}+...)}_{10},$ K-1 rank item ${(c_0{b}_n^{K-1}+c_1{b}_{n-1}^{K-1}+c_2{b}_{n-2}^{K-1}+...)}_{10}.$

8. method as claimed in claim 7, wherein, the running program of this digital filter application distribution arithmetic algorithm is:

A. define an accumulation item, and be set at 0, input signal is K position of the input of serial in regular turn then, promptly the 0th, the 1st ..., the K-1 position;

When b. the input signal serial is imported the 0th, obtain the 0th rank item value, and be stored in the accumulation item, and the 0th rank item value is ${(c_0{b}_n^0+c_1{b}_{n-1}^0+c_2{b}_{n-2}^0+...)}_{10};$

C. will accumulate divided by 2 and save as accumulation;

When d. the input signal serial is imported the 1st, obtain the 1st rank item value and be ${(c_0{b}_n^1+c_1{b}_{n-1}^1+c_2{b}_{n-2}^1+...)}_{10};$

E. the 1st rank item value with steps d adds the accumulation item, saves as the accumulation item;

F. will accumulate divided by 2 and save as accumulation;

G. repeat above-mentioned steps, when the m position is imported in the input signal serial, obtain m rank item value, m=2 wherein ..., K-2, m rank item value is ${(c_0{b}_n^m+c_1{b}_{n-1}^m+c_2{b}_{n-2}^m+...)}_{10};$

H. the m rank item value with step g adds the accumulation item, saves as the accumulation item;

I. will accumulate divided by 2 and save as accumulation;

J. when the K-1 position is imported in the input signal serial, obtain K-1 rank item value and be ${(c_0{b}_n^{K-1}+c_1{b}_{n-1}^{K-1}+c_2{b}_{n-2}^{K-1}+...)}_{10};$

K. the K-1 rank item value with step j adds the accumulation item, saves as the accumulation item; And

L. after last position (K-1 position) input, the value of accumulation item is Y (n), finishes product term and the calculating of a sample period.

9. method as claimed in claim 8, wherein, distributed arithmetic algorithm, the hardware that can utilize look-up table to carry out P rank item value realize that it codomain that comprises each rank item is { c _jCombination, j=0,1,2 ..., N-1, and $\left\{b_{n-j}^p\right\}\&Element;\left\{\mathrm{0,1}\right\},$ Make P rank item value have 2 ^NIndividual codomain, its with $(b_n^p{b}_{n-1}^p{b}_{n-2}^p\&CenterDot;\&CenterDot;\&CenterDot;{)}_{10}$ Be the address, with 2 ^NThere is a storer in individual value, and its size is 2 ^NIndividual word, each word have K position.

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