CN1447563A - Stack speed process method in Ethernet exchanger - Google Patents
Stack speed process method in Ethernet exchanger Download PDFInfo
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- CN1447563A CN1447563A CN 02107650 CN02107650A CN1447563A CN 1447563 A CN1447563 A CN 1447563A CN 02107650 CN02107650 CN 02107650 CN 02107650 A CN02107650 A CN 02107650A CN 1447563 A CN1447563 A CN 1447563A
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Abstract
In the stack chain constituted by exchange chips, the normal forwarding flow of the data frames received by exchange chips passing through is as follows. (A) Data frames are received. (B) The protocol process of the frame and looking up the forwarding target port of the frame. (C) Determining whether the target port is the local port. If yes, the frame is sent to the target port through the flow (D). The characters are that before the flow (B), the stack process branch is setup to determine whether the source port is the stack port. At least for the data frame, whose source port is the stack port, the determination of whether the current chip is the end of the stack chain is carried out. If the current chip is not at the end of the stack chain, the data is sent to next stack port quickly.
Description
[technical field]
The present invention relates to electrical communication technology, relate in particular to a kind of Ethernet switch stack speed process method.
[background technology]
Pile up the schematic diagram that link is realized multi-chip stacking as Fig. 1 to Fig. 3 for adopting, more than " reception/transmission " direction of the some Ethernet physical ports of " Rx/Tx " expression among each figure.Single worker's stack manner is meant that an exchange chip has only a port to be connected to and piles up link, the sending direction of this stack port is connected to the receive direction of next exchange chip stack port, link successively and form an annular, as shown in Figure 1, characteristics of this stack manner are not have edge device, and all exchange chips are all located on the identical relative position.
The duplex stack manner is that each chip has two ports to be connected to pile up link, and " reception/transmission " direction of a stack port of exchange chip is connected respectively to " reception/transmission " direction of adjacent exchange chip, as shown in Figure 2.Characteristics of duplex stack manner are to have the edge device pile up link, and the exchange chip that is connect as computer A among Fig. 2 and B is the edge device that this piles up link.
Redundant duplexing stack manner provides the path of a redundancy on the basis that duplex is piled up, shown in the dotted line among Fig. 3, when operate as normal, this link is inoperative, when break down and can not work in other path, can redundant path be started working by agreement, thereby guarantee whole operate as normal of piling up chipset.
As can be seen, which kind of stack manner no matter will be when port one mails to port x as Frame, must be through piling up link, the thick line part among promptly above Fig. 1, Fig. 2, Fig. 3 from top figure.
Ethernet switch is to utilize address search Table A RL to finish the forwarding of packet between port, the address search table is preserved is to be connected the media access control address MAC of the computer on each port of switch and corresponding port thereof number, the media access control address of every computer is that the whole world is unique, and the address search table is mainly set up by automatic learning process.
For example, in Fig. 1, computer A is connected the port one of exchange chip 1, if computer A sends packet to other computers, exchange chip 1 will be learnt the address of computer A and a list item is set in the address search table, and the address that indicates computer A is at port one.If other ports have the packet of the computer A of mailing to, search address table and just can know computer A, thereby packet is forwarded to the computer A of port one at port one.
If exchange chip 1 was never received the packet from computer B; so can be in the address search table relevant for the list item of computer B; if computer A sends packet to computer B; exchange chip 1 is searched address table and can be found to find output port; this moment, exchange chip 1 common meeting be broadcast to all of the port to this packet; comprise stack port, packet will progressively be delivered to computer B like this.For the packet that is broadcast to other computers, these computers can ownly check, when the destination address of finding packet when their is computer B rather than oneself, understand automatically with these data packet discardings.
It below also is the basic forwarding principle of Ethernet switch.
According to the basic principle of ether exchange as can be known, it is important that the rapid foundation of switch address look-up table causes the pass to the performance that exchanges, if learning process will cause each port a large amount of broadcasting packets to occur too slowly, not only occupy the effective bandwidth of port, Ethernet switch also possibly can't in time be finished transmission, causes congested.
Exchange chip piles up that being actually links together a plurality of exchange chips is used as equipment and uses, and in order to reduce broadcast traffic, improves forwarding performance of equipment, and the address search table of respective switch more should be consistent as far as possible.
Unified address look-up table has two kinds of methods usually:
1, send special address updating message between stack equipment, it is synchronous to be used for address table, this method
Need many software operations, design is complicated, and performance is poor.
2, on all pile up link frame must cover whole link so that other chip also can be learnt
To this address, even if the destination interface of this frame may be on this chip.This method is not with
Come any additional designs requirement, operating process is finished automatically by hardware, and performance is very good.
The forwarding process of each chip of employing said method 2 as shown in Figure 4, each equipment that piles up, for each Frame that receives, all at first carry out address learning, search the acquisition destination interface by address table then, next need to judge whether and to send to stack port to message, if from the Frame of stack port, in order to guarantee that Frame can cover whole links, must guarantee then that this packet can resend piles up link, as the indicated data path of the thick line among Fig. 4.The shortcoming of this technology is: the repeating process of each chip is a basic fixed, postpones also to fix, and enters the Frame that piles up link for each, need cover the whole link that piles up, and just covers the forwarding process of all chips.Like this, when the equipment that piles up was many, the whole link that piles up will produce very big forward delay, reduced the forwarding performance when piling up.
[summary of the invention]
The object of the present invention is to provide a kind of can the shortening to enter the forward delay of Frame in each stacked chips that piles up link, thereby accelerate to pile up the Ethernet switch stack speed process method that link is transmitted.
The method applied in the present invention is: this Ethernet switch stack speed process method, piling up in the link that exchange chip constitutes, the Frame that exchange chip receives the normal forwarding process of process as follows: a. receiving data frames; B. the destination interface forwarding lookup of the protocol processes of frame and frame; C. judge whether its destination interface is local port, if its destination interface is a local port, then be dealt into the destination interface of this frame through flow process d., it is characterized in that: before described flow process b, be provided with one and pile up whether the source port of handling branch's judgment data frame is stack port, at least be judged as the Frame of stack port for source port, whether carry out current chip again is the judgement of piling up the link end, if current chip is not to pile up the link end, then Frame is dealt into next stack port fast.
In piling up processing branch, carry out source port when whether being the judgement of stack port, be judged as the Frame that is not stack port for source port, be not local port, then Frame is dealt into next stack port fast if the destination interface of this Frame is judged as.
Described piling up handled in the branch, judge that current chip is whether for piling up link when terminal, in the Ethernet that duplex mode piles up, judge whether current chip is edge device, if not edge device, current chip is judged as and is not to pile up the link end, then Frame is dealt into next stack port fast; Pile up the link end if edge device, current chip are judged as, then abandon this Frame.
Frame can add self-defining label TAG piles up link with transmission control information in front; Among the described self-defining label TAG, when simplex mode is piled up, comprise link life span TTL territory, first serves the initial value that exchange chip that single worker piles up link is provided with link life span TTL with Frame, the initial value of link life span TTL is exactly that the number of stacked chips deducts 1, after Frame enters next exchange chip, in piling up processing branch, this exchange chip is just checked its link life span value, if the link life span value that is checked through is greater than 1, deducting 1 resulting value with this link life span ttl value that is checked through substitutes and to become current link life span ttl value, and current exchange chip is judged as and is not to pile up the link end, and Frame is dealt into next stack port fast; If the link life span ttl value that is checked through is less than or equal to 1, then current chip is judged as and piles up the link end, then abandons this Frame.
Beneficial effect of the present invention is: in the present invention, in a single day Frame has been gone up and has been piled up link and just must arrive all stacked chips through piling up link " broadcasting ", can guarantee the synchronous of each exchange chip address search table so as early as possible, in piling up processing branch, be judged as the Frame of stack port for source port, and current chip is not when piling up the link end, then Frame is dealt into next stack port fast, the Frame that these stack ports are come is skipped long protocol processes and destination interface forwarding lookup flow process consuming time, directly frame is dealt into stack port, significantly reduced the forward delay that piles up link, effect was especially obvious when multiple devices piled up, therefore, the present invention can shorten and enters the forward delay of Frame in each stacked chips that piles up link, transmits thereby accelerate to pile up link; In piling up processing branch, be judged as the Frame that is not stack port for source port, if being judged as, the destination interface of this Frame not local port, then Frame is dealt into next stack port fast, like this, if the position that exchange chip has an opportunity to learn a new computer then makes other exchange chips also can acquire, improved reliability of the present invention; Pile up link transmits in order to be more convenient for, add self-defining label TAG with transmitting control information in the front of normal data frames, this label only is stacked the Frame that transmits in the link and uses, participated in the exchange chip identification of piling up, Frame is the normal data frame format when mailing to other equipment by non-stack port, any customized label all is removed, and to guarantee and the favorable compatibility of other equipment, has improved practicality of the present invention; When simplex mode is piled up, customized label comprises link life span TTL territory, first serves the initial value that exchange chip that single worker piles up link is provided with link life span TTL with Frame, the initial value of link life span TTL is exactly that the number of stacked chips deducts 1, after Frame enters next exchange chip, in piling up processing branch, this exchange chip is just checked its link life span ttl value, if the link life span value that is checked through is greater than 1, deducting 1 resulting value with this link life span ttl value that is checked through substitutes and to become current link life span ttl value, and current exchange chip is judged as and is not to pile up the link end, and Frame is dealt into next stack port fast; If the link life span ttl value that is checked through is less than or equal to 1, then current chip is judged as and piles up the link end, then abandon this Frame, can guarantee like this if the position that exchange chip has an opportunity to learn a new computer, other exchange chips also can be acquired, simultaneously, guarantee that again this Frame does not repeat to send in piling up link; In the Ethernet that duplex mode piles up, in piling up processing branch, judge whether current chip is edge device, if not edge device, current chip is judged as and is not to pile up the link end, then Frame is dealt into next stack port fast, if edge device, current chip is judged as and piles up the link end, then abandon this Frame, so also make if the position that exchange chip has an opportunity to learn a new computer then makes other exchange chips also can acquire fast, simultaneously, guarantee that again this Frame is unlikely to repeat to send in piling up link, under duplex is piled up pattern, mainly by judging whether current chip is edge device decision whether continuation Data transmission frame, not effect of link life span TTL territory this moment, but can for the purpose of unification, still be retained in the TAG.Whether edge device is provided with in each exchange chip by register by software; Other territories in the label are used in transmitting control information between stacked chips, and this forwarding behavior to unified each chip is necessary; The present invention only needs the circuit of Ethernet switching chip is carried out very little change, and is with low cost, is suitable for chip and realizes.
In a word, the present invention can shorten and enters the forward delay of Frame in each stacked chips that piles up link, transmit thereby accelerate to pile up link, the present invention is practical, when an exchange chip has an opportunity to learn the position of a new computer, other exchange chips also can be acquired, simultaneously, guarantee that again this Frame is unlikely to repeat to send the reliability height in piling up link, with low cost, be suitable for chip and realize.
[description of drawings]
Fig. 1 is single worker's stack manner schematic diagram;
Fig. 2 is duplexing stack manner schematic diagram;
Fig. 3 is redundant duplexing stack manner schematic diagram;
The existing exchange chip of Fig. 4 is transmitted and the handling process schematic diagram;
Fig. 5 is that exchange chip of the present invention is transmitted and the handling process schematic diagram;
Fig. 6 piles up the link schematic diagram for concrete application example.
[embodiment]
With embodiment the present invention is described in further detail with reference to the accompanying drawings below:
Exchange chip of the present invention transmit and handling process as follows: as shown in Figure 5, piling up in the link that exchange chip constitutes, the Frame of exchange chip reception the normal forwarding process of process as follows: a. receiving data frames; B. the destination interface forwarding lookup of the protocol processes of frame and frame; C. judge whether its destination interface is local port, if its destination interface is a local port, then be dealt into the destination interface of this frame through flow process d., before flow process b, whether be provided with one and pile up whether the source port of handling branch's 2 judgment data frames is stack port, be judged as the Frame of stack port for source port, carrying out current chip again is the judgement of piling up the link end, if current chip is not to pile up the link end, then Frame is dealt into next stack port fast; In piling up processing branch 2, carry out source port when whether being the judgement of stack port, be judged as the Frame that is not stack port for source port, be not local port, then Frame is dealt into next stack port fast if the destination interface of this Frame is judged as.
In the Ethernet that duplex mode piles up, judge current chip whether for piling up link when terminal, judges whether current chip is edge device, if not edge device, current chip is judged as and is not to pile up the link end, then Frame is dealt into next stack port fast; Pile up the link end if edge device, current chip are judged as, then abandon this Frame.
In the Ethernet that simplex mode is piled up, can add self-defining label TAG in the front of normal data frames with transmitting control information, this customized label comprises link life span TTL territory, first serves the initial value that exchange chip that single worker piles up link is provided with link life span TTL with Frame, the initial value of link life span TTL is exactly that the number of stacked chips deducts 1, after Frame enters next exchange chip, in piling up processing branch 2, this exchange chip is just checked its link life span ttl value, if the link life span value that is checked through is greater than 1, deducting 1 resulting value with this link life span ttl value that is checked through substitutes and to become current link life span ttl value, and current exchange chip is judged as and is not to pile up the link end, and Frame is dealt into next stack port fast; If the link life span ttl value that is checked through is less than or equal to 1, then current chip is judged as and piles up the link end, then abandons this Frame.
Lift a concrete application example below flow process of the present invention is described, a single worker piles up link as shown in Figure 6, if there is Frame to be dealt into the port N of exchange chip C3 from the port M of exchange chip C1, suppose that now port N once sent data to port M, therefore exchange chip C1, C2 and C4 know port N destination interface in corresponding stack port by the address search table, and exchange chip C3 knows that port N is at local port:
1. after Frame enters exchange chip C1,, find order through the forwarding lookup of protocol processes destination interface
Port be stack port because source port M is not stack port, and destination interface is judged
For not being local port, then exchange chip C1 puts link life span TTL=3, and with data
Frame mails to stack port fast;
2. Frame enters exchange chip C2, because the source port of Frame is a stack port, is piling up the place
In the reason branch 2,, pile up and handle after branch 2 is kept to 2 with link life span TTL because of TTL＞1
At once Frame is sent from stack port, in normal forwarding process, the process long period
After protocol processes and the forwarding lookup, determine that just destination interface is not a local port, but because data
The frame source port is a stack port, so this Frame no longer repeats transmission, therefore, exchange chip C2
Learn the address of port M, transmission later on can be broadcasted;
3. before the forwarding of exchange chip C2 and handling process were not finished fully, Frame may arrive friendship
Change chip C3, owing to be the Frame from stack port, Frame is piling up the processing branch equally
Prop up in 2, the value of link life span TTL is reduced to 1, and Frame is sent from stack port, simultaneously,
In normal forwarding process, Frame is transmitted to port N.Equally, exchange chip C3 also acquires
The address of port M, transmission later on can be broadcasted;
4. exchange chip C3 is not delivered to message before the port N, and Frame may arrive the exchange core
Sheet C4, Frame is in piling up processing branch 2, because link life span TTL has equaled 1,
Pile up processing branch 2 and will not send Frame, in normal forwarding process, determine that destination interface is not
Be local port, but because the Frame source port is a stack port, so this Frame is no longer heavy
Recurrence is sent, and Frame is at the off-the-air that piles up on the link, and Frame sends and is all over, with
Sample, exchange chip C4 also acquires the address of port M, and transmission later on can be broadcasted.
Here, need to prove, is the normal data frame format when Frame mails to other equipment by non-stack port, with the favorable compatibility of assurance and other equipment.
Claims (7)
1 one kinds of Ethernet switch stack speed process methods, piling up in the link that exchange chip constitutes, the Frame that exchange chip receives the normal forwarding process of process as follows: a. receiving data frames; B. the destination interface forwarding lookup of the protocol processes of frame and frame; C. judge whether its destination interface is local port, if its destination interface is a local port, then be dealt into the destination interface of this frame through flow process d., it is characterized in that: before in described flow process (b), be provided with one and pile up whether the source port of handling branch (2) judgment data frame is stack port, at least be judged as the Frame of stack port for source port, whether carry out current chip again is the judgement of piling up the link end, if current chip is not to pile up the link end, then Frame is dealt into next stack port fast.
2. Ethernet switch stack speed process method according to claim 1, it is characterized in that: described piling up handled in the branch (2), carry out source port when whether being the judgement of stack port, be judged as the Frame that is not stack port for source port, not local port if the destination interface of this Frame is judged as, then Frame is dealt into next stack port fast.
3. Ethernet switch stack speed process method according to claim 1 and 2, it is characterized in that: described piling up handled in the branch (2), judge that current chip is whether for piling up link when terminal, in the Ethernet that duplex mode piles up, judge whether current chip is edge device, if not edge device, current chip is judged as and is not to pile up the link end, then Frame is dealt into next stack port fast; Pile up the link end if edge device, current chip are judged as, then abandon this Frame.
4. Ethernet switch stack speed process method according to claim 1 and 2 is characterized in that: Frame adds self-defining label (TAG) piles up link with transmission control information in front.
5. Ethernet switch stack speed process method according to claim 4, it is characterized in that: in the described self-defining label (TAG), when simplex mode is piled up, comprise link life span (TTL) territory, first serves the initial value that exchange chip that single worker piles up link is provided with link life span (TTL) with Frame, the initial value of link life span (TTL) is exactly that the number of stacked chips deducts 1, after Frame enters next exchange chip, in piling up processing branch (2), this exchange chip is just checked its link life span (TTL) value, if the link life span value that is checked through is greater than 1, deducting 1 resulting value with this link life span (TTL) value that is checked through substitutes and to become current link life span (TTL) value, and current exchange chip is judged as and is not to pile up the link end, and Frame is dealt into next stack port fast; If link life span (TTL) value that is checked through is less than or equal to 1, then current chip is judged as and piles up the link end, then abandons this Frame.
6. Ethernet switch stack speed process method according to claim 4, it is characterized in that: described self-defining label (TAG) only is stacked the Frame that transmits in the link and uses, participated in the exchange chip identification of piling up, Frame is the normal data frame format when mailing to other equipment by non-stack port.
7. Ethernet switch stack speed process method according to claim 5, it is characterized in that: described self-defining label (TAG) only is stacked the Frame that transmits in the link and uses, participated in the exchange chip identification of piling up, Frame is the normal data frame format when mailing to other equipment by non-stack port.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02107650 CN1210914C (en) | 2002-03-22 | 2002-03-22 | Stack speed process method in Ethernet exchanger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02107650 CN1210914C (en) | 2002-03-22 | 2002-03-22 | Stack speed process method in Ethernet exchanger |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1447563A true CN1447563A (en) | 2003-10-08 |
| CN1210914C CN1210914C (en) | 2005-07-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02107650 Expired - Fee Related CN1210914C (en) | 2002-03-22 | 2002-03-22 | Stack speed process method in Ethernet exchanger |
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| CN (1) | CN1210914C (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100349423C (en) * | 2005-12-31 | 2007-11-14 | 杭州华三通信技术有限公司 | Access method of document in pile system |
| CN100393070C (en) * | 2005-06-14 | 2008-06-04 | 杭州华三通信技术有限公司 | Method for message redirection in stacking equipment |
| CN1960324B (en) * | 2005-11-02 | 2010-07-21 | 盛科网络（苏州）有限公司 | Network switchboard using loop for completing tunnel packing and de-packing treatment and method thereof |
| CN101499976B (en) * | 2004-10-28 | 2011-04-06 | 阿尔卡特朗讯 | Stack manager protocol with automatic set up mechanism |
| CN101436901B (en) * | 2008-12-05 | 2011-06-22 | 中兴通讯股份有限公司 | Apparatus and method for managing OLT chip of EPON by Ethernet |
| CN107317762A (en) * | 2017-06-29 | 2017-11-03 | 北京东土军悦科技有限公司 | Jamming control method and field layer device based on industry internet field layer device |
| CN112019459A (en) * | 2020-09-09 | 2020-12-01 | 盛科网络（苏州）有限公司 | Message processing method and system based on dynamic online and offline of equipment in stacking system |
-
2002
- 2002-03-22 CN CN 02107650 patent/CN1210914C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101499976B (en) * | 2004-10-28 | 2011-04-06 | 阿尔卡特朗讯 | Stack manager protocol with automatic set up mechanism |
| CN100393070C (en) * | 2005-06-14 | 2008-06-04 | 杭州华三通信技术有限公司 | Method for message redirection in stacking equipment |
| CN1960324B (en) * | 2005-11-02 | 2010-07-21 | 盛科网络（苏州）有限公司 | Network switchboard using loop for completing tunnel packing and de-packing treatment and method thereof |
| CN100349423C (en) * | 2005-12-31 | 2007-11-14 | 杭州华三通信技术有限公司 | Access method of document in pile system |
| CN101436901B (en) * | 2008-12-05 | 2011-06-22 | 中兴通讯股份有限公司 | Apparatus and method for managing OLT chip of EPON by Ethernet |
| CN107317762A (en) * | 2017-06-29 | 2017-11-03 | 北京东土军悦科技有限公司 | Jamming control method and field layer device based on industry internet field layer device |
| CN112019459A (en) * | 2020-09-09 | 2020-12-01 | 盛科网络（苏州）有限公司 | Message processing method and system based on dynamic online and offline of equipment in stacking system |
| CN112019459B (en) * | 2020-09-09 | 2021-10-26 | 苏州盛科通信股份有限公司 | Message processing method and system based on dynamic online and offline of equipment in stacking system |
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| Publication number | Publication date |
|---|---|
| CN1210914C (en) | 2005-07-13 |
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