CN1447562A - Logic circuit of interface between bases and subordinates of VXI bus registers - Google Patents

Abstract

A logic circuit includes the address control signal receiver, the data transceiver, the common bus receiver, the interrupt receiving and driving unit, the VXI bus configuration register, the address decoder, the interface state device and control logic unit as well as the interrupter and interrupt daisy chain etc. The interface design is realized through hardware logic, possessing interfaces for setting multiple signals outside the chip and providing the address signals and the read/write signals needed by the local. Thus, designers to not need to define the offset address registers in configuration registers and the related decoding circuit through VXI bus. The circuit is easy to use and applicable to development of A16, A16/A24, A16/A32 modules in automated test systems based on VXI bus.

Description

The vxi bus register base is from logic glue

Technical field

The present invention relates to technical field of measurement and test, specifically is that a kind of vxi bus register base is from logic glue.

Background technology

Based on VXI (VMEbus Extension for Instrument, IEEE STD 1155) advantage of the module instrument of bussing technique is the Auto-Test System that is easy to be integrated into different purposes, has good interoperability, the message transmission rate height, the reliability height, easy-maintaining, volume is little, in light weight, low in energy consumption, mobility is good.What vxi bus adopted is the addressing system and the modularized design thinking of VME bus.But, in order to adapt to instrument design and the integrated needs of Auto-Test System, on the basis of VME bus, additionally increased many functions towards field tests, just comprise that wherein VXI module instrument takies the configuration and the software and hardware resources management of system memory resources.All functions must cooperate by vxi bus interface appropriate design to be finished.

The vxi bus instrument module has three kinds from the port addressing mode: A16, A16/A24, A16/A32, maximum addressable space is defined as 64 respectively, 8M, 2G byte.The actual demand of instrument module physical space is that the hardware designs personnel realize by offset address register in the configuration register of vxi bus definition and associated translation circuit in the system.

There is following shortcoming from the VXI that provides in the market from the interface process chip:

1) only realized the basic function of VXI from interface, the user needs more extra design of hardware and software could realize required, complex interface function comparatively, and cost is higher.

2) during VXI modular circuit single board design, this locality needs CPU to support just can finish the operate as normal of interface.For the veneer circuit that does not need CPU more, can not use ready-made interface chip to realize the VXI interface function.

Summary of the invention

The objective of the invention is to provides an improved vxi bus register base from logic glue for the application of VXI module hardware, it adopts hardware logic to realize Interface design, have multiple external signal and select to be provided with interface, the designer need not be concerned about offset address register in the vxi bus definition configuration register and associated translation circuit etc., easy to use, can improve design efficiency, reduce development cost.

Vxi bus register base of the present invention comprises that from logic glue address control signal receiver, data collector, common bus receiver and interrupt signal receive driver element, is characterized in that also comprising:

The vxi bus configuration register, it is connected with data collector, common bus receiver respectively, according to the outer setting model sign indicating number definition module of its input port, selects the A16/D16 configuration register of VXI code requirement;

A16, A24, A32 address decoder, it is connected with vxi bus configuration register, data collector, address controlling receiver respectively, logical address switch that its respective input mouth contact pin is outer and 4 bit address space are selected signal, can select signal according to described outer logical address switch and 4 bit address space, switch three kinds of address spaces of A16/A24/A32 and select corresponding addressing space size, required reading is provided;

Address latch, it is connected with the output of A16, A24, A32 address decoder, is used to provide address wire and the local decoding of read-write common user through latching to use;

Interface state machine and control logic unit, it respectively with the common bus receiver, and A16, A24, A32 address decoder connect, and is used for finishing that address space switches, transfer of data is replied, reply interrupt cycle, number passes the Cycle Length adjustment and local reset signal etc. is provided;

And interrupter and interruption daisy chain, it is connected with the interrupt levels switch that interface state machine and control logic unit, interrupt signal receive outside driver element and the sheet respectively, is used for handling local interrupt event, interrupts to the vxi bus application.

Vxi bus register base of the present invention is as follows from the major advantage of logic glue:

1) support VXI A16, three kind of 16 bit addressing mode of A16/A24, A16/A32, three kinds of address spaces switch in an interface logic and use.

2) but the model sign indicating number sheet of VXI module be provided with outward, made things convenient for the definition of user to module.

3) VXI interface A24, A32 address space sheet are selected outward, flexible configuration, the module interface of different size capable of being combined.

4) the VXI interrupt levels is provided with outward by sheet.

5) the port addressing cycle is adjustable.

6) interface need not the local cpu support.

7) owing to adopt hardware logic to realize Interface design, the user need not to pay close attention to interface, can be absorbed in the design of module local circuit, has improved design efficiency, reduces development cost.The present invention is applicable to the exploitation based on the A16 of the Auto-Test System of vxi bus, A16/A24, A16/A32 module.

Description of drawings

Fig. 1 is that vxi bus is from the interface logic block diagram.

Embodiment

The present invention is further described from interface logic block diagram 1 below in conjunction with vxi bus.Vxi bus signal definition and bus receive, drive, receive and dispatch electric rule, can be with reference to " VMEbus Standard:IEC821 " standard-required.

Shown in Figure 1 from logic glue, comprising: address control signal receiver, data collector, common bus receiver, interrupt signal receive driver element, vxi bus configuration register, address decoder, interface state machine and control logic unit, interrupter and interruption daisy chain and address latch etc.

The vxi bus configuration register mainly is achieved as follows the A16/D16 configuration register of VXI code requirement, and five registers are as shown in table 1.It is connected with data collector, common bus receiver respectively, and sheet external model sign indicating number is provided with and inserts on the type of device register, for user flexibility arbitrary value in 0～FFFH scope is set, and is used for the uniqueness of identification module.

Table 1

The address offset amount	The VXI register
		????00H	The ID register
????02H	The type of device register
		????04H	State/control register
????08H	The offset address register
		????0A-3FH	User definition

A16, A24, A32 address decoder, it is connected with vxi bus configuration register, data collector, address controlling receiver respectively, and its respective input mouth is connected to the outer logical address switch of sheet and 4 bit address space are selected signal.At the 0A-3EH in A16 space address section, this interface has directly translated 16 reading common users and has used.If still not enough, also be provided with an address latch, for also providing through the address wire and the local decoding of read-write common user of latching, uses this interface.

A24, the switching of A32 address space and space size are optional to be one of main feature of the present invention.The interface logic outside provides 4 bits to select signal b3～b0 to carry out the address space switching and the addressing space size is selected, and the design of port addressing scope is as shown in table 2, and wherein b3 is used for switching the A24/A32 space, and b2～b0 is used for selecting the space size.

Table 2

Address space	Select signal b3～b0	The space size
			??A24	?0	?16KB
	?1	?32KB
				?2	?64KB
	?3	?128KB
				?4	?256KB
	?5	?512KB
				?6	?1MB
	?7	?2MB
			??A32	?8	?64KB
	?9	?128KB
				?10	?256KB
	?11	?512KB
				?12	?1MB
	?13	?2MB
				?14	?4MB
	?15	?8MB

B3～b0 can or upper and lowerly draw mode setting by the outer toggle switch of sheet.The big I in A24 space is selected in 16K～2M scope; The big I in A32 space is selected in 64K～8M scope.This optional design can satisfy most users' instrument module design requirement.

Interface state machine and control logic unit, it respectively with the common bus receiver, and A16, A24, A32 address decoder be connected, it is used for realizing the transition of interface operating state, finishes that address space switches, transfer of data is replied, reply interrupt cycle, number passes the Cycle Length adjustment, function such as local reset signal is provided.The interface logic work clock is 16MHz.

In order to make the different chip of interface logic energy addressing work speed, number passes Cycle Length must be controlled.This interface logic is with a local BUSY ^*Waiting signal comes control cycle length (control DTACK ^*The generation time of signal).BUSY ^*For height is represented the transmission by normal speed 125ns, BUSY ^*For low, press the 1us speed rates.

Interrupter, interruption daisy chain, it receives driver element with interface state machine with control logic unit, interrupt signal respectively and the interrupt levels switch is connected.Realize a ROAK (Release OnAcknowledge) interrupter, can handle local four interrupt events, interrupt to the vxi bus application, seven interrupt levelss can be by outside 3 bit signal line options.

VXI interface of the present invention directly provides A16-A1 ten six roots of sensation address wires and relevant read-write through latching to be total to local the use to this locality, and the maximum address space is the 128K byte.If the user needs bigger addressing space, this interface also provides address latch signal to this locality, and the user can latch the extra address wire from vxi bus.This interface also provides the input of two local self check status signals: self check is passed through and is ready.Make the VXI module correctly support of the management of the Zero greeve controller of vxi bus platform to this module.

The present invention is applicable to the exploitation based on the A16 of the Auto-Test System of vxi bus, A16/A24, A16/A32 module.

Claims (1)

1, a kind of vxi bus register base comprises that from logic glue address control signal receiver, data collector, common bus receiver and interrupt signal receive driver element, is characterized in that also comprising:

The vxi bus configuration register, it is connected with data collector, common bus receiver respectively, selects the A16/D16 configuration register of VXI code requirement according to the outer setting model sign indicating number of its input port;

A16, A24, A32 address decoder, it is connected with vxi bus configuration register, data collector, address controlling receiver respectively, logical address switch that its respective input mouth contact pin is outer and 4 bit address space are selected signal, can select signal according to described outer logical address switch and 4 bit address space, switch three kinds of address spaces of A16/A24/A32 and select corresponding addressing space size, required reading is provided;

Address latch, it is connected with the output of A16, A24, A32 address decoder, is used to provide address wire and the local decoding of read-write common user through latching to use;

Interface state machine and control logic unit, it respectively with the common bus receiver, and A16, A24, A32 address decoder connect, and is used for finishing that address space switches, transfer of data is replied, reply interrupt cycle, number passes the Cycle Length adjustment and local reset signal etc. is provided;

And interrupter and interruption daisy chain, it is connected with the interrupt levels switch that interface state machine and control logic unit, interrupt signal receive outside driver element and the sheet respectively, is used for handling local interrupt event, interrupts to the vxi bus application.