CN1447430A - Ferroelectric monotube latching structure and flushbonding type non-volatile logic IC - Google Patents
Ferroelectric monotube latching structure and flushbonding type non-volatile logic IC Download PDFInfo
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- CN1447430A CN1447430A CN 03115373 CN03115373A CN1447430A CN 1447430 A CN1447430 A CN 1447430A CN 03115373 CN03115373 CN 03115373 CN 03115373 A CN03115373 A CN 03115373A CN 1447430 A CN1447430 A CN 1447430A
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Abstract
Combining the ferroelectric monotube unit, the transfer gate, the resistances, the phase inverter and the logic gates etc digital circuit basic units constitute the fereoelectric monotube latching structure. The structure the function of latching the logic states of the digital circuit. Thus, non-volatile logic of whole chip can be realized by embedding the ferroelectric monotube latching structure into Large Scale Integrated circuits.
Description
Technical field
The invention belongs to the large-scale digital ic technical field, be specifically related to a kind ofly utilize ferroelectric single tube to latch structure and the non-volatile logical integrated circuit of embedding realized of circuit structure thus.
Background technology
The general tool volatility of large-scale digital ic: when power remove, the information that is stored in the digital system can be lost; When power supply is opened again, still can't recover in the information that the power down eve is stored in the digital system.
If when power down digital system in volatile information write in the nonvolatile memory array by certain addressing mechanism, again each information is read into from nonvolatile memory on the corresponding logical node of digital system when powering on, can realizes the non-volatile of logical message.But owing to need complicated addressing mechanism and read-write control, required time of read-write operation is long, and speed is slow, is difficult to deal with such as accidents such as power down.If adopt Embedded method, with near the nonvolatile memory cell timely preservation state information when the power down that is distributed in each logical node, when powering on state information is write in the logical node corresponding with it, then can realize non-volatile digital integrated circuit truly.
Though existing in the market E
2The non-volatile read-write memories of semiconductor such as PROM, Flash Memory, but because the shortcoming that himself exists: (1) read or write speed is slower, is the ms magnitude; (2) operating voltage is higher, needs the additional pressurization pump circuit, increases device count and area; (3) number of times read-write, that wipe is limited; (4) a little less than the anti-irradiation ability, make these nonvolatile memory spares be difficult to realize embedded non-volatile logic with the digital circuit coupling of high speed, low-power consumption.
Summary of the invention
The objective of the invention is to propose a kind of read or write speed fast, read non-destruction, antifatigue, circuit structure and be easy to simply realize that the ferroelectric non-volatile single tube of extensive integrated and anti-width of cloth photograph latchs structure, and utilize ferroelectric single tube to latch the non-volatile logical integrated circuit of low-power consumption that structure is formed.
The present invention proposes ferroelectric non-volatile single tube and latchs structure, by ferroelectric Transistor Cell M and transmission gate 1. one 8., digital circuit elementary cell such as phase inverter N, resistance R esistor, some gates combines and constitutes, and sees shown in Figure 1.Wherein, node D, G, S are respectively leakage, grid, the source end of ferroelectric Transistor Cell M.The basic structure of ferroelectric Transistor Cell M is the grid deposit one deck ferroelectric thin film at metal-oxide-semiconductor.Because ferroelectric thin film has spontaneous and remanent polarization, and the carrier concentration of the semiconductor surface that is in contact with it is changed, semiconductor surface can be with bend, thereby have the effect that modulation semiconductor surface electricity is led.At the grid biasing of ferroelectric Transistor Cell M, can form conducting channel or not have conducting channel between source, leakage.Utilize the conducting of semiconductor surface raceway groove and just can write down logical zero and 1 two states by two states.
At the grid of ferroelectric Transistor Cell M, connecting transmission gate 1., 2., output 3..Transmission gate is a kind of basic device in the electronic circuit, leaks butt joint by the metal-oxide-semiconductor source of two conducting channel complementations and forms, and the grid of two complementations is controlled the break-make of this device simultaneously.Among Fig. 1,1. input termination power level of transmission gate (get among the figure+5V is an example), the grid of its NMOS is subjected to the control of signal WQ, the control signal of PMOS grid and the complementation of NMOS.WQ be the write signal W that sends of the system logical node Q value that will write down during with power down with logical consequence.Transmission gate input end grounding (0V) 2., the grid of its NMOS is subjected to signal WQ
-Control.Q
-Complementary for logical node Q.Transmission gate input termination 3. read voltage (about 0～+ 2V, get among the figure+0.5V is an example), the grid of its NMOS is subjected to the control of signal R.R is the read signal that system sends.
In the drain electrode of ferroelectric Transistor Cell M, connecting resistance R esistor, the other end of resistance is connecting the output of transmission gate 4,5.Transmission gate input end grounding (0V) 4., the grid of its NMOS is subjected to the control of signal WQ.Transmission gate input termination power level 5., the grid of its NMOS is subjected to signal R+WQ
-Control.Signal R+WQ
-Be signal R and signal WQ
-Or logical consequence mutually.Also connecting the input of a phase inverter in the drain electrode of ferroelectric Transistor Cell M, the output of phase inverter is connecting transmission gate input 8..The logical node Q that will write down in the transmission gate output termination digital system 8., the grid of its NMOS is subjected to the control of read signal R.
At the source electrode of ferroelectric Transistor Cell M, connecting transmission gate 6., output 7..Transmission gate input end grounding (0V) 6., the grid of its NMOS is subjected to the control of signal R+WQ.Signal R+WQ be signal R with signal WQ mutually or logical consequence.Transmission gate input termination power level 7., the grid of its NMOS is subjected to signal WQ
-Control.
The operation principle that above-mentioned ferroelectric single tube latchs structure is as follows:
When the digital system operate as normal, 1.-8. the diagram transmission gate all disconnects, and ferroelectric Transistor Cell M and digital system are isolated fully.
When needs are done one writing when operation to this structure, transmission gate 1., 4., 6. open, power level is added on the grid of ferroelectric Transistor Cell M, this moment the source, leak equal ground connection.Impressed field forces the ferroelectric thin film layer among the ferroelectric Transistor Cell M to reach positive saturated polarization.Semiconductor surface strong inversion between leak in the source forms conductive channel.When transmission gate turn-offed, because ferroelectric thin film has remanent polarization+Pr, the conducting channel of semiconductor surface still existed." 1 " is latched among the ferroelectric Transistor Cell M at this moment.
When needs read on the logical node with " 1 ", transmission gate 3., 5., 6., 8. open, voltage official post conducting channel between leak in the source produces certain electric current, resistance by the drain terminal serial connection is converted into magnitude of voltage with current value, by the phase inverter N that plays the A/D function magnitude of voltage of simulating is changed into digital logical value " 1 " again, and be written on the logical node by transmission gate 8.
When needs are write " 0 " when operation to this structure, transmission gate 2., 5., 7. open, 0V is added on the grid of ferroelectric Transistor Cell M, this moment, power level was missed in the source.Impressed field forces the ferroelectric thin film layer among the ferroelectric Transistor Cell M to reach negative saturated polarization.The surface conduction channel attenuation.When transmission gate turn-offs, because the effect of the remanent polarization-Pr of ferroelectric thin film still keeps the raceway groove situation of semiconductor surface." 0 " is latched among the ferroelectric Transistor Cell M at this moment.
When needs read on the logical node with " 0 ", transmission gate 3., 5., 6., 8. open, the source-drain current that produces is very faint, utilize the resistance of drain terminal serial connection that little current value is converted into magnitude of voltage, by phase inverter N the magnitude of voltage of simulating is changed into digital logical value " 0 " again, and 8. be written on the logical node by transmission gate.
Like this, two kinds of different conditions of ferroelectric thin film residual polarization can make ferroelectric single tube latch structure to be in 0,1 two states, and this two states just can latch the value of information on the logical node under the situation of not powering.
Latch structure for above-mentioned ferroelectric single tube, can do following corresponding conversion:
Because 1., 5., 7. transmission gate only transmits power level under conducting state, can substitute by single PMOS pipe; 2., 4., 6. transmission gate only transmits the 0V level under conducting state, can be substituted by single NMOS pipe; 3. transmission gate transmit between 0 following of conducting state～+ 2V read level, also can substitute by single NMOS pipe.And 8. transmission gate promptly may transmit power level, also may transmit the 0V level, has only the form that adopts transmission gate all not send to loss two kinds of level to logical node.Structure as shown in Figure 2.
Transmission gate among Fig. 2 1.-2., 4.-8. triple gate in the similar digital circuit of role, transmission 0 or 1 two kind of logical value when conducting, by the time be in high-impedance state, therefore can with any type of triple gate alternative it, but circuit form comes complicatedly than the aforementioned triple gate that is formed by one or two metal-oxide-semiconductor.
In addition, can 1. and 2. merge into the transmission gate among Fig. 2 No. two selectors of strap choosing, sheet selects and is in high-impedance state when invalid, and sheet selects when effective, selects to be output as 1 or 0 according to corresponding control logic.4. and 5. in like manner, transmission gate, 6. and 7. transmission gate also can be replaced by No. two selectors, as long as read-write R, W and logical node Q or Q that chip selection signal and control signal are sent by system
-Produce by certain combinational logic, just can realize identical latch function.As shown in Figure 3.
In addition, power level or the 0V that ferroelectric Transistor Cell M grid, leakage, each end of source transmit when write operation also can be by logical node Q, Q
-Logical value 1 or 0 replace.At this moment, be input as Q or Q if adopt
-, control end is that the alignment formula CMOS triple gate of write signal W can realize that ferroelectric single tube latchs the function of structure.As shown in Figure 4.Can also derive the circuit form of forming by various triple gates thus, but the basic functional principle of circuit is constant.
The present invention also latchs structure applications in large-scale digital ic with above-mentioned ferroelectric single tube.Because ferroelectric single tube latchs structure and has non-volatile, anti-irradiation, antifatigue and advantage such as read for non-destructive, can realize latching the function of the logic state of digital circuit, and read or write speed is in the 10ns magnitude, be enough to deal with accidents such as power down, add simple in structure, required supply voltage is compatible mutually with digital system, make this structure can be embedded in the large-scale digital ic, promptly on each logical node of sequential logical circuit, all embed above-mentioned ferroelectric single tube and latch structure, latch structure to ferroelectric single tube during power down and write logical value, read again when powering on, just can realize the non-volatile of whole digital system logical value, constitute " ferroelectric single tube latchs embedded non-volatile digital integrated circuit ".
Ferroelectric single tube latchs embedded non-volatile digital integrated circuit and is with a wide range of applications.As previously mentioned, can be applicable in computer and the electronic testing instrument.When power supply interrupted suddenly, ferroelectric single tube latched structure and can protect the information in computer or the tester to prevent loss immediately.Can recover automatically again to cut off the power supply when system restarts all information of eve make computer and tester continue normal operation.
In addition, ferroelectric single tube latchs embedded non-volatile digital integrated circuit and also is applicable to various low energy consumption occasions, as portable computer, and portable communications system, smart card etc.Because its unique capability of resistance to radiation is particularly useful for energy-conservation occasions such as Aero-Space electronic equipment.When above-mentioned each electronic system need not operate, system information deposited in and be distributed in intrasystem each ferroelectric single tube and latch in the structure and turn off power supply, when power supply starts once more, can automatically information be recovered again, thereby save energy consumption, can be rated as " green chip ".
Description of drawings
Fig. 1 latchs structural diagrams for ferroelectric single tube.
Fig. 2 latchs one of malformation for ferroelectric single tube.
Fig. 3 latchs two of malformation for ferroelectric single tube.
Fig. 4 latchs three of malformation for ferroelectric single tube.
Fig. 5 is for to latch the structural diagrams that become non-volatile frequency divider of structure applications in trigger with ferroelectric single tube.
Fig. 6 is the simulation waveform figure of non-volatile frequency divider simulation power down.
Embodiment
Because trigger is the elementary cell of digital system sequential logical circuit, provides below ferroelectric single tube is latched structure applications constitutes non-volatile frequency divider in d type flip flop example.
Fig. 5 is the structure chart that is latched the non-volatile frequency divider of structure realization by ferroelectric single tube.Wherein, two frequency dividing circuits for constituting in the frame of broken lines by d type flip flop.Node 1 is connecting transmission gate I to node 2, wherein, and the control of the NMOS tube grid subject clock signal clk of transmission gate I (transmission gate among Fig. 5 all only marks out the control signal of NMOS, because therefore control signal and the NMOS complementation of PMOS save mark in the drawings).What node 2 was connecting phase inverter I is input to node 3.What node 3 was connecting phase inverter II is input to node 4.Node 4 is connecting transmission gate II and is getting back to node 2, wherein, and the reverse signal clk of the NMOS tube grid subject clock signal clk of transmission gate II
-Control.Node 3 is connecting transmission gate III again to node 5, and wherein, the NMOS tube grid of transmission gate III is subjected to reverse clock signal clk
-Control.What node 5 was connecting phase inverter III is input to node 6.What node 6 was connecting phase inverter IV is input to node 7.Node 7 is connecting transmission gate IV again and is getting back to node 5, wherein, and the control of the NMOS tube grid subject clock signal clk of transmission gate IV.It is input that said structure has constituted with node 1, and node 6 is output Q, and node 7 is inverse output terminal Q
-D type flip flop.Link to each other with input by phase inverter V if will export Q, just can constitute output frequency is the frequency divider of clock signal clk frequency 1/2.The logical node of this frequency divider is a node 5.As long as in time write down the logical value of node 5 during power down, recover the logical value of this point when powering on, just can guarantee that circuit can continue operate as normal with the state of power down eve.Therefore, by output Q, the Q of frequency divider
-And system the read-write R, the W that send control the operation that ferroelectric single tube latchs structure, and the output of ferroelectric single tube being latched structure is connected with node 5, has constituted non-volatile frequency dividing circuit thus.
Fig. 6 has provided the simulation waveform of non-volatile frequency divider simulation power-down conditions.As seen from the figure, system sends write signal W when power supply power down for the first time, and this moment, Q was 0, Q
-Be 1.The single tube latch cicuit is activated writes " 0 " operation.System sends read signal R when and then powering on, and " 0 " is read among the Q.After read signal W was sent in power supply power down for the second time, this moment, Q was 1, Q
-Be 0.The single tube latch cicuit is activated and carries out the one writing operation.System sends read signal R again when and then powering on, and " 1 " is read among the Q.As seen, be embedded in that ferroelectric single tube in the frequency divider latchs structure latch information when having reached power down, the requirement of recovering information when powering on, thereby realized the function of non-volatile frequency divider.
Claims (5)
1, a kind of non-volatile ferroelectric single tube latchs structure, by ferroelectric Transistor Cell M, transmission gate 1.-8., phase inverter N, resistance R esistor and some gates combine and constitute, wherein the basic structure of ferroelectric Transistor Cell M is: at deposit one deck ferroelectric thin film on the grid of MOS structure and come electric current between modulation source, leakage with the polarized state of ferroelectric thin film, the grid G of ferroelectric Transistor Cell M and transmission gate 1., 2., output 3. is connected; Drain D is connected with resistance R esistor, and the other end of resistance and transmission gate are 4., output 5. is connected, and drain D also is connected with the input of phase inverter N, and the output of phase inverter is connected with transmission gate input 8.; Source S and transmission gate are 6., output 7. is connected.
2, non-volatile ferroelectric single tube according to claim 1 latchs structure, it is characterized in that wherein transmission gate 1., 5., 7. substituted by single PMOS pipe, transmission gate 2., 4., 6. substitute by single NMOS pipe, 3. transmission gate is substituted by single NMOS pipe.
3, non-volatile ferroelectric single tube according to claim 1 latchs structure, it is characterized in that transmission gate 1. and 2., transmission gate 4. and 5., 6. and 7. transmission gate substituted by No. two selectors respectively.
4, non-volatile ferroelectric single tube according to claim 1 latchs structure, it is characterized in that when write operation, and power level that the grid of ferroelectric Transistor Cell, leakage, each end of source transmit or 0V are by logical node Q, Q
-Logical value 1 or 0 replace.
5, a kind of non-volatile logical integrated circuit is characterized in that embedding arbitrary non-volatile ferroelectric single tube that is made of ferroelectric Transistor Cell on each logical node of sequential logic part of large-scale digital ic latchs structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03115373 CN1253940C (en) | 2003-02-13 | 2003-02-13 | Ferroelectric monotube latching structure and flushbonding type non-volatile logic IC |
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|---|---|---|---|
| CN 03115373 CN1253940C (en) | 2003-02-13 | 2003-02-13 | Ferroelectric monotube latching structure and flushbonding type non-volatile logic IC |
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| CN1253940C CN1253940C (en) | 2006-04-26 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109970358A (en) * | 2019-03-28 | 2019-07-05 | 电子科技大学 | A kind of optical drive logic device and its application method based on studies on BIT-based ferroelectric thin films |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109970358A (en) * | 2019-03-28 | 2019-07-05 | 电子科技大学 | A kind of optical drive logic device and its application method based on studies on BIT-based ferroelectric thin films |
| CN109970358B (en) * | 2019-03-28 | 2021-09-28 | 电子科技大学 | Optical drive logic device based on bismuth titanate-based ferroelectric film and application method thereof |
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