CN1442790A - Extending method for extending ROM of computer and interface chip thereof - Google Patents

Abstract

A method and interface chip for increasing the capacity of an extendible ROM is disclosed. Said ROM chip is composed of a basic block and extendible block. Said basic block has the characteristics and content needed by a standard ROM chip and low capacity, so it can be mapped to the memory space. Said extendible block and whole ROM chip can be mapped to a group of I/O ports in I/O space. Its start address is set up by control port. Its data can be accessed from data port. The data in extendible block and whole ROM chip can be accessed in automatic address increment mode.

Description

The expansion method of extending ROM of computer and interface chip

The present invention relates to the expansion method and the interface chip of the expansion ROM of computer PCI bus, but especially capacity is mapped to the method and the interface chip of the access space of computer system greater than the expansion ROM of UMB clear area.

Expansion ROM standard and pci bus standard according to PC must have a header section in the rom chip of expansion ROM, so that allow computer system detect this expansion ROM and auto-initiation.The header section of ROM mainly comprises: the data of 0000H address are 55H, and the data of 0001H address are OAAH, and the data of 0002H address are indicated byte etc. for the ROM capacity.Computer system is in the POST process of scanning expansion ROM, to detect the header section that meets above-mentioned requirements and correct data check and to confirm existing and effectively of expansion ROM.Expansion ROM must can be mapped to storage space, in computer system, the expansion ROM space belongs to the part in the storage space, computer system is as the program of carrying out in the internal memory, by the initialization module among the invoke extensions ROM, give expansion ROM with control, it is carried out initialization.But for the expansion ROM of pci bus, computer system at first with the expansion ROM spatial mappings in storage space, then the data in the rom chip are copied in the UMB, remove the mapping relations in expansion ROM space again, make itself and storage space isolated.Final computer system is carried out initialization to the expansion ROM of pci bus and to the core image write-protect in the core image of expansion ROM; replace the mode of true ROM like this with core image; both made expansion ROM still be positioned UMB; kept compatibility; avoid the speed influence of low speed ROM again, kept the efficient of high-speed PCI bus.

The expansion ROM of current pci bus is mainly used in and realizes some function in the computer initialization process, and for example: the expansion ROM of video card is used for the initialization video card and strengthens the Presentation Function of BIOS; The expansion ROM of SCSI card is used for the initialization scsi device; The expansion ROM of hard disk reduction card (hard disk protecting card, system reset card are arranged similarly) is used for obtaining control in the computer initialization process; and then the input and output of interception and inspection hard disc data; thereby can protect and reduce the hard disc data of user's selection area, to prevent mistake deletion, deliberately to destroy and anti-virus etc.This class expansion ROM is provided with in rom chip realizes necessary computer program code of correlation function and data, and be used to indicate the effective header section of this expansion ROM, computer system with the content replication in the rom chip in the UMB zone of storage space, then in core image, rather than in ROM, carry out the initialization module supervisor of expansion ROM.Referring to Fig. 1, the PC storage space generally includes the Extended RAM (Expanded Memory) of conventional memory (Conventional Memory), UMB (Upper Memory), exented memory (Extended Memory) and less use at present.The UMB zone typically refers to the zone that specific address is A0000H to FFFFFH, wherein the address is that the zone of A0000H to BFFFFH is used for the display buffer, the address is the expansion ROM that the zone of C0000H to C7FFFH is generally used for video card, the address is the BIOS (early stage BIOS is simple, only uses above zone, F0000H address) that the zone of E0000H to FFFFFH is generally used for computer system.The UMB zone that is not assigned with, promptly the address is the zone between the C000H to DFFFFH, the 96KB capacity that is to say that as the free space of expansion ROM the summation of the capacity of each expansion ROM should not surpass 96KB altogether.

Current actual conditions and development trend are: first, BIOS need constantly increase new function, for example support usb bus and equipment in the future, so current BIOS has still adopted the expansion method of paging access after data compression, temporarily more UMB can be do not taken, but any space can be do not abdicated yet; Second, the development of current video card makes the expansion ROM capacity of most of video cards surpass 32KB, the AGP video card of for example a employing ATI RAGE 128GL chip, its expansion ROM capacity is 44KB, another money adopts the AGP 2X video card of ATI RAGE MOBILITY-M, its expansion ROM capacity is 64KB, stays the spatial summation of using to each expansion ROM like this and will only be left 64KB; The 3rd, each has the equipment of expansion ROM because the development of self needs more available RO space to go to realize more function.So the expansion method of a kind of expansion ROM of needs provides big as far as possible available ROM space with as far as possible little space hold.

Existing some expansion ROM has adopted the expansion method of known a kind of similar BIOS paging access, this method is divided into the less page or leaf of some capacity with the whole rom chip of expansion ROM, then undertaken with the exchanges data of rom chip, and no longer take the UMB zone that is equivalent to whole ROM capacity by a page window.Operating process is, initialization module in the rom chip is being called back acquisition control by computer system, other program among initialization module and the ROM writes data to page control register as required, specifies the page number of the access of wanting, and passes through the data of this page of page window access again.But there is following shortcoming in this method: first, efficient is low, after the computer system warm reset, data in the page control register are unexpected, specify a page that does not have header section in order to prevent this unknown data, each page of expansion ROM all needs to be provided with identical header section and initialization module, so will reduce the actual active volume of rom chip, and window is more little, the actual more at most active volume of the page is more little, expansion ROM for pci bus, because computer system copies to the data among the ROM in the UMB, data in the internal memory only are the maps of certain page of rom chip, so realize page accesses, can only open a page window again in other free memory zone, so altogether needs are taken the UMB zone that doubles page window size, and the big more then committed memory of page window is many more; Second, poor compatibility, just there was physical memory originally in UMB zone in storage space, when the expansion ROM spatial mappings after storage space, might clash with the existing internal memory of same address, so after computer system copies to internal memory with the data among the ROM, the BIOS of most mainboards can isolate real expansion ROM space, also can be behind os starting because of the page window that the use in UMB zone has been covered expansion ROM, so might be by the content of page window access to whole rom chip.Certainly, because BIOS is the control program of PC indispensability, not needing header section, itself is again the master of map operation, can not have above-mentioned shortcoming so this expansion method is applied to BIOS, then exists but be applied to expansion ROM.

The objective of the invention is, the expansion method of the higher expansion ROM of a kind of efficient and compatibility and the pci bus interface chip of supporting the high capacity expansion ROM based on this method are provided.

Technical conceive of the present invention is: in order to keep compatible, can be with the raw data of the part necessity in the rom chip, and for example header section, initialization module still provide by the less expansion ROM of the capacity that is mapped to storage space; Because the expansion ROM of pci bus mainly is to use its core image, the expansion ROM and the storage space of reality will be isolated after the raw data of computer system in having duplicated rom chip, and the I/O port all can access after the system start-up of computer initialization process neutralization operation, so the most of raw data in the rom chip can be made into to provide by the I/O port that is mapped to input/output space; With reference to the method for CMOS RAM by address/index port 70H and tens data unit of FPDP 71H access, the present invention is mapped to the rom chip of linearity addressing in one group of I/O port, by control port the mode of start address and FPDP access data and auto-increment address is set, supports jumbo expansion ROM.

Realize that technical scheme of the present invention comprises following four aspects:

1, the hardware interface aspect of expansion ROM, increase a presettable counter and one group of I/O port that is used for expansion ROM, the I/O port comprises control port and FPDP, control port is mainly used in the start address that presets data block that will access in presettable counter, FPDP is used for data access, and after the intact data of access,, make it to count to point to the address of next data to presettable counter output count signal;

2, the space layout aspect of rom chip, the rom chip (1) of expansion ROM is divided into fundamental block (11) and extension blocks (12), in fundamental block, have in the rom chip of expansion ROM of a standard the feature and the content that must have, the header section of expansion ROM and necessary initialization module all are arranged in the fundamental block, and the ROM capacity indication byte in the header section is only indicated the size of fundamental block and do not comprised extension blocks;

3, the access aspect of fundamental block (11), fundamental block can be mapped to the storage space (2) of computer system, thereby can be detected and initialization by computer system by the processing mode of existing expansion ROM, the detected expansion ROM of computer system only comprises this fundamental block;

4, the access aspect of extension blocks (12), extension blocks and whole rom chip can be mapped in one group of I/O port of input/output space (3) of computer system, initialization module in the fundamental block and other program can be as required, insert the start address of data block in rom chip of the access of wanting to control port, access data constantly from FPDP then, up to the intact desired data block of access, every access finishes data, presettable counter auto-increment then is to point to the address of next data.

The hardware interface aspect of the expansion ROM of such scheme, further also have one group of data selector and logic sum gate, data selector make when the I/O port access expansion ROM to the count value of rom chip output presettable counter as the access address, and when the fundamental block by storage space access expansion ROM the relative address in the specified fundamental block during to the rom chip output access; Logic sum gate will carry out or operate from the access control signal of I/O port and access control signal from storage space, thereby the rom chip that makes expansion ROM can be accepted the access requirement from the I/O port, can accept the access requirement from storage space again.

Based on such scheme, for the idle UMB that is not more than the 96KB capacity, expansion ROM only takies the zone that is equivalent to the fundamental block size, by current expansion ROM standard, the I of the capacity of the fundamental block in the rom chip is to 2KB, use the header section and the initialization module of the expansion ROM of setting aside concerns for general expansion ROM; For the input/output space that is 65536 I/O port addresss to the maximum, expansion ROM takies two I/O port addresss at most, is respectively applied for control port and FPDP.Though this scheme has only been used Limited resources, in theory, the capacity of the expansion ROM that this scheme can be supported (capacity of rom chip just) does not have any direct restriction.

The I/O port that is used for expansion ROM in the such scheme, when not needing to support rom chip online erasable, the synthetic bidirectional port of read-only FPDP and the control port of only writing promptly only can be taken an I/O port address, further reduce taking system resource.

Aspect concrete enforcement, can make the fundamental block in the rom chip as much as possible little, and presettable counter be provided be equivalent to the address of whole rom chip scope, make the I/O port can access to whole rom chip.Just, after control port is inserted the relative origin of needed data rom chip, just can be by any data of FPDP access in fundamental block and the extension blocks.PC for adopting X86 and compatible family CPU, when the data that read by the I/O FPDP among the ROM, can use following assembly instruction sequence (being example with 16 bit instructions and address):

" mov di, the start address of data buffer "; Appointment with the deposit data of reading in this piece internal memory

" mov cx wants the byte number of reading of data "; Appointment will be read so multidata

" mov dx, the address of control I/O port ",

" mov ax wants the start address of reading of data "; Specify and want the start address of reading of data in ROM

" out dx, ax "; Insert and want the start address of reading of data in ROM

" mov dx, the address of data I/O port ",

“cld”，

“rep?insb”。 Allow CPU from FPDP, read continuously automatically

Above-mentioned instruction sequence can also be optimized, and for example once reads 4 bytes rather than 1 byte, to improve access speed.In pci bus, the access speed of expansion ROM data mainly is subject to rom chip itself, so therefore the speed by FPDP access ROM data be not lower than and existing expansion ROM be mapped to the storage space mode of access data again.

Hardware interface part in the technique scheme can be carried out integrated, to reduce batch cost, final primordial is in the pci bus interface chip of the support high capacity expansion ROM of technical solution of the present invention, or be integrated in the control chip of the miscellaneous equipment of supporting expansion ROM, for example be integrated in the control chip of video card or SCSI card.

Based on technical scheme of the present invention, make jumbo expansion ROM can be applied to the limited PC of UMB, avoided the compatibility issue of the expansion method of paging access simultaneously, not reducing operational efficiency substantially, not increasing under the prerequisite of hardware cost and software overhead, realized the dilatation of expansion ROM.

The present invention is further illustrated below in conjunction with accompanying drawing.

Fig. 1 is the distribution schematic diagram and the development trend of the storage space of current PC.

Fig. 2 is the spatial mappings graph of a relation of technical solution of the present invention.

Fig. 3 is the circuit block diagram of the related hardware part of technical solution of the present invention.

The schematic diagram of Fig. 4 in the expansion ROM card, using based on the pci bus interface chip of technical solution of the present invention.

See Fig. 2, the rom chip of expansion ROM (1) is divided into fundamental block (11) and extension blocks (12).The same can being mapped in the storage space (2) of expansion ROM of fundamental block and existing not dilatation, in storage space, can only access arrive fundamental block, the expansion ROM map is the core image after the data with fundamental block copy to UMB, and expansion ROM only takies the UMB zone that is equivalent to the fundamental block size in storage space.Whole rom chip can be mapped in one group of I/O port of input/output space (3), in input/output space, can access arrive whole rom chip by being used of control port and FPDP, expansion ROM only takies two port addresss in input/output space, angle from input/output space, expansion ROM is a linear space like this: have the degree of depth that is equivalent to the rom chip capacity, the width that only is equivalent to I/O FPDP width, and width is not subjected to the influence of the degree of depth, so can support jumbo expansion ROM.

See Fig. 3, this is the circuit block diagram of hardware components related to the present invention, the part interface circuit and the storer that comprise expansion ROM are rom chip (1), but do not consider the online erasable of rom chip because simplify, the pci bus state machine of being responsible for each parts work of coordination in addition also is omitted in this figure.Command decoder (8A) carries out command decoder to the input of pci bus, produces memory read control signal (MEM-RD), I/O port reads control signal (IO-RD), I/O port write control signal (IO-WR).Internal bus (8M) is changed the signal of pci bus, produces address bus (A0-An), data bus (D0-Dn).Among this figure, presettable counter (8K) can be with reference to the principle of general digital circuit 74LS197; Comparer (8C) and (8G) can be with reference to the principle of general digital circuit 74LS688; Data selector (8L) can be with reference to the principle of general digital circuit 74LS157; Chronotron (8J) can be one group of trigger, also can realize by a state machine, be used for the back edge of the FPDP read control signal (PORT-RD) of expansion ROM is converted to address increment count signal (COUNT), just OPADD increment count signal (COUNT) after intact data by the FPDP access.

See Fig. 3, when computer system from storage space when this expansion ROM sends the read data requirement, comparer (8G) is compared the address (A0-An) of address bus with the expansion ROM plot (8F) in the configuration space, output expansion ROM plot matched signal (ROM), deliver to two input ends with door (8H) with the memory read control signal (MEM-RD) of command decoder (8A) output, with door (8H) output expansion ROM read control signal (ROM-RD), warp or door (8I) are to rom chip (1) output read control signal (READ); And the I/O port reads control signal (IO-RD) of command decoder this moment (8A) output is invalid, so it is invalid with the FPDP read control signal (PORT-RD) of the expansion ROM of door (8D) output, so data selector (8L) is selected from the address (A0-An) of the address bus address signal (ADDR) as rom chip (1), the i.e. access address with respect to the rom chip fundamental block of computer system appointment; Rom chip (1) outputs to the data of assigned address on the data bus (D0-Dn), and is returned to the computer system of sending the access requirement when receiving read control signal (READ).

See Fig. 3, when computer system is sent when presetting the requiring of start address to this expansion ROM from input/output space, comparer (8C) is compared the address (A0-An) of address bus with the I/O plot (8B) in the configuration space, the I/O port plot matched signal (PORT) of output expansion ROM, deliver to two input ends with door (8E) with the I/O port write control signal (IO-WR) of command decoder (8A) output, the write control signal of exporting the control port of expansion ROM with door (8E) is address preset signal (PRESET), presettable counter (8K) is when receiving address preset signal (PRESET), to be that start address is inserted counter from the data (DO-Dn) of data bus, as the initial count value of after this counting.

See Fig. 3, when computer system from input/output space when this expansion ROM sends requiring of read data, comparer (8C) is compared the address (A0-An) of address bus with the I/O plot (8B) in the configuration space, the I/O port plot matched signal (PORT) of output expansion ROM, deliver to two input ends with door (8D) with the I/O port reads control signal (IO-RD) of command decoder (8A) output, with the FPDP read control signal (PORT-RD) of door (8D) output expansion ROM, warp or door (8I) are to rom chip (1) output read control signal (READ); And this moment expansion ROM FPDP read control signal (PORT-RD) be effectively, so data selector (8L) is selected the current count value (P-ADDR) exported from presettable counter (8K) address signal (ADDR) as rom chip (1); Rom chip (1) outputs to the data of assigned address on the data bus (D0-Dn), and is returned to the computer system of sending the access requirement when receiving read control signal (READ); And chronotron (8J) is converted to address increment count signal (COUNT) with the back edge of the FPDP read control signal (PORT-RD) of expansion ROM after data are read, this signal makes presettable counter (8K) counting once, and the count value of output (P-ADDR) increases to the address of next data.

See Fig. 3, when computer system from input/output space when this expansion ROM sends requiring of next read data, data selector (8L) is still selected the address signal (ADDR) of the current count value (P-ADDR) of presettable counter (8K) output as rom chip (1), and this count value has been pointed to the address of next data, so when rom chip (1) receives same read control signal (READ), the data of next address will be returned, presettable counter (8K) is counted once more subsequently, to point to the address of next data again.So operation, just can access all data in the ROM.Can also reset start address when needing, to point to the data block that in the rom chip another will access.

See Fig. 4, this is the schematic diagram of the major part of an expansion ROM card.Expansion ROM card (7) has based on the pci bus interface chip (8) of the support high capacity expansion ROM of technical solution of the present invention and rom chip (1), and be connected to by pci bus interface chip (8) on the pci bus (6) of computing machine, pci bus interface chip (8) is connected with rom chip (1) by 8 bit data bus, 16 bit address buses and ROM read control signal line.Pci bus interface chip (8) is that model is the integrated circuit of WCHC0601, and rom chip (1) is that model is the integrated circuit of 27C512.The desired hardware interface part of technical solution of the present invention that this interface chip is integrated, this interface chip is supported the expansion ROM of 64KB capacity, but only mapping is not more than the fundamental block of 4KB in UMB, other extension blocks then is used access by what one group of I/O port was promptly controlled I/O port and data I/O port, the I/O port address is to be determined by the I/O base register in the configuration space, so can not cause conflict by automatic distribution of computer system; This interface chip is supported the online erasable of rom chip, so data I/O port is a bidirectional port, no matter be after fetching data from data I/O port reads or after data I/O port writes data, the presettable counter of interface chip inside is all counted once automatically, to point to the address of next data; The data bus of this interface chip inside is 32 bit widths, so single job just can be preset start address, presets and need on 8 bit data bus 16 bit address be divided into twice.

Expansion ROM with the 64KB capacity of hard disk reduction card is an example, its initialization module is fairly simple, the INT19H that mainly is intercepting system interrupts, and makes that expansion ROM can regain control before computer guiding operating system, so that display and operation interface and carry out other preliminary work.By existing processing mode; computer system always copies to all data of this expansion ROM in the limited UMB; take UMB 62KB to 64KB (initialization module can initiatively be discharged); expansion ROM is tackled INT19H by initialization module; and before computer guiding operating system, obtain control; because the core image of this moment is write-protected, so the core image of expansion ROM will be copied in the conventional memory display and operation interface and carry out other preliminary work again.And use method of the present invention, the extension blocks that expansion ROM is divided into fundamental block and the 62KB of 2KB, as long as duplicate less fundamental block in UMB before the initialization, take UMB 2KB, expansion ROM is tackled INT19H by initialization module, and before computer guiding operating system, obtain control, by the I/O port data in the expansion ROM are copied in the conventional memory then, again display and operation interface and carry out other preliminary work.With regard to this example, method of the present invention does not have influence on the original function of hard disk reduction card, but reduced taking to UMB, making that hard disk reduction is stuck on the PC of some expansion ROM that can't directly use 64KB and above capacity also can operate as normal, in fact, because saved the data reproduction process of core image, so also improved travelling speed to conventional memory.An example of above-mentioned just practical application of the present invention is not limited to above-mentioned example but implement the present invention, after the overall technological scheme pointed with reference to the present invention, on concrete the enforcement local adjustment or variation can be arranged.

Claims (10)

1, based on a kind of expansion method of the expansion ROM of pci bus, it is characterized in that:

The rom chip of expansion ROM is divided into fundamental block and extension blocks on space layout;

Fundamental block is mapped in the storage space of computer system;

Extension blocks is mapped to one group of I/O port that is used for expansion ROM of the input/output space of computer system.

2, expansion method according to claim 1 is characterized in that: have in the fundamental block in the rom chip of expansion ROM of a standard the feature and the content that must have.

3, expansion method according to claim 2 is characterized in that: have the header section and the initialization module of expansion ROM in the fundamental block, the ROM capacity indication byte in the header section is only indicated the size of fundamental block and is not comprised extension blocks.

4, expansion method according to claim 1 is characterized in that: fundamental block can be detected and initialization by computer system by the processing mode of existing expansion ROM, and the detected expansion ROM of computer system only comprises fundamental block.

5, expansion method according to claim 1 is characterized in that: the I/O end that is used for expansion ROM comprises a control port and a data port.

6, expansion method according to claim 5, it is characterized in that: the step of data comprises the following sequence of operation in the access extension blocks, at first insert the start address of data block in rom chip of the access of wanting to control port, then by data of FPDP access, promptly be in the data of start address position, be in the data of the next address of start address if desired, just once more by data of FPDP access, up to finishing desired data block by the FPDP access.

7, according to claim 1 or 6 described expansion methods, it is characterized in that: the characteristic that fundamental block has extension blocks simultaneously and had, promptly the mapping mode of extension blocks and/or data acess method/step are applicable to whole rom chip.

8, support a kind of pci bus interface chip of expansion ROM, it is characterized in that:

The pci bus interface chip internal has expansion ROM base register and comparer, I/O base register and comparer, address bus, data bus, presettable counter, logic sum gate, data selector;

Expansion ROM base register and comparer are used for determining an expansion ROM space, I/O base register and comparer are used for determining one group of I/O port, comprise a control port and a data port, presettable counter be used to preset start address and after the intact data of access automatically with address increment, logic sum gate is used to make the external ROM chip can accept access requirement from storage space, can accept access requirement again from input/output space, data selector is used for when the storage space access selecting from the access address as the external ROM chip, the address of address bus, and selects when the input/output space access from the count value of the presettable counter access address as the external ROM chip;

The access control signal in expansion ROM space and the access control signal of FPDP are delivered to two input ends of logic sum gate respectively, logic sum gate output is used for the access control signal of external ROM chip, the write control signal of control port is delivered to the control input end of presetting of presettable counter, the count pulse input end that signal is delivered to presettable counter is finished in the access of FPDP, the initialize data input end of presettable counter is connected to data bus, the count value output data of presettable counter is delivered to a data input end of data selector, another data input pin of data selector is connected to address bus, and data selector output is used for the access address signal of external ROM chip.

9, pci bus interface chip according to claim 8 is characterized in that: from the intact data of FPDP access, presettable counter is just counted once at every turn, and the count value increment is to point to the address of next data.

10, pci bus interface chip according to claim 8 is characterized in that:

The external ROM chip that the pci bus interface chip is connected is divided into fundamental block and extension blocks on space layout;

The pci bus interface chip is mapped to the fundamental block of external ROM chip in the storage space of computer system, whole rom chip or its extension blocks is mapped to one group of I/O port that is used for expansion ROM of the input/output space of computer system;

Just, for with pci bus interface chip and external ROM chip serving as the main expansion ROM that constitutes, computer system can only access from storage space to the fundamental block of external ROM chip, carry out access and the extension blocks of external ROM chip must be used for the I/O port of expansion ROM from a group of input/output space.

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