CN1437242A

CN1437242A - Isolator forming process

Info

Publication number: CN1437242A
Application number: CN 02103509
Authority: CN
Inventors: 林俊杰; 史望澄
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2002-02-05
Filing date: 2002-02-05
Publication date: 2003-08-20
Anticipated expiration: 2022-02-05
Also published as: CN1191620C

Abstract

The process to forming isolator on SiGe substrate with strained Si layer includes the steps of: providing one semiconductor SiGe substrate and forming on the substrate one first cushion layer and one hard mask layer; microphotographing and etching the substrate to form several channels; forming the second cushion layer inside the channels and depositing deposit layer to fill the channels; removing successively the hard mask layer and the first cushion layer to expose the surface of the semiconductor substrate; and finally forming strained Si layer on the exposed semiconductor substrate. The present invention can avoid the breakdown of bonding in the strained Si layer and the SiGe substrate and the diffusion of Ge atom to the strained Si layer and raise the quality of the semiconductor substrate.

Description

Form the method for spacer assembly

Technical field

The invention relates to a kind of manufacture of semiconductor, particularly relevant for a kind of method that in SiGe (SiGe) substrate, forms spacer assembly with distortion silicon (strained-Si) layer.

Background technology

Compared to traditional silicon base, there is a kind of substrate can improve the carrier mobility of metal-oxide half field effect transistor (MOSFET) channel recently, just provide a kind of compound substrate, be formed with a distortion silicon layer in this substrate.This through stressed and distortion silicon (strained-Si) that make lattice deformability elongate with the size of the lattice that cooperates SiGe is long brilliant on silicon-Germanium base by being lower than under 750 degree Celsius, making has a thin distortion silicon layer on the silicon-Germanium base.On the surperficial channel (surface-channel) of metal-oxide half field effect transistor, can see the situation that has electric hole and electric current to improve with distortion silicon layer, electronics translational speed at the stressed distortion silicon that makes lattice deformability and elongate is very fast, so have transfer rate faster, and then the usefulness of device improved.

It is very responsive to temperature that yet this kind has the metal-oxide half field effect transistor of distortion silicon layer, because expose the bond scission of link that at high temperature can make between distortion silicon and silicon-Germanium base, and makes distortion silicon recover the lattice size of silicon originally.

Utilizing regional oxidizing process (LOCOS) and shallow trench isolation method (STI) to form separator on the semiconductor-based end, is a kind of technology commonly used on the semiconductor-based end.Please refer to Fig. 1 (a)-Fig. 1 (d), Fig. 1 (a)-Tu (d) is the known silicon-Germanium base 13 with distortion silicon, shown in Fig. 1 (a), and label 11 expressions one silicon-Germanium base; Then, shown in Fig. 1 (b), on silicon-Germanium base 11, be formed with a thin distortion silicon layer 12; Then, shown in Fig. 1 (c), little shadow and etch groove 14 in this substrate 13; At last, shown in Fig. 1 (d), in groove 14, insert oxide with as shallow groove isolation layer 15, and carry out short annealing and handle that (rapid thermalannealing is RTA) with oxide densification.

The method of inserting oxide is to form one deck protection oxide layer (liner oxide) earlier on groove 14; (high densityplasma chemical vapord eposition, mode HDPCVD) is inserted oxide to form shallow groove isolation layer 15 with high density plasma enhanced chemical vapor deposition again.All can use high temperature in the process that formation pad oxide and short annealing are handled, wherein, the temperature that forms pad oxide is between 1000 degree Celsius are spent to 1100, and the temperature of short annealing processing is greatly about about 1000 degree Celsius.

Such high temperature can allow the bond scission of link of 11 of distortion silicon layer 12 and silicon-Germanium base, the lattice that makes distortion silicon 12 be elongated recovers the shape of silicon crystal lattice originally, so that the phenomenon that distortion silicon layer 12 produces the crack or peels off, thus, the effectiveness of this substrate 13 is then identical with silicon-Germanium base 11 originally, is to be out of shape nonsensical that the action of silicon 12 then can become with the silicon crystal lattice elongation in advance.Simultaneously, the germanium atom in the silicon-Germanium base 11 (Ge) can diffuse to the distortion silicon layer 12 in and pollute, influence the quality of substrate 13.

Summary of the invention

In view of this, the object of the present invention is to provide a kind of method that on silicon-Germanium base, forms shallow groove isolation layer with distortion silicon layer, it can not influence because of high temperature, and germanium atom can not diffuse to the distortion silicon layer, so form the high-quality silicon-Germanium base with distortion silicon layer.

According to above-mentioned purpose, the invention provides the method for a manufacturing spacer assembly, comprise the following steps: to provide the semiconductor substrate, form one first bed course and curtain layer of hard hood in regular turn in semiconductor-based basal surface; Lithography is formed with the semiconductor-based end of first bed course and curtain layer of hard hood to form plural groove; Form one second bed course at plural trench wall; Deposit a separator to fill up groove; Remove the curtain layer of hard hood and first bed course in regular turn, to reveal this semiconductor-based basal surface; And silicon layer is out of shape in formation on the semiconductor-based end of exposing.

The effect brought of the present invention is thus: can effectively avoid being out of shape bond scission of link between silicon and the silicon-Germanium base, and germanium atom diffuses in the distortion silicon layer, and then reach the purpose that promotes quality of the semiconductor-based end.

Description of drawings

Fig. 1 (a)-Fig. 1 (d) is the known silicon-Germanium base profile with distortion silicon;

Fig. 2 (a)-Fig. 2 (g) is the known silicon-Germanium base profile with distortion silicon.

The figure number explanation:

The 11-silicon-Germanium base; 12-is out of shape silicon layer;

The 13-substrate; The 14-groove;

The 15-shallow groove isolation layer; The 21-silicon-Germanium base;

22-first bed course; The 23-silicon nitride layer;

The 24-trench wall; 25-second bed course;

The 26-shallow groove isolation layer; The 27-groove;

28-is out of shape silicon layer.

Embodiment

Below be embodiments of the invention, more cooperate Fig. 2 a to Fig. 2 g explanation embodiments of the invention flow chart.

Please refer to Fig. 2 (a) and Fig. 2 (b), Fig. 2 (a) is a silicon-Germanium base 21, earlier thin first bed course 22, for example oxide layer of deposition one deck on silicon-Germanium base 21.

Please refer to Fig. 2 (b), then on first bed course 22, form curtain layer of hard hood 23, for example a silicon nitride layer.The effect of first bed course 22 is to make curtain layer of hard hood 23 more easily attached on the silicon-Germanium base 21, and curtain layer of hard hood 23 then is to use as etch stop layer when follow-up grinding steps.

Please refer to Fig. 2 (c), little shadow and etching are formed with the silicon-Germanium base 21 of first bed course 22 and curtain layer of hard hood 23 to form groove 24.

Please refer to Fig. 2 (d), deposition one second bed course 25 on groove 24, oxide layer for example, second bed course 25 when next step carries out high density plasma enhanced chemical vapor deposition (HDPCVD) as protective layer, because the energy of HDPCVD is higher, second bed course can prevent that when carrying out HDPCVD ion bombardment (ion bombardment) effect damages silicon-Germanium base 21; And the blemish that is become can repair etched trench the time.

Please refer to Fig. 2 (e), groove 24 that deposits second bed course 25 and the silicon-Germanium base 21 that is formed with curtain layer of hard hood 23 are carried out HDPCVD to form shallow groove isolation layer 26, for example oxide layer.And because HDPCVD can deposit and be higher than curtain layer of hard hood 23 surfaces, therefore grind in the mode of cmp (CMP), the curtain layer of hard hood 23 that is ground to as etch stop layer promptly stops, and so can form a flat surfaces on silicon-Germanium base 21.

Please refer to the 2nd (f) figure, mode with wet etching is removed the curtain layer of hard hood on the silicon-Germanium base 21 23, then also first bed course 22 on the silicon-Germanium base 21 is removed, therefore on silicon-Germanium base 21, form groove 27, and on silicon-Germanium base 21, stay shallow groove isolation layer 26.

Please refer to the 2nd (g) figure, silicon-Germanium base 21 is carried out selectivity building crystal to grow (selective epitaxial growth, SEG), so can form distortion silicon layer 28, so promptly finish the structure of the shallow groove isolation layer 26 of silicon-Germanium base 21 with distortion silicon layer 28 at groove 27.

The structure that the present invention forms is identical with the structure of the shallow groove isolation layer 15 of the silicon-Germanium base 11 with distortion silicon layer 12 of known manufacturing, difference is that the present invention forms groove 24 in advance on silicon-Germanium base 21, deposition one deck bed course 25 is as protective layer in groove 24, then deposited oxide layer is with as shallow groove isolation layer 26 the groove 24 that is formed with bed course 25 in, and the last silicon 28 that just will be out of shape is formed on the surface of exposing silicon-Germanium base 21 in the mode of selectivity building crystal to grow; And the step of known manufacturing shallow groove isolation layer 15 is to form distortion silicon layer 12 earlier on silicon-Germanium base 11; follow little shadow and etching silicon-Germanium base 11 to form groove 14; in groove 14, form a bed course (not shown) as protective layer, then in groove 14 deposited oxide layer with as shallow groove isolation layer 15.The present invention carries out in last one step forming distortion silicon layer 28 on the silicon-Germanium base 21; thus; in groove 24, form protective layer, isolating oxide layer in regular turn and carry out in the process of densification; high temperature will can not exert an influence to distortion silicon layer 28; can effectively avoid being out of shape the bond scission of link of silicon layer 28 and silicon-Germanium base 21; and germanium atom diffuses in the distortion silicon layer 28, and then reaches the purpose that promotes quality of the semiconductor-based end.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting scope of the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that the claim scope defined.

Claims

1. a method that forms spacer assembly comprises the following steps:

The semiconductor substrate is provided;

Form one first bed course and curtain layer of hard hood in regular turn in this semiconductor-based basal surface;

Lithography is formed with this semiconductor-based end of this first bed course and this curtain layer of hard hood to form plural groove;

Form one second bed course at these plural trench walls;

Deposit a sedimentary deposit to fill up this groove;

Remove this curtain layer of hard hood and this first bed course in regular turn, to expose this semiconductor-based basal surface; And

On this semiconductor-based end of exposing, form the distortion silicon layer.

2. a kind of method that forms spacer assembly according to claim 1 is characterized in that: deposit this sedimentary deposit to fill up the step that more comprises a flattening surface behind this groove.

3. a kind of method that forms spacer assembly according to claim 1 is characterized in that: this semiconductor-based end is a silicon-Germanium base.

4. a kind of method that forms spacer assembly according to claim 1 is characterized in that: this first bed course is an oxide layer.

5. a kind of method that forms spacer assembly according to claim 1 is characterized in that: this curtain layer of hard hood is a silicon nitride layer.

6. a kind of method that forms spacer assembly according to claim 1 is characterized in that: this second bed course is an oxide layer.

7. a kind of method that forms spacer assembly according to claim 1 is characterized in that: this sedimentary deposit is a high density plasma enhanced chemical vapor deposition oxide layer.

8. a kind of method that forms spacer assembly according to claim 1 is characterized in that: the method that forms distortion silicon on this semiconductor-based end of exposing is the method for selectivity building crystal to grow.