CN1435879A - Method for mfg. non-volatile internal memory - Google Patents
Method for mfg. non-volatile internal memory Download PDFInfo
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- CN1435879A CN1435879A CN 02102849 CN02102849A CN1435879A CN 1435879 A CN1435879 A CN 1435879A CN 02102849 CN02102849 CN 02102849 CN 02102849 A CN02102849 A CN 02102849A CN 1435879 A CN1435879 A CN 1435879A
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Abstract
A process for preparing non-volatile memory includes providing a substrate having a long-strip stack structure on it, generating an embedded drain in the substrate at both sides of said stack structure, generating an insulating layer on the embedded drain, sequentially generating a Si layer and a top cover layer, vertically patterning said top cover layer, Si layer and stack structure to form several gate structures, generating a liner layer on the exposed Si layer, gate structure and substrate, removing top cover layer, and generating metallic silicide layer on the exposed silicon layer.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor device, and particularly relevant for a kind of non-voltile memory (Non-volatile Memory, manufacture method NVM).
Technical background
Because the data that non-voltile memory deposited in can't disappear because of the interruption of power supply supply, so its application is very extensive.There are two kinds to have similar structure in the non-voltile memory, are respectively mask-type ROM (Mask ROM) and silicon nitride ROM (NitrideROM).
Figure 1A to Fig. 1 D illustrate is the manufacturing process generalized section of known a kind of non-voltile memory.
Please refer to Figure 1A, the method for known formation non-voltile memory at first provides a substrate 100.Then, in substrate 100, form the stack architecture 101 of a strip.Wherein, strip stack architecture 101 is made of the cap layer 105 and a gate oxide 102 (or electric charge capture layer 102) of a polysilicon layer 104, a silicon nitride material.Then, in strip stack architecture 101 substrate on two sides 100, form flush type drain electrode 106.
Afterwards, please refer to Figure 1B, in substrate 100, form an insulating barrier 108, cover the stack architecture 101 of strip.
Then, please refer to Fig. 1 C, etch-back insulating barrier 108, and the cap layer 105 of removal silicon nitride material.So that insulating barrier 108 only covers flush type drain electrode 106.
Then, please refer to Fig. 1 D, above substrate 100, form a conductive layer 110, cover polysilicon layer 104 and insulating barrier 108.With the direction perpendicular to flush type drain electrode 106, patterned conductive layer 110, polysilicon 104 and gate oxide 102 (or electric charge capture layer 102) are with grid structure (not illustrating) and the word line that forms several islands afterwards.Wherein several island grid structures of same row and same word line electrically connect.
Wherein, the known conductive layer 110 that is used for forming word line, its material is tungsten silicide (WSi
x).Yet the manufacture craft temperature that forms tungsten silicide is often up to more than 1000 degree Celsius.And under the manufacture craft condition of such high temperature, will limit the design of device channel length, this kind situation is very disadvantageous for the making of short channel read-only memory.In addition, because the resistance value of tungsten silicide material itself is higher, so known, will impact for the service speed of device with the material of tungsten silicide as word line.
Summary of the invention
Therefore, purpose of the present invention is exactly that a kind of manufacture method of non-voltile memory is being provided, to avoid having limited because of the high temperature of hot manufacture craft in the known method length of device channel.
Another object of the present invention provides a kind of manufacture method of non-voltile memory, and is higher because of resistance value to avoid in the known method employed tungsten silicide, and influenced the service speed of device.
The present invention proposes a kind of manufacture method of silicon nitride ROM, and the method at first provides a substrate, wherein has been formed with the stack architecture of a strip in the substrate, and this strip stack architecture is made of a conductive layer and an electric charge capture layer.And this electric charge capture layer can be silicon monoxide-silicon-nitride and silicon oxide (ONO) stack architecture, one silicon nitride-silicon nitride-silicon nitride (NNN) stack architecture with or one silicon nitride-silicon-nitride and silicon oxide (NNO) stack architecture.Then, in this strip stack architecture substrate on two sides, form flush type drain electrode with ionic-implantation.And, in the flush type drain electrode, form an insulating barrier.Afterwards, in substrate, form a polysilicon layer and a cap layer in regular turn.And with stack architecture, to form several grid structures perpendicular to directional patterns cap layer, polysilicon layer and the strip of flush type drain electrode.Then, on the surface of the silicon layer that is not covered, grid structure and substrate, form the silicon monoxide lining with thermal oxidation method by cap layer.Afterwards, remove cap layer.And above substrate, after the deposition layer of metal layer, carry out a tempering manufacture craft, form a metal silicide layer so that metal level and polysilicon layer react.At last, the unreacted metal layer is removed.Wherein, this metal silicide layer only is formed on the polysilicon layer surface that not oxidized silicon lining covers, and it is as the word line that several grid structures are electrically connected.And when formed metal silicide was titanium silicide, the required temperature of its tempering manufacture craft was that 600 degree Celsius are to 800 degree Celsius.When formed metal silicide was cobalt silicide, the required temperature of its tempering manufacture craft was that 600 degree Celsius are to 700 degree Celsius.
The present invention proposes a kind of manufacture method of mask-type ROM, and the method at first provides a substrate, wherein has been formed with the stack architecture of a strip in the substrate, and the stack architecture of this strip is made of a grid conducting layer and a gate dielectric layer.Then, in the stack architecture substrate on two sides of strip, form flush type drain electrode with ionic-implantation.In the flush type drain electrode, form an insulating barrier again.Afterwards, in substrate, form a polysilicon layer and a cap layer in regular turn.And with stack architecture, to form several grid structures perpendicular to directional patterns cap layer, polysilicon layer and the strip of flush type drain electrode.Then, on the surface of the silicon layer that is not covered, grid structure and substrate, form the silicon monoxide lining with thermal oxidation method by cap layer.Afterwards, remove cap layer.And above substrate, after the deposition layer of metal layer, carry out a tempering manufacture craft, form a metal silicide layer so that metal level and polysilicon layer react.Then, the unreacted metal layer is removed.Wherein, this metal silicide layer only is formed on the polysilicon layer surface that not oxidized silicon lining covers, and it is as the word line that several grid structures are electrically connected.And formed metal silicide is when being titanium silicide, and the required temperature of its tempering manufacture craft is that 600 degree Celsius are to 800 degree Celsius.When formed metal silicide was cobalt silicide, the required temperature of its tempering manufacture craft was that 600 degree Celsius are to 700 degree Celsius.
The manufacture method of non-voltile memory of the present invention because its manufacture craft temperature that forms metal silicide layer (word line) is low than known method, therefore, can reduce the heat budget of manufacture craft, so will help the making of short channel non-voltile memory.
The manufacture method of non-voltile memory of the present invention is because it is used as the resistance value of the metal silicide layer of word line material, low than the resistance value of the word line in the known method.Therefore, can improve the service speed of device.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborate.
Description of drawings
Figure 1A to Fig. 1 D is the manufacturing process generalized section of known a kind of non-voltile memory.
Fig. 2 A to Fig. 2 L is the manufacturing process schematic diagram according to the non-voltile memory of a preferred embodiment of the present invention.Label declaration:
100,200: substrate 101,207: the stack architecture of strip
102,202: dielectric layer (gate oxide or electric charge capture layer)
104,204: polysilicon layer (grid conducting layer)
105,206: silicon nitride layer 106,214: the flush type drain electrode
108,216: insulating barrier 110: conductive layer
204a: the grid structure 208,222 of island: photoresist layer
209,224: lining 210: the ion implantation step
212: pouch-type ion implantation step
218: silicon layer 220: cap layer
226: metal level 226a: metal silicide layer
Embodiment
Fig. 2 A to Fig. 2 L, it illustrates and is the manufacture method according to the non-voltile memory of a preferred embodiment of the present invention.
Please refer to Fig. 2 A, the method for formation non-voltile memory of the present invention at first provides a substrate 200.Then, in substrate 200, form a dielectric layer 202, a grid conducting layer 204, a silicon nitride layer 206 and a patterned light blockage layer 208 in regular turn.Wherein, the material of grid conducting layer 204 for example is a polysilicon.And be example with the mask-type ROM, dielectric layer 202 is a gate oxide.With the silicon nitride ROM is example, dielectric layer 202 is an electric charge capture layer, and its material for example is the three-layer-material layer of silica-silicon-nitride and silicon oxide (ONO), the three-layer-material layer of silicon nitride-silicon nitride-silicon nitride (NNN) or the three-layer-material layer of silicon nitride-silicon-nitride and silicon oxide (NNO).
Afterwards, asking the while with reference to Fig. 2 B and Fig. 2 C, is etch mask with photoresist layer 208, and patterned sin layer 206, grid conducting layer 204 and dielectric layer 202 are with the stack architecture 207 that forms several strips.Its top view is shown in Fig. 2 B.Afterwards, please refer to Fig. 2 C (Fig. 2 C is the generalized section of Fig. 2 B by I-I '), form a lining 209 with surface with grid conducting layer 204 at the substrate 200 that is not covered, dielectric layer 202 by silicon nitride layer 206.The method that wherein forms lining 209 is for example for to form an oxide layer with thermal oxidation method.
Then, please refer to Fig. 2 D, carry out an ion implantation step 210 and a pouch-type ion implantation step (Pocket implanting) 212, to form flush type drain electrode 214 and pouch-type doped region (not illustrating) in strip stack architecture 207 substrate on two sides 200, wherein flush type drain electrode 214 for example is the doped region that is mixed with N type ion.
Because before forming flush type drain electrode 214, be formed with lining 209 on the surface of the grid conducting layer 204, dielectric layer 202 and the substrate 200 that expose earlier, therefore, just can not damage the surface of grid conducting layer 204, dielectric layer 202 and substrate 200 at ion implantation step 210 that forms flush type drain electrode 214 and pouch-type ion implantation step 212.
Then, please refer to Fig. 2 E, in substrate 200, form an insulating barrier 216, cover the stack architecture 207 and the lining 209 of strip.Wherein, the method for formation insulating barrier 216 for example is a chemical vapour deposition technique.And the material of insulating barrier 216 for example is tetraethyl orthosilicate (Tetraethyl-ortho-silicate, TEOS) silica (TEOS-Oxide).
Afterwards, please refer to Fig. 2 F, planarization insulating layer 216 is so that silicon nitride layer 206 comes out.Afterwards, remove silicon nitride layer 206 again, so that insulating barrier 216 only covers the top of flush type drain electrode 214.Wherein, the method for planarization insulating layer 216 for example is an etch-back manufacture craft or a chemical mechanical milling method.
Then, please refer to Fig. 2 G, above substrate 200, form a silicon layer 218 and a cap layer 220 in regular turn, cover insulating barrier 216 and grid conducting layer 204.Wherein, the material of silicon layer 218 for example is a polysilicon.The material of cap layer 220 for example is a silicon nitride.
Then, please on cap layer 220, form a patterned light blockage layer 222 simultaneously with reference to Fig. 2 H and Fig. 2 I.Wherein the pattern of this photoresist layer 222 is that its top view is shown in Fig. 2 H perpendicular to several strip patterns of the direction of flush type drain electrode 214 (grid conducting layers 204).
Afterwards, please refer to Fig. 2 J, it is by the generalized section of II-II ' among Fig. 2 H.With photoresist layer 222 is etch mask, patterning cap layer 220, silicon layer 218 with grid conducting layer 204, to form several grid structures 204a.Afterwards, photoresist layer 222 is removed, on the surface of the silicon layer 218 that exposes, grid structure 204a and substrate 200, formed a lining 224 again.The method that wherein forms lining 224 for example is the oxide layer with thermal oxidation method formation.Owing to be coated with cap layer 220 on the silicon layer 218 of grid structure 204a top.Therefore, this lining 224 only can be formed on the surface of the silicon layer 218, grid structure 204a and the substrate 200 that are not covered by cap layer 220.
Then, please refer to Fig. 2 K, remove cap layer 220.Afterwards, above substrate 200, form a metal level 226, cover lining 224 with grid structure 204a on silicon layer 218.Wherein, the material of metal level 226 for example is Titanium or metallic cobalt.
Then, please refer to Fig. 2 L, carry out a tempering manufacture craft, so that metal level 226 and silicon layer 218 reactions, and form metal silicide layer 226a.Afterwards, will not remove with the metal level 226 of silicon layer 218 reaction.Wherein, metal silication silicon layer 226a for example is a titanium silicide layer or a silicon cobalt substrate.When being the material of metal level 226 with the Titanium, the temperature of its tempering manufacture craft for example is that 600 degree Celsius are to 800 degree Celsius.When being the material of metal level 226 with the metallic cobalt, the temperature of its tempering manufacture craft for example is that 600 degree Celsius are to 700 degree Celsius.And formed metal silicide layer 226a is as the word line that several grid structures 204a is electrically connected.
In the process of carrying out the tempering manufacture craft, owing to be coated with lining 224 on the surface of substrate 200 and grid structure 204a both sides.Therefore, metal silicide layer 226a can not be formed at this, and only is formed on the part that is coated with silicon layer 218 above the grid structure 204a.
In the above-mentioned formation mask-type ROM and the method for silicon nitride ROM, the employed material of its word line is titanium silicide or cobalt silicide, and returns the manufacture craft temperature of manufacture craft far below known formation tungsten silicide owing to form the fire of titanium silicide or cobalt silicide.Therefore, for the non-volatile memory device advantageous particularly that forms short channel.In addition, because the resistance value of titanium silicide and cobalt silicide is less than the resistance value of tungsten silicide, therefore, the present invention can improve the service speed of device with titanium silicide or the cobalt silicide material as word line.
Comprehensive the above, the present invention has following advantage:
1, the manufacture method of non-voltile memory of the present invention because its manufacture craft temperature that forms metal silicide layer (word line) is low than known method, therefore, can reduce the heat budget of manufacture craft, so will help the making of short channel non-voltile memory.
2, the manufacture method of non-voltile memory of the present invention is because it is used as the resistance value of the metal silicide of word line material, low than the resistance value of the word line in the known method.Therefore, can improve the service speed of device.
Though the present invention is open with preferred embodiment; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention claim after looking defines and is as the criterion.
Claims (20)
1, a kind of manufacture method of silicon nitride ROM is characterized in that: comprise the following steps: at least
One substrate is provided, has been formed with the stack architecture of a strip in this substrate, wherein the stack architecture of this strip is made of a grid conducting layer and a dielectric layer;
In this substrate of the stack architecture both sides of this strip, form flush type drain electrode;
In this flush type drain electrode, form an insulating barrier;
Above this substrate, form a silicon layer and a cap layer in regular turn, cover stack architecture and this insulating barrier of this strip;
With this cap layer of directional patternsization, this silicon layer and this strip stack architecture, to form several grid structures perpendicular to this flush type drain electrode;
Surface in this silicon layer, those grid structures and this substrate that expose forms a lining;
Remove this cap layer;
Form a metal silicide layer on the surface of this silicon layer.
2, a kind of manufacture method of non-voltile memory is characterized in that: comprise the following steps: at least
One substrate is provided, has been formed with the stack architecture of a strip in this substrate, wherein the stack architecture of this strip is made of a grid conducting layer and an electric charge capture layer;
In this substrate of the stack architecture both sides of this strip, form flush type drain electrode;
In this flush type drain electrode, form an insulating barrier;
Above this substrate, form a silicon layer and a cap layer in regular turn, cover stack architecture and this insulating barrier of this strip;
With stack architecture, to form several grid structures perpendicular to this cap layer of directional patternsization, this silicon layer and this strip of the drain electrode of this flush type;
Surface in this silicon layer, those grid structures and this substrate that expose forms a lining;
Remove this cap layer;
Form a metal silicide layer on the surface of this silicon layer.
3, the manufacture method of non-voltile memory as claimed in claim 2 is characterized in that: wherein this metal silicide layer comprises a titanium silicide layer.
4, the manufacture method of non-voltile memory as claimed in claim 3 is characterized in that: the temperature that wherein forms this titanium silicide layer is between 600 degree Celsius are spent to Celsius 800.
5, the manufacture method of non-voltile memory as claimed in claim 2 is characterized in that: wherein this metal silicide layer comprises a silicon cobalt substrate.
6, the manufacture method of non-voltile memory as claimed in claim 5 is characterized in that: the temperature that wherein forms this silicon cobalt substrate is between 600 degree Celsius are spent to Celsius 700.
7, the manufacture method of non-voltile memory as claimed in claim 2 is characterized in that: wherein this electric charge capture layer be selected from silicon monoxide-silicon-nitride and silicon oxide (ONO) stack architecture, one silicon nitride-silicon nitride-silicon nitride (NNN) stack architecture and one silicon nitride-silicon-nitride and silicon oxide (NNO) stack architecture one of them.
8, the manufacture method of non-voltile memory as claimed in claim 2 is characterized in that: wherein the material of this lining comprises silica.
9, the manufacture method of non-voltile memory as claimed in claim 2 is characterized in that: wherein the material of this silicon layer comprises polysilicon.
10, the manufacture method of non-voltile memory as claimed in claim 2 is characterized in that: wherein the material of this insulating barrier comprises tetraethyl orthosilicate silica (TEOS-Oxide).
11, the manufacture method of non-voltile memory as claimed in claim 2 is characterized in that: wherein the material of this cap layer comprises silicon nitride.
12, a kind of manufacture method of read-only memory is characterized in that: comprise the following steps: at least
One substrate is provided, has been formed with the stack architecture of a strip in this substrate, wherein the stack architecture of this strip is made of a grid conducting layer and a gate dielectric layer;
In this substrate of the stack architecture both sides of this strip, form flush type drain electrode;
In this flush type drain electrode, form an insulating barrier;
Above this substrate, form a silicon layer and a cap layer in regular turn, cover stack architecture and this insulating barrier of this strip;
With this cap layer of directional patternsization, this silicon layer and this strip stack architecture, to form several grid structures perpendicular to this flush type drain electrode;
Surface in this silicon layer, those grid structures and this substrate that expose forms a lining;
Remove this cap layer;
Form a metal silicide layer on the surface of this silicon layer.
13, the manufacture method of read-only memory as claimed in claim 12 is characterized in that: wherein this metal silicide layer comprises a titanium silicide layer.
14, the manufacture method of read-only memory as claimed in claim 13 is characterized in that: the temperature that wherein forms this titanium silicide layer is between 600 degree Celsius are spent to Celsius 800.
15, the manufacture method of read-only memory as claimed in claim 12 is characterized in that: wherein this metal silicide layer comprises a silicon cobalt substrate.
16, the manufacture method of read-only memory as claimed in claim 15 is characterized in that: the temperature that wherein forms this silicon cobalt substrate is between 600 degree Celsius are spent to Celsius 700.
17, the manufacture method of read-only memory as claimed in claim 12 is characterized in that: wherein the material of this lining comprises silica.
18, the manufacture method of read-only memory as claimed in claim 12 is characterized in that: wherein the material of this silicon layer comprises polysilicon.
19, the manufacture method of read-only memory as claimed in claim 12 is characterized in that: wherein the material of this insulating barrier comprises tetraethyl orthosilicate silica (TEOS-Oxide).
20, the manufacture method of read-only memory as claimed in claim 12 is characterized in that: wherein the material of this cap layer comprises silicon nitride.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021028494A CN1316601C (en) | 2002-01-28 | 2002-01-28 | Method for mfg. non-volatile internal memory |
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|---|---|---|---|
| CNB021028494A CN1316601C (en) | 2002-01-28 | 2002-01-28 | Method for mfg. non-volatile internal memory |
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| CN1435879A true CN1435879A (en) | 2003-08-13 |
| CN1316601C CN1316601C (en) | 2007-05-16 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296987C (en) * | 2003-09-23 | 2007-01-24 | 茂德科技股份有限公司 | Mfg method of contact hole and mfg method of semiconductor element |
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| JP3869089B2 (en) * | 1996-11-14 | 2007-01-17 | 株式会社日立製作所 | Manufacturing method of semiconductor integrated circuit device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296987C (en) * | 2003-09-23 | 2007-01-24 | 茂德科技股份有限公司 | Mfg method of contact hole and mfg method of semiconductor element |
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| CN1316601C (en) | 2007-05-16 |
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