CN1434513A - Programmable gate array based on transistor grid oxidation layr breakdown property - Google Patents

Programmable gate array based on transistor grid oxidation layr breakdown property Download PDF

Info

Publication number
CN1434513A
CN1434513A CN 03117373 CN03117373A CN1434513A CN 1434513 A CN1434513 A CN 1434513A CN 03117373 CN03117373 CN 03117373 CN 03117373 A CN03117373 A CN 03117373A CN 1434513 A CN1434513 A CN 1434513A
Authority
CN
China
Prior art keywords
mentioned
fpga
terminal
grid
gate array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN 03117373
Other languages
Chinese (zh)
Other versions
CN1267995C (en
Inventor
彭泽忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to CN 03117373 priority Critical patent/CN1267995C/en
Publication of CN1434513A publication Critical patent/CN1434513A/en
Application granted granted Critical
Publication of CN1267995C publication Critical patent/CN1267995C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

This invention discloses a FPGA unit suitable for FFGA array including a column position line, a read position line and line character line containing a condenser a selection transistor and a switch, in which the said condenser has two ends, one end connects to the column position line, the other lines to a switch control nexus and dielectric substance in between. The above mentioned selection transistor includes a source, a grid and drain in which the grid connects to the read position line, the source links to the switch control nexus and the drain to the line, the above switch is controlled by the nexus.

Description

Programmable gate array based on gate oxide transistor layer breakdown characteristics
Technical field
Content of the present invention is programmable gate array (FPGA), and a kind of FPGA that punctures based on the gate oxide transistor layer more specifically says so.
Background technology
FPGA is just increasing as the application of the treatment element of logical AND/logic OR.One type FPGA utilizes static memory (SRAM) unit, and it needs six transistors.This has just determined it that very big cell size and low storage density are arranged, and is volatile based on the FPGA of static memory (SRAM).
The FPGA of another kind of type is based on anti-fuse (anti-fuse) technology.Though it is accepted widely, anti-fuse technique needs special fuse technology.In addition, the FPGA based on anti-fuse technique can only carry out one-time programming.
Also have one type FPGA to be based on quickflashing (flash) memory technology.Yet, the semiconductor technology that the flash Technology Need is more complicated comparatively speaking, so cost is very high.
Summary of the invention
The present invention discloses a kind of FPGA structure, the transistor that constitutes it has ultra-thin dielectric, and this dielectric can breakdown (soft breakdown and hard breakdown) thereby the level of leakage current is set.A kind of suitable ultra-thin dielectric is thick about 50 or a thinner high-quality gate oxide in the transistor, and this is that present advanced CMOS (complementary metal oxide semiconductors (CMOS)) logic process is generally available.Usually with the method for deposition, perhaps from the active area oxidation growth of silicon, perhaps comprehensive method forms such oxide layer.Other dielectric that is fit to comprises silica-silicon-nitride and silicon oxide complex media, oxide layer of compound or the like.
Content of the present invention is: a kind of being applicable to has the row bit line, and field programmable gate array (FPGA) unit of the FPGA array of sense bit line and row word line is characterized in that this unit contains:
A capacitor, it has first terminal and second terminal, and first terminal is connected to the row bit line, and second terminal is connected to a switch control node, between above-mentioned first terminal of above-mentioned capacitor and second terminal dielectric layer is arranged;
Select transistor for one, it has grid, a source and a leakage, and above-mentioned grid are connected to above-mentioned sense bit line, and above-mentioned source is connected to above-mentioned switch Control Node, and above-mentioned leakage is connected to a capable word line;
A switch, it is controlled by above-mentioned switch Control Node.
In the content of the present invention: described switch is a mos field effect transistor (MOSFET), and the grid of above-mentioned mos field effect transistor (MOSFET) are connected to above-mentioned switch Control Node.
Described switch and described selection transistor have the gate oxide thicker than the dielectric of above-mentioned capacitor.
In the content of the present invention: above-mentioned first terminal of above-mentioned capacitor, the grid of transistorized above-mentioned grid of above-mentioned selection and above-mentioned switch form with same polysilicon layer.
In the content of the present invention: the first metal layer connects the above-mentioned grid of above-mentioned switch Control Node and above-mentioned switch.
The gate oxide thickness that above-mentioned switch and the transistorized above-mentioned gate oxide thickness of selection are input/output transistors under the CMOS technology.
Another content of the present invention is: the method for a kind of operation site programmable gate array (FPGA), this gate array comprise many capable word lines, many row bit lines, many sense bit lines, and many FPGA unit on the crosspoint of corresponding row word line and row bit line; Above-mentioned FPGA unit comprises a capacitor, a selection transistor and a switch; Above-mentioned capacitor has first terminal and second terminal, and first terminal is connected to a row bit line, and above-mentioned second terminal is connected to a switch Control Node; Between above-mentioned first terminal of above-mentioned capacitor and above-mentioned second terminal is dielectric; Above-mentioned selection transistor has grid, a source and a leakage, and above-mentioned grid are connected to above-mentioned sense bit line, and above-mentioned source is connected to above-mentioned switch Control Node, and above-mentioned leakage is connected to a capable word line; Above-mentioned switch is controlled by above-mentioned switch Control Node; It is characterized in that this method comprises:
Add on first voltage to one selecteed row bit line and the transistorized grid of selecteed above-mentioned selection;
Add on second voltage to the one selecteed capable word line;
Cross over first voltage and second voltage of capacitor dielectric, form an electrical potential difference and puncture above-mentioned dielectric, make above-mentioned capacitor become a resistance device.
In this method: also comprise add the 3rd voltage to the not corresponding capable word line of above-mentioned selecteed selection transistor on.
In this method: above-mentioned selecteed selection transistor is read on above-mentioned selecteed selection transistor and above-mentioned row bit line by adding the 4th voltage.
In this method: also comprise add the 5th voltage to the not corresponding capable word line of above-mentioned selecteed selection transistor on.
Another content of the present invention is: a kind of field programmable gate array (FPGA), this gate array comprise many capable word lines, many row bit lines, many sense bit lines, and many unit on the crosspoint of corresponding row word line and row bit line; It is characterized in that each unit comprises:
The capacitor that first terminal and second terminal are arranged, first terminal is connected to a row bit line, and above-mentioned second terminal is connected to a switch Control Node, is dielectric between above-mentioned first terminal of above-mentioned capacitor and above-mentioned second terminal;
Select transistor for one, it has grid, a source and a leakage, and above-mentioned grid are connected to above-mentioned sense bit line, and above-mentioned source is connected to above-mentioned switch Control Node, and above-mentioned leakage is connected to a capable word line;
A switch is controlled by above-mentioned switch Control Node.
In this field programmable gate array (FPGA): above-mentioned switch is a MOSFET, and the grid of above-mentioned MOSFET are connected to above-mentioned switch Control Node.
In this field programmable gate array (FPGA): above-mentioned switch and above-mentioned selection transistor have the gate oxide thicker than above-mentioned capacitor dielectric.
In this field programmable gate array (FPGA): above-mentioned first terminal of above-mentioned capacitor, the grid of transistorized above-mentioned grid of above-mentioned selection and above-mentioned switch form with same polysilicon layer.
In this field programmable gate array (FPGA): the first metal layer connects the above-mentioned grid of above-mentioned switch Control Node and above-mentioned switch.
In this field programmable gate array (FPGA): the above-mentioned gate oxide of above-mentioned switch and selection transistor are the thickness of the input/output transistors under CMOS (complementary metal oxide semiconductors (CMOS)) technology.
Description of drawings
Fig. 1 adopts the partial circuit schematic diagram of FPGA of the present invention;
The section layout figure of the FPGA that Fig. 2 is shown in Figure 1;
Magnitude of voltage table when the FPGA unit shown in Fig. 3 Fig. 1-3 moves;
Magnitude of voltage table when another FPGA unit example of Fig. 4 moves;
The sectional drawing of a kind of experimental provision of Fig. 5;
Fig. 6 represents the figure of a constant voltage stress to the effect of superthin grid oxide layer;
Fig. 7 is illustrated in the I-E characteristic figure in each stage of superthin grid oxide layer decline;
Fig. 8 on the n-of different oxidated layer thickness ditch field-effect transistor (transoid), the time measured value that the puncture of representing with semilog coordinate 63% distributes and the graph of a relation of grid voltage;
Fig. 9 is at the I-E characteristic that detects the n-type device of measuring after the Continuous Breakdown incident.
Embodiment
Following narration has provided a large amount of details, so that example of the present invention is had a thorough understanding.Yet the people who is familiar with related process will recognize that the present invention just can implement under the situation of neither one or a plurality of details, and method, element, material that perhaps can adopt other etc. just can be implemented.In other cases, covered, to the just no longer detailed description or the graphic extension of structure, material or operating principle of some called optical imaging for fear of some aspect of the present invention.
Concrete characteristics, structure or the characteristic with this example links mutually of " example " mentioned in the whole detailed description or " certain example " expression narration are included in an example of the present invention at least.Therefore, " in an example " or the words such as " in certain examples " of each place appearance in whole detailed description not necessarily refer to same example entirely.And concrete characteristics, structure or characteristic can combine in an example or a plurality of example in any suitable manner.
The present invention relates to the flash memory design based on gate oxide breakdown, the assignee of its inventor and invention is identical with the present invention.Below each document in the lump as with reference to illustration: the U.S. Patent application (sequence number 09/955,641) that submit to September 18 calendar year 2001, autograph " utilizing the semiconductor memory cell and the memory array of ultra-thin dielectric punch-through "; The U.S. Patent application (sequence number 10/024,327) that submit to December 17 calendar year 2001, autograph " utilizing the semiconductor memory cell and the memory array of ultra-thin dielectric punch-through "; The U.S. Patent application (sequence number 09/982,034) that submit to December 17 calendar year 2001, autograph " smart card that has the nonvolatile memory that processes with logic process "; The U.S. Patent application (sequence number 09/982,314) that submit to December 17 calendar year 2001, autograph " with the oxide layer Reprogrammable nonvolatile memory of logic process manufacturing "; U.S. Patent application (the sequence number 10/133 that on April 26th, 2002 submitted to, 604), the Chinese patent application (application number 01129152.4) that autograph " adopts the high density semiconductor memory cell and the memory array of single-transistor " to be submitted to December 6 calendar year 2001, autograph " utilizing the Reprogrammable non-volatile memory of ultra-thin medium breakdown phenomenon "; The Chinese patent application (application number 01129151.6) that submit to December 6 calendar year 2001, autograph " utilizing the semiconductor memory cell and the memory array of ultra-thin medium breakdown phenomenon "; The Chinese patent application (application number 01129150.8) that submit to December 6 calendar year 2001, autograph " smart card " with the memory that utilizes ultra-thin medium breakdown phenomenon.
What Fig. 1 represented is a FPGA array 100 that utilization the present invention constitutes.This array 100 is arrays of two row, two row, but it can extend with random scale.This array 100 comprises four memory cell 102, and each comprises that one is selected 104, one electric capacity 106 of transistor and a switch 108.
Memory cell 102, the first row R for example 1With the first row C 1(be commonly referred to as " bit line " or " row bit line ") intersection point, select the grid of transistor 104 to be connected to readout word line (BLR) in the memory cell 102, leak and be connected to line R 1(be commonly referred to as " word line " or " the row word line "), the source is connected to an end of electric capacity 106.The other end of electric capacity is connected to row bit line (BL).
The grid of switch 108 also are to be connected to the source of selecting transistor 104.Thereby an end of source and electric capacity 106 is connected.This tie point is called as the switch Control Node.The source of switch 108 is connected with the common switch of Ben Lie with the form of leaking with " daisy chain ".
In the process of programming, relative higher voltage be added on the row and column of selection electric capacity 106 two ends, and puncture the gate oxide of electric capacity 106.Among Fig. 1, be positioned at row bit line C xWith row bit line R yThe other memory cell 102 at intersection point place be programmed the y=1 here in the same way ... N, N are the sums of row, x=1 ... M, M are the sums of row.
The element that is programmed with FPGA 100 in 102 such memory cell pie graphs 1 is good because such structure can by standard, only need the CMOS technology of single level polysilicon deposition to make, need not increase mask.And use the Flash FPGA of " floating grid " to need two-layer polysilicon at least.The FPGA of anti-fuse needs special processing step.More long-range says, along with the development of technological level, it is very little that electric capacity and transistor can be done.For example, current 0.18 micron, the technology of 0.13 micron and littler live width will make the density of FPGA improve greatly.
Though only showed one 2 * 2 FPGA array 100, used the FPGA of advanced (for example 0.13 m) CMOS logic process actual fabrication can comprise tens thousand of even millions of unit.Along with the progress of CMOS logic process, bigger array also can be realized.
Fig. 2 is the domain 200 of FPGA array 100 parts.Domain as Fig. 2 is applicable to advanced CMOS logic process.This word of MOS is generally understood as and is applicable to any grid material (comprising doped polycrystalline silicon and other good conductor) and the various gate medium that is not limited to silicon dioxide.This word usefulness that in this explanation, comes to this.For example, dielectric can be any dielectric, and such as oxide or nitride, it when adding the voltage of a period of time hard breakdown or soft breakdown will take place.In an example, used the heat growth grid silicon dioxide of about 50 thickness (0.25 m technology is 50 , and 0.18 m technology is 30 , and 0.13 m technology is 20 ).
FPGA array 100 preferably adopts grid mode layout, makes alignment such as C 1And C 2With line such as R 1, R 2Vertically.Two unit 102 shown in Fig. 2 just are made of row two row.Can see among Fig. 2 that metal wire one (M1) is used for connecting the grid of switch (SW) and an end of electric capacity 106.Select the leakage of transistor (ST and 104) to pass through n +The diffusion region through hole, the ground floor metal, the ground floor contact hole, second layer metal connects with word line.Finally, all devices (selecting transistor 104, electric capacity 106 and switch 108) all will be made of low pressure (LV) oxide and the polysilicon layer above it.
Now, explain the operation principle of FPGA array 100 with reference to illustrative voltages shown in Figure 3.It will be appreciated that these voltages are illustrative, in different application or when using different technologies, will use different voltage probably.When programming, each memory cell in the FPGA array 100 just is exposed under four kinds of a kind of situations in the possible voltage combination, and these voltage combination table are shown the line mark 301,303,305 and 307 among Fig. 3; Write voltmeter and be shown line mark 309,311,313 and 315.Suppose one by R 1And C 1The FPGA unit 102 (note: all unit all are identical with the unit among Fig. 2 102 among the FPGA100) determined of intersection point be chosen as programming.Selecteed memory cell 102 and selected row and selected row (" SR/SC ") are relevant.As shown on the line mark 301, selecteed word line R 1Voltage (demarcate and to be V W1Or " word line voltage ") be 0 volt, bit line C 1Voltage (demarcate and to be V BlOr " bit-line voltage ") be 8 volts.Finally, selecteed read bitline voltage (is demarcated and is V BlrOr " read bitline voltage ") be 3.3 volts.
Such one group of voltage causes selects transistor 104 states to be " opening ", thereby 0 volt of voltage of word line is delivered to an end of electric capacity 106.Electric capacity 106 other ends are connected to bit line (V Bl) be 8 volts.Therefore, the voltage at electric capacity 106 two ends is 8 volts.The gate oxide of electric capacity 106 is designed under this electrical potential difference breakdown, thereby realizes the programming of FPGA unit.Further describe, when the oxide layer of electric capacity 106 was breakdown, this electric capacity 106 also just was converted into resistance.
Need to prove that the accurate numerical value of puncture voltage is to be determined by oxidated layer thickness and some other factors.When with 0.13 m technology, very thin of gate oxide, thereby electric capacity 106 two ends only need very low electrical potential difference to puncture.
Suppose R 1And C 1Be selecteed row and column, consider this being positioned at selecteed row and non-selected row (" SR/UC ") as R 1And C 2The crosspoint on the influence of FPGA unit 102.As shown in the line mark 305, word line R 1Voltage be 0 volt, not by the voltage (V on the selecteed sense bit line Blr) and non-selected bit line C 2Voltage be 0 volt.Because selecting the gate voltage of transistor 104 is 0 volt, FPGA unit 102 is not programmed under this condition.
Suppose R 1And C 1Be selecteed row and column, consider this being positioned at non-selected row and selecteed row (" UR/SC ") as R 2And C 1The influence of the FPGA unit 102 on the crosspoint.Shown in line mark 303 like that, non-selected word line R 2Voltage be 3.3 volts, the voltage (V of selecteed sense bit line Blr) be 3.3 volts, bit line C 1Voltage be 8 volts.Because 3.3 volts of read bitline voltage make and select transistor 104 to be " opening " attitude that 3.3 volts of voltages of word line are delivered to an end of electric capacity 106.Electric capacity other end voltage is constrained on bit-line voltage, is 8 volts at this moment.This causes the electrical potential difference at 4.7 volts at electric capacity 106 two ends.Memory cell 102 is designed to not be programmed under such condition.
Suppose R 1And C 1Be selecteed row and column, consider this for being positioned at non-selected row and non-selected row (" UR/UC ") as R 2And C 2The influence of the FPGA unit 102 on the crosspoint.Shown in line mark 307 like that, not selected word line R 2Voltage be 3.3 volts, the voltage (V of selected sense bit line not Blr) and not selected bit line C 2Voltage be 0 volt.Because selecting the grid voltage of transistor 104 is 0 volt, select transistor to be in " pass " attitude.One end of electric capacity 106 is floated.The other end is 0 volt owing to connect bit line.Under this condition, do not programme in FPGA unit 102.
After FPGA unit 102 was programmed because of electric capacity 106 gate oxide breakdowns, the physical characteristic of unit 102 also was changed.Especially, electric capacity 106 becomes a resistance element.Note, though, in programming process, select the voltage (promptly selecting 3.3 volts of voltages on the gate oxide of transistor 104) on the transistor oxide layer to be higher than its representative value (is 1.8 volts for 0.18 m CMOS technology), but this higher voltage can not puncture the gate oxide of selecting transistor 104, and this is because the programming time very short (generally being shorter than several seconds).
The playback mode of FPGA array 100 is as follows: what add the 1.8-3.3 volt on the row bit line of selecting (" SC ") reads to select voltage, the sense bit line (V that is selecting Blr) on add 1.8 volts read to select voltage, add 0 volt of voltage at the capable word line of selecting (" SR ").Notice that these magnitudes of voltage are the CMOS technology of 0.18 m corresponding to characteristic size.The CMOS technology of more advanced more small-feature-size will be with lower voltage.As in 0.13 mCMOS technology, reading on row bit line of selecting and sense bit line selects voltage to be about 1.2 volts.
Suppose row and column (" the SC/SR ") R of selection 1And C 1Intersection point FPGA unit 102 be programmed.Shown in line mark 309 like that, the voltage (reading to select voltage for one) of 1.8-3.3 volt is by bit line C 1Be connected to an end of electric capacity 106.Notice that a higher bit-line voltage can detect the bigger electric current that reads from bit line.Then select transistorized grid voltage to be changed to 1.8 volts by the sense bit line that connects, will be and leak by the bit line R that connects 1Be changed to 0 volt.This makes that selecting transistor is " opening " attitude.But, be " opening " attitude though select transistor, still have certain resistance by selecting transistor.In addition, if electric capacity 106 is programmed, the 1.8-3.3 volt voltage that is added in two ends can produce the leakage current (generally surpassing 10ua) from the row bit line selected to the row word line.As a result, the electric capacity 106 of programming and selection transistor 104 constitute a bleeder circuit, and its intermediate node is connected to the grid of switch 108.Bleeder circuit places this gate voltage on the switch 108, is enough to open switch 108.If this unit 102 before be not programmed, the resistance ratio of electric capacity 106 selects the resistance of transistor 104 a lot of greatly, because select transistor to open, makes bit-line voltage place switch 108 for 0 volt again, and switch 108 will cut out.
Suppose R 1And C 1Be the row and column of selecting, consider this and select for the row that are positioned at non-selected row and selection (" UR/SC ") as R 2And C 1The influence of the unit 102 on the crosspoint.Shown in line mark 311 like that, the voltage (reading to select voltage for one) of 1.8-3.3 volt is by bit line C 1Be connected to an end of electric capacity 106.Then select transistorized grid voltage to be changed to 1.8 volts, and the source will be by the bit line R that connects by the sense bit line that connects 2Be changed to 1.8 volts.This makes that selecting transistor 104 is " pass " attitude.
Suppose R 1And C 1Be the row and column of selecting, consider this and select the row that is positioned at selection and non-selected row (" SR/UC ") as R 1And C 2The influence of the unit 102 on the crosspoint.Shown in line mark 313 like that, 0 volt voltage (reading to select voltage for one) passes through bit line C 2Be connected to an end of electric capacity 106.Then select transistorized grid voltage to be changed to 0 volt, and source/leakage will be by the bit line R that connects by the sense bit line that connects 1Be changed to 0 volt.Under such condition, from the word line to the bit line, there is not electric current to flow through.
Suppose R 1And C 1Be the row and column of selecting, consider this and select being positioned at non-selected row and non-selected row (" UR/UC ") as R 2And C 2The influence of the unit 102 on the crosspoint.Shown in line mark 315 like that, 0 volt voltage (reading to select voltage for one) passes through bit line C 2Be connected to an end of electric capacity 106.Then select transistorized grid voltage to be changed to 0 volt, and source/leakage will be by the bit line R that connects by the sense bit line that connects 2Be changed to 1.8 volts.Under such condition, from the word line to the bit line, there is not electric current to flow through.
In the process of operation, adopted time column voltage value.At first, the voltage of determining a word line is 0 volt.Then the voltage of a bit line is defined as 1.8 volts, and read bitline voltage is made as 0.3 volt-1.8 volts.V is set BlrBe 0.3 volt-1.8 volts, be to select transistor 104 to be in the crack state that opens, thereby have only very little leakage current (in the nA magnitude) to occur in order to make.
In the concrete illustration that legend 1-3 describes, the gate voltage of switch 108 and V Cc(0.18 m CMOS technology is 0.18 volt) maintains an equal level or is lower slightly.Thereby the magnitude of voltage that switch 108 can transmit has only (V Cc-V t).This can have influence on the speed of FPGA circuit.In another kind of example, the gate oxide of switch 108 and selection transistor 104 is done thicklyer, can be used to the input and output device like this.For example, switch 108 and select the gate oxide thickness of transistor 104 60 or thicker that can be positioned.The gate oxide thickness of electric capacity 106 still maintains the conventional thickness of specific CMOS technology, as 30 in the 0.18 mCMOS technology.The programming of this second kind of example and read voltage and see Fig. 4.
In the read and write operating process in second kind of example, bit-line voltage is biased to 3.3 volts (with respect to 0.18 volts in the example of Fig. 1-3).3.3 volts voltage will be arranged, so it can transfer overvoltage V on the grid of switch 108 CcAnd affix drives gate voltage.Thereby the switch after the programming will have low-down resistance to make speed ability be improved.
Except the memory cell 102 shown in the array 100, in the document of using, oxide layer breakdown various researchs have been carried out.These researchs have pointed out to puncture the suitable voltage of ultra-thin dielectric, and determine that puncture is controlled.When the superthin grid oxide layer is exposed to following time of stress of voltage induced, will occur in the gate oxide puncturing.Really cutter system is not clear though cause the gate oxide intrinsic breakdown, and breakdown process is a progressive process that arrives hard breakdown (" the HBD ") stage by soft breakdown (" SBD ").A kind ofly puncture the defect center that reason is considered to oxide layer.Can work separately and cause puncture in these defect centers, thereby perhaps trap-charge causes local high electric field and big electric current and a kind of positive feedback condition that causes thermal runaway.Thereby improve manufacturing process and can reduce the appearance that this oxide layer defective reduces this puncture.Capture even the Another reason that punctures is considered to the electronics and the space at various centers in flawless oxide layer, this capturing also can cause thermal runaway.
Lay this people such as grade in Lars has carried out the experiment of carrier separation, shows when grid adds positive bias that the ionizing collision of electronics is the main source of substrate gap electric current in the substrate.Mu Hanmode Lars Lay this, English lattice Reed De Wofu, the many Ge Luosensiji of Gui, Luo Bindigeluofu, " the oxide layer breakdown back substrate hole current origin cause of formation " international electronic device meeting 00-537 of the graceful E plum in Hull, 2000 (Mahmoud Rasras, Ingrid DeWolf, Guido Groeseneken, Robin Degraeve, Herman e.Maes, Substrate Hole CurrentOrigin after Oxide Breakdown, IEDM 00-537,2000.) on super thin oxide layer, carried out a Constant Pressure Stress experiment by a kind of device that relates to the raceway groove transoid, show that SBD (soft breakdown) and HBD (hard breakdown) can be used to store data, and just can obtain needed SBD or HBD degree by the stress time of control gate oxide layer memory element.Fig. 5 shows the sectional schematic diagram of this experimental provision.Constant Pressure Stress is shown in Fig. 6 for the influence of superthin grid oxide layer, and the x axle among the figure is the time, is unit with the second; The y axle is an electric current, is unit with the ampere.X-axis becomes logarithmic relationship with the y axle.Fig. 8 shows the grid current and the substrate gap electric current of soft breakdown and hard breakdown fore-and-aft survey under Constant Pressure Stress.In time of 12.5 seconds roughly, total current is very stable, and main component is an electronic current, as I gMeasured.Leakage current can be thought the leakage current (" SILC ") of Fowler-Nordheim (" FN ") tunnel effect and stress induction.At about 12.5 seconds time place, the substrate gap electric current of observing measurement has a big jump, and it is to set up soft breakdown (" SBD ") a signal.From 12.5 seconds to about 19 seconds, total current kept constant substantially on this new level, although some fluctuation of substrate current.Located at about 19 seconds, electronic current and substrate current all have a big jump, show to have set up hard breakdown (" HBD ").From Fig. 6 as seen, the time of standing stress by control gate oxide layer memory element can obtain desired SBD and HBD degree.
People such as Su Xun have studied the back SBD conduction in the ultra-thin silicon dioxide film.Qiao Disuxun, " conduction of soft breakdown in the silicon dioxide gate oxide " international electronic device meeting 00-533 of An Likui Milan Paulette Dubost, 2000 (Jordi Sune, Enrique Miranda, Post Soft Breakdown conduction in SiO2Gate Oxides, IEDM 00-533,2000.) Fig. 7 shows the superthin grid oxide layer in each stage of declining current-voltage (" I-V ") characteristic when falling.Among the figure, the x axle is the voltage of representing with logarithmic relationship, is unit with the volt; The y axle is the electric current of representing with logarithmic relationship, is unit with the ampere.From Fig. 7 as seen, it is very wide to can be used to range of voltage values that the gate oxide memory element is programmed, and SBD or HBD can be used to stored information in the gate oxide memory element.Also show several backs among the figure and puncture I-V characteristic, the change procedure from SBD to HBD as can be seen.Leakage current that produces at SBD and HBD place and the leakage current that produces under the intermediate case between these two kinds of extreme cases are roughly linear with 2.5 volts of magnitudes of voltage to 6 volts of scopes.
People such as Wu have studied the relation of the voltage of super thin oxide layer to the voltage acceleration." the voltage acceleration effect that the super thin oxide layer relevant with voltage punctures " international electronic device meeting 00-541 of EY Wu etc., 2000 (E.Y Wu et al., Voltage-Dependent Voltage-Acceleration of Oxide Breakdown forUltra-Thin Oxides, IEDM 00-541,2000. Figure 10 show the relation of the breakdown time of 63% distribution that the n-ditch FETs (transoid) that changes from 2.3nm to 5.0nm at oxidated layer thickness measures to the semi-logarithmic scale grid voltage.These distribute generally speaking consistent and are linear, show that this process is controlled.
It is that 3nm, area are 6.4 * 10 to oxidated layer thickness after detecting the Continuous Breakdown incident that people from Milan such as reaches -5Cm 2NMOSFET (n field effect type semiconductor transistor) device carried out the I-V feature measurement.People from Milan such as reaches at " analytic modell analytical model of the leakage current by multiple breakdown channel in the silica membrane " the 39th international Reliability Physics school year forum of international Institute of Electrical and Electric Engineers, calendar year 2001 Orlando 367-379 page or leaf (" Analytic Modeling of Leakage Current Through Multiple Breakdown Pathsin SiO2 Films ", IEEE 39th Annual International Reliability Physics Symposium, Orlando, FL, 2001, pp 367-379.) Fig. 9 shows these measurement results corresponding to linear zone, and wherein " N " is the conducting channel number.These results are very linear, show that path is resistive basically.
The transistor that uses in the various memory cells described here all is some normal low voltage logic transistors as a rule.If adopt 0.25 m technology, these transistorized superthin grid oxidated layer thickness such as about 50 ; If adopt 0.13 m technology, these transistorized superthin grid oxidated layer thickness such as about 20 .Voltage on a kind of like this superthin grid oxide layer two ends can temporarily be much higher than V when programming Cc, for V with the integrated circuit of 0.25 m technology manufacturing CcBe generally 2.5 volts; For the integrated circuit made from 0.13 m technology, V CcBe generally 1.2 volts.Such super thin oxide layer generally can stand 4 to 5 volts voltage and can not reduce transistor performance.
Invention description described here and application thereof are just illustrative, are not to limit invention scope.Here some examples that disclose had many mutation and modification.The people who has a common skill in technology circle knows the actual substitute and the equivalence product of various elements in these examples.For example, the various voltages that adopt in each example are illustrative, because people have the judgment of selecting a precise voltage value in a voltage range, and magnitude of voltage is all relevant with device property in either case.In order to narrate normally used line kind in the memory, used words such as line, alignment and source line, but some memory can there be other call to these lines.In addition, various doping types may be reversed, and for example the previously described n type of this paper channel transistor may be replaced by p type channel transistor.Therefore, scope and spirit of the present invention be must not depart from, just can such and such change and improvement be done the disclosed example of this paper.

Claims (16)

1, be applicable to have the row bit line, field programmable gate array (FPGA) unit of the FPGA array of sense bit line and row word line is characterized in that this unit contains:
A capacitor, it has first terminal and second terminal, and first terminal is connected to the row bit line, and second terminal is connected to a switch control node, between above-mentioned first terminal of above-mentioned capacitor and second terminal dielectric layer is arranged;
Select transistor for one, it has grid, a source and a leakage, and above-mentioned grid are connected to above-mentioned sense bit line, and above-mentioned source is connected to above-mentioned switch Control Node, and above-mentioned leakage is connected to a capable word line;
A switch, it is controlled by above-mentioned switch Control Node.
2, by the described field programmable gate array of claim 1 (FPGA) unit, it is characterized in that: described switch is a mos field effect transistor (MOSFET), and the grid of above-mentioned mos field effect transistor (MOSFET) are connected to above-mentioned switch Control Node.
3, by the described field programmable gate array of claim 2 (FPGA) unit, it is characterized in that: described switch and described selection transistor have the gate oxide thicker than the dielectric of above-mentioned capacitor.
4, by the described field programmable gate array of claim 1 (FPGA) unit, it is characterized in that: above-mentioned first terminal of above-mentioned capacitor, the grid of transistorized above-mentioned grid of above-mentioned selection and above-mentioned switch form with same polysilicon layer.
5, by the described field programmable gate array of claim 1 (FPGA) unit, it is characterized in that: the first metal layer connects the above-mentioned grid of above-mentioned switch Control Node and above-mentioned switch.
6, by the described field programmable gate array of claim 3 (FPGA) unit, it is characterized in that: the gate oxide thickness that above-mentioned switch and the transistorized above-mentioned gate oxide thickness of selection are input/output transistors under the CMOS technology.
7, the method for a kind of operation site programmable gate array (FPGA), this gate array comprises many capable word lines, many row bit lines, many sense bit lines, and many FPGA unit on the crosspoint of corresponding row word line and row bit line; Above-mentioned FPGA unit comprises a capacitor, a selection transistor and a switch; Above-mentioned capacitor has first terminal and second terminal, and first terminal is connected to a row bit line, and above-mentioned second terminal is connected to a switch Control Node; Between above-mentioned first terminal of above-mentioned capacitor and above-mentioned second terminal is dielectric; Above-mentioned selection transistor has grid, a source and a leakage, and above-mentioned grid are connected to above-mentioned sense bit line, and above-mentioned source is connected to above-mentioned switch Control Node, and above-mentioned leakage is connected to a capable word line; Above-mentioned switch is controlled by above-mentioned switch Control Node; It is characterized in that this method comprises:
Add on first voltage to one selecteed row bit line and the transistorized grid of selecteed above-mentioned selection;
Add on second voltage to the one selecteed capable word line;
Cross over first voltage and second voltage of capacitor dielectric, form an electrical potential difference and puncture above-mentioned dielectric, make above-mentioned capacitor become a resistance device.
8, by the method for the described operation site programmable gate array of claim 7 (FPGA), it is characterized in that: also comprise add the 3rd voltage to the not corresponding capable word line of above-mentioned selecteed selection transistor on.
9, by the method for the described operation site programmable gate array of claim 7 (FPGA), it is characterized in that: above-mentioned selecteed selection transistor is read on above-mentioned selecteed selection transistor and above-mentioned row bit line by adding the 4th voltage.
10, by the method for the described operation site programmable gate array of claim 9 (FPGA), it is characterized in that: also comprise add the 5th voltage to the not corresponding capable word line of above-mentioned selecteed selection transistor on.
11, a kind of field programmable gate array (FPGA), this gate array comprises many capable word lines, many row bit lines, many sense bit lines, and many unit on the crosspoint of corresponding row word line and row bit line; It is characterized in that each unit comprises:
The capacitor that first terminal and second terminal are arranged, first terminal is connected to a row bit line, and above-mentioned second terminal is connected to a switch Control Node, is dielectric between above-mentioned first terminal of above-mentioned capacitor and above-mentioned second terminal;
Select transistor for one, it has grid, a source and a leakage, and above-mentioned grid are connected to above-mentioned sense bit line, and above-mentioned source is connected to above-mentioned switch Control Node, and above-mentioned leakage is connected to a capable word line;
A switch is controlled by above-mentioned switch Control Node.
12, by the described field programmable gate array of claim 11 (FPGA), it is characterized in that: above-mentioned switch is a MOSFET, and the grid of above-mentioned MOSFET are connected to above-mentioned switch Control Node.
13, by the described field programmable gate array of claim 12 (FPGA), it is characterized in that: above-mentioned switch and above-mentioned selection transistor have the gate oxide thicker than above-mentioned capacitor dielectric.
14, by the described field programmable gate array of claim 11 (FPGA), it is characterized in that: above-mentioned first terminal of above-mentioned capacitor, the grid of transistorized above-mentioned grid of above-mentioned selection and above-mentioned switch form with same polysilicon layer.
15, by the described field programmable gate array of claim 11 (FPGA), it is characterized in that: the first metal layer connects the above-mentioned grid of above-mentioned switch Control Node and above-mentioned switch.
16, by the described field programmable gate array of claim 13 (FPGA), it is characterized in that: the above-mentioned gate oxide of above-mentioned switch and selection transistor are the thickness of the input/output transistors under the CMOS technology.
CN 03117373 2003-02-28 2003-02-28 Programmable gate array based on transistor grid oxidation layr breakdown property Expired - Fee Related CN1267995C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 03117373 CN1267995C (en) 2003-02-28 2003-02-28 Programmable gate array based on transistor grid oxidation layr breakdown property

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 03117373 CN1267995C (en) 2003-02-28 2003-02-28 Programmable gate array based on transistor grid oxidation layr breakdown property

Publications (2)

Publication Number Publication Date
CN1434513A true CN1434513A (en) 2003-08-06
CN1267995C CN1267995C (en) 2006-08-02

Family

ID=27634344

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 03117373 Expired - Fee Related CN1267995C (en) 2003-02-28 2003-02-28 Programmable gate array based on transistor grid oxidation layr breakdown property

Country Status (1)

Country Link
CN (1) CN1267995C (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102224566A (en) * 2008-11-21 2011-10-19 吉林克斯公司 Integrated capacitor with alternating layered segments
CN103187420A (en) * 2011-12-29 2013-07-03 无锡华润上华科技有限公司 One-time programmable storage unit and manufacturing method and semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102224566A (en) * 2008-11-21 2011-10-19 吉林克斯公司 Integrated capacitor with alternating layered segments
CN102224566B (en) * 2008-11-21 2014-02-19 吉林克斯公司 Integrated capacitor with alternating layered segments
CN103187420A (en) * 2011-12-29 2013-07-03 无锡华润上华科技有限公司 One-time programmable storage unit and manufacturing method and semiconductor device
CN103187420B (en) * 2011-12-29 2015-11-25 无锡华润上华科技有限公司 One-time programmable memory cell and manufacture method, semiconductor device

Also Published As

Publication number Publication date
CN1267995C (en) 2006-08-02

Similar Documents

Publication Publication Date Title
US6650143B1 (en) Field programmable gate array based upon transistor gate oxide breakdown
US11398256B2 (en) Local bit lines and methods of selecting the same to access memory elements in cross-point arrays
US9595530B1 (en) Methods and apparatus for vertical bit line structures in three-dimensional nonvolatile memory
US7623368B2 (en) Non-volatile semiconductor memory based on enhanced gate oxide breakdown
JP4599059B2 (en) Semiconductor memory cell and memory array utilizing breakdown phenomenon of ultra-thin dielectric
CN100524831C (en) Semiconductor memory cell, memory array and operation method thereof
JP5043357B2 (en) Programmable memory cell
US10181341B1 (en) Memory device including current generator plate
CN1726562A (en) CMIS semiconductor nonvolatile storage circuit
US6791891B1 (en) Method of testing the thin oxide of a semiconductor memory cell that uses breakdown voltage
JP2016167332A (en) Storage device
JP2010103563A (en) Semiconductor memory cell and memory array using breakdown phenomena in ultra-thin dielectric
JPH0855488A (en) Circuit for detecting distribution of cell threshold value and method therefor
CN1737993A (en) Mos electric fuse, its programming method, and semiconductor device using the same
US20070109852A1 (en) One time programming memory cell using MOS device
US10109680B1 (en) Methods and apparatus for three-dimensional nonvolatile memory
US8873271B2 (en) 3D architecture for bipolar memory using bipolar access device
US10541273B2 (en) Vertical thin film transistors with isolation
CN1267995C (en) Programmable gate array based on transistor grid oxidation layr breakdown property
JPH06291287A (en) Nonvolatile semiconductor memory device
US20190034125A1 (en) Methods and apparatus for three-dimensional nonvolatile memory
CN1229870C (en) Single transistor adopted high-density semiconductor memory unit and memory array
WO2022130554A1 (en) Semiconductor memory device
CN1190849C (en) Semiconductor memory unit and array using ultra-thin medium breakdown phenomenon
JP2023118092A (en) Resistive memory cell and associated cell array structure

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20060802

Termination date: 20190228