CN1434503A - Method for making memroy element - Google Patents
Method for making memroy element Download PDFInfo
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- CN1434503A CN1434503A CN 02102504 CN02102504A CN1434503A CN 1434503 A CN1434503 A CN 1434503A CN 02102504 CN02102504 CN 02102504 CN 02102504 A CN02102504 A CN 02102504A CN 1434503 A CN1434503 A CN 1434503A
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Abstract
A process method for memory element is to form a thin dielectric layer on a provided base and form a strip conductive structure composed of a polysilicon layer and a top-cover layer on the thin dielectric layer then to form a built-in position lead on the base both sides of the conducting structure and a bottom anti-reflection layer above the base, then, further to form several polysilicon islands with patternized bottom anti-reflection layer vertical to the strip conducting structure and the said structure to form a figure line on the islands.
Description
Technical field
The invention relates to a kind of manufacture method of memory component, and particularly relevant for a kind of manufacture method of polysilicon island thing (Poly-Island) of memory component.
Background technology
Memory is as the term suggests be in order to store data or the semiconductor element of data.In the storage of numerical data, our ordinary practice forms the capacity of memory with position (Bit).Each then is called memory cell (Cell) in order to the unit that stores data in the memory.And memory cell is in ten hundreds of bank bits, and the ad-hoc location at place then is called address (Address).In other words, memory cell is able to arranged in array mode in memory, and each row is represented a particular storage address with the combination of row.Wherein, list in colleague or several memory cell of same column are connected in series with common lead.The lead that memory cell is joined is called character line (Word Line), and perpendicular to another lead of character line because relevant with the transmission of data, therefore be called bit line (Bit Line).
Shown in Figure 1A to Fig. 1 E, it illustrates the manufacturing process generalized section into known a kind of memory component.
Please refer to Figure 1A, the photoresist layer 108 of one oxide layer 102, a polysilicon layer 104, a silicon nitride layer 106 and a patterning at first is provided in the substrate 100 that is provided in the manufacture method system of known memory component.
Afterwards, please refer to 1B figure, is etch mask with photoresist layer 108, and patterned sin layer 106 and polysilicon layer 104 are with the conductive structure 105 that forms a strip.Afterwards, in the substrate 100 of conductive structure 105 both sides of strip, form an embedded type bit line 101.
Then, please refer to 1C figure, in substrate 100, form an insulating barrier 110, cover the conductive structure 105 and embedded type bit line 101 of strip.
Afterwards, please refer to 1D figure and Fig. 1 E, etch-back insulating barrier 110 and remove silicon nitride layer 106 forms a conductive layer 115 again on the polysilicon layer 104 of strip and insulating barrier 110.Then, with perpendicular to the directional patterns conductive layer 115 of embedded type bit line 101 and the polysilicon layer 104 of strip, to form a character line (not drawing) and several polysilicon island things (not drawing) respectively.
In the manufacture method of known memory component, be on earlier that a conductive layer is the comprehensive polysilicon layer that covers strip after, again with the etch process polysilicon layer of this conductive layer of patterning and strip simultaneously, to form character line and polysilicon island thing respectively.And this kind method be with an etch process simultaneously with conductive layer and the two-layer patterning of strip polysilicon layer, therefore can be because of the problem of high-aspect-ratio (High Aspect Ratio), and easily produce the incomplete situation of etching.In addition since in the known method in order to form the etch process parameters of polysilicon island thing, tend to damage oxide layer, or even substrate surface.
Summary of the invention
Purpose of the present invention just provides a kind of manufacture method of memory component, to avoid can influencing its etched quality because of the problem of high-aspect-ratio when forming polysilicon island thing.
Another object of the present invention provides a kind of manufacture method of polysilicon island thing, so that in the etch process that forms polysilicon island thing, can not injure oxide layer and substrate.
The present invention proposes a kind of manufacture method of memory component, and it is that a thin dielectric layer at first is provided in a substrate that is provided, and wherein this thin dielectric layer is that example is a tunnel oxide with the flash memory, is that example is a gate oxide with the mask-type ROM.Then form the conductive structure of a strip on thin dielectric layer, wherein the conductive structure of strip is made of a polysilicon layer and a cap layer.Afterwards, in the conductive structure substrate on two sides of strip, form an embedded type bit line.And form a bottom anti-reflection layer (BottomAnti-Reflective Coating BRAC), covers the conductive structure and the embedded type bit line of strip in the top of substrate.Then, with the direction perpendicular to the conductive structure of strip, the conductive structure of patterning bottom anti-reflection layer and strip is to form the conductive structure of several islands.And the method for the conductive structure of patterning strip is at first carried out one first etch process, wherein first etch process is with hydrogen bromide and carbon tetrafluoride (HBr/CF4) gas source as etching plasma, and first etch process is about 1 for the etching selectivity of bottom anti-reflection layer and cap layer.Carry out one second etch process afterwards, wherein second etch process is with carbon tetrafluoride, three fluorocarbonss and argon gas (CF4/CHF3/Ar) gas source as etching plasma, and second etch process for the etching selectivity of cap layer and bottom anti-reflection layer greater than about 5.Carry out one the 3rd etch process then, wherein the 3rd etch process is with hydrogen bromide, helium and helium-oxygen (HBr/He/He-O2) gas source as etching plasma, and the 3rd etch process for the etching selectivity of polysilicon layer and oxide layer greater than about 50.Then, after removing remaining bottom anti-reflection layer, between the conductive structure of several islands, insert an insulating barrier, remove the cap layer of several conductive structures again.Afterwards, on the polysilicon layer of several conductive structures, form a character line.
The present invention proposes a kind of manufacture method of polysilicon island thing, and one oxide layer at first is provided in a substrate that is provided the method.Then form the conductive structure of a strip on oxide layer, wherein the conductive structure of strip is made of a polysilicon layer and a cap layer.Afterwards, above substrate, form a bottom anti-reflection layer, cover the conductive structure of strip.Then with the direction perpendicular to the conductive structure of strip, the conductive structure of patterning bottom anti-reflection layer and strip is to form several polysilicon island things.And the method for the conductive structure of patterning strip is at first carried out one first etch process, wherein first etch process is with hydrogen bromide and carbon tetrafluoride (HBr/CF4) gas source as etching plasma, and first etch process is about 1 for the etching selectivity of bottom anti-reflection layer and cap layer.Carry out one second etch process afterwards, wherein second etch process is with carbon tetrafluoride, three fluorocarbonss and argon gas (CF4/CHF3/Ar) gas source as etching plasma, and second etch process for the etching selectivity of cap layer and bottom anti-reflection layer greater than about 5.Carry out one the 3rd etch process then, wherein the 3rd etch process is with hydrogen bromide, helium and helium-oxygen (HBr/He/He-O2) gas source as etching plasma, and the 3rd etch process for the etching selectivity of polysilicon layer and oxide layer greater than about 50.
The manufacture method of memory component of the present invention owing to it earlier forms conductive structure patterning of strip after the polysilicon layer of island, just forms character line on the polysilicon layer of island.Therefore, can avoid in the known method because of the conductive structure of while etching strip and the problem that high-aspect-ratio is arranged in order to the material layer that forms character line.
The manufacture method of polysilicon island thing of the present invention, its etch process parameters can avoid the thin dielectric layer (for example tunnel oxide) of polysilicon island thing below to suffer damage with substrate.
Description of drawings
Figure 1A to Fig. 1 E is the manufacturing process generalized section of known a kind of memory component;
Fig. 2 A to Fig. 2 P be according to the manufacturing process section of the memory component of a preferred embodiment of the present invention and on look schematic diagram.
100,200: substrate
101,201: embedded type bit line
102,202: oxide layer (thin dielectric layer)
104,204,204a: polysilicon layer
105,205: the conductive structure of strip
106,206,206a: silicon nitride layer (cap layer)
108,208,212: photoresist layer
110,214: insulating barrier
115: conductive layer
205a: the conductive structure of island
210: bottom anti-reflection layer
216: character line
Embodiment
Fig. 2 A to Fig. 2 P, it is the manufacture method according to the memory component of a preferred embodiment of the present invention.
Please refer to Fig. 2 A, a thin dielectric layer 202, a polysilicon layer 204, a cap layer 206 and a patterned light blockage layer 208 at first are provided in the substrate 200 that is provided successively.Wherein, thin dielectric layer 202 is that example is a tunnel oxide with the flash memory, is that example is a gate oxide with the mask-type ROM.The material of cap layer 206 for example is a silicon nitride.
Afterwards, please refer to Fig. 2 B, is etch mask with photoresist layer 208, and patterning cap layer 206 and polysilicon layer 204 are with the conductive structure 205 that forms a strip.Then, in conductive structure 205 substrate on two sides 200 of strip, form an embedded type bit line 201 with ionic-implantation.
Then, please refer to Fig. 2 C, above substrate 200, deposit a bottom anti-reflection layer 210, cover the conductive structure 205 and the embedded type bit line 201 of strip.The thickness of wherein formed bottom anti-reflection layer 210 is enough thick, so that formed bottom anti-reflection layer 210 has a smooth surface.
Then, please be simultaneously with reference to Fig. 2 D to Fig. 2 G, Fig. 2 E is by the generalized section of I-I ' among Fig. 2 D; Fig. 2 F is by the generalized section of II-II ' among Fig. 2 D; And among Fig. 2 G formula Fig. 2 D by the generalized section of III-III '.
Form a patterned light blockage layer 212 on bottom anti-reflection layer 210, wherein, photoresist layer 212 is several strip patterns vertical with the conductive structure 205 of strip.Be etch mask with photoresist layer 212 afterwards, the conductive structure 205 of patterning strip.
Then, please be simultaneously with reference to Fig. 2 H to Fig. 2 K, Fig. 2 I is by the generalized section of I-I ' among Fig. 2 H; Fig. 2 J is by the generalized section of II-II ' among Fig. 2 H; And Fig. 2 K is by the generalized section of III-III ' among Fig. 2 H.
After being the conductive structure 205 of etch mask patterning strip, just formed the conductive structure 205a of several islands with photoresist layer 212.Wherein the conductive structure 205a of each island comprises the polysilicon layer 204a of an island and the cap layer 206a of an island.And between each leads the conductive structure 205a of shape, have a bottom anti-reflection layer 210 that part is not removed.
Wherein, the method for the conductive structure 205 of patterning strip is to be formed by the etch process of three steps.Wherein, first etch process is with hydrogen bromide and the carbon tetrafluoride gas source as etching plasma, and first etch process is about 1 for the etching selectivity between bottom anti-reflection layer 210 and the cap layer 206.Therefore, first etch process together with the time remove the cap layer 206 of bottom anti-reflection layer 210 with the part of part.And the process conditions of first etch process for example are the hydrogen bromide of feeding 10sccm to 20sccm gas flow and the carbon tetrafluoride of 70sccm to 90sccm gas flow.And a gas pressure of first etch process is 10mTorr to 20mTorr for example.In addition, first etch process for example is to carry out at a high-density plasma etching chamber (HDP Etcher), and the power supply that its top is supplied for example is 650 watts to 750 watts, and the power supply that its bottom is supplied for example is 140 watts to 160 watts.
After carrying out first etch process, carry out one second etch process.Wherein, second etch process is with carbon tetrafluoride, three fluorocarbonss and the argon gas gas source as etching plasma, and second etch process is greater than about 5 for the etching selectivity between cap layer 206 and the bottom anti-reflection layer 210.Therefore in second etch process, the etch-rate of bottom anti-reflection layer 210 can be less than the etch-rate of cap layer 206.And the process conditions of second etch process are for example for feeding carbon tetrafluoride, three fluorocarbonss of 50sccm to 70sccm gas flow and the argon gas of 100sccm to 200sccm gas flow of 10sccm to 20sccm gas flow.And a gas pressure of second etch process is 100mTorr to 150mTorr for example.In addition, second etch process for example is to carry out in heavier-duty reactive ion etching chamber, a magnetic field (MERIEEtcher), and the power supply that its bottom is supplied for example is 500 watts to 700 watts.
After carrying out second etch process, carry out one the 3rd etch process.Wherein, the 3rd etch process is with hydrogen bromide, helium and the helium-oxygen gas source as etching plasma, and the 3rd etch process for the etching selectivity of polysilicon layer 204 and the thin dielectric layer 202 of silica material greater than about 50.Therefore, in the 3rd etch process, the etch-rate of polysilicon layer 204 is far longer than the etch-rate of thin dielectric layer 202.And the process conditions of the 3rd etch process are for example for feeding hydrogen bromide, the helium of 50sccm to 150sccm gas flow and the helium-oxygen mixed gas of 3sccm to 10sccm gas flow of 150sccm to 250sccm gas flow.And a gas pressure of the 3rd etch process is 60mTorr to 80mTorr for example.In addition, the 3rd etch process for example is to carry out in a high-density plasma etching chamber, and the power supply that its top is supplied for example is 300 watts to 400 watts, and the power supply that its bottom is supplied for example is 60 watts to 90 watts.
Since the parameter of the 3rd etch process for the thin dielectric layer 202 of silica material and the etching selectivity between the polysilicon layer 204 greater than about 50.Therefore,, also can stop at thin dielectric layer 202 automatically, and can not injure thin dielectric layer 202 even the 3rd etch process is removed bottom anti-reflection layer 210 fully, even eating thrown thin dielectric layer 202 and damage the surface of substrate 200.
Afterwards, please refer to Fig. 2 L to Fig. 2 O, Fig. 2 M is by the generalized section of I-I ' among Fig. 2 L; Fig. 2 N is by the generalized section of II-II ' among Fig. 2 L; And Fig. 2 O is by the generalized section of III-III ' among Fig. 2 L.
After the conductive structure 205a that forms several islands, remove photoresist layer 212 and residual bottom anti-reflection layer 210.Wherein, remove the method for photoresist layer 212 and residual bottom anti-reflection layer 210 for example with dry-etching method and wet etching removal.
Then, please refer to Fig. 2 P, Fig. 2 P is by the generalized section of IV-IV ' among Fig. 2 L.After removing photoresist layer 212, between the conductive structure 205a of island, insert an insulating barrier 214, and the cap layer 206a of island is removed.Afterwards, go up formation one character line 216, so that the polysilicon layer 204a of several islands electrically connects in the polysilicon layer 204a of island.The method that wherein forms character line 216 for example is top deposition one deck conductive layer (not drawing) of substrate 200 earlier, covers polysilicon layer 204a and the insulating barrier 214 of several islands, and patterned conductive layer more afterwards is with formation character line 216.
The manufacture method of memory component of the present invention owing to it earlier forms polysilicon layer 204 patternings of strip after the polysilicon layer 204a of several islands, just goes up in the polysilicon layer 204a of several islands and forms character line 216.Therefore, can avoid in the known method because of the polysilicon layer of the strip of etching simultaneously with in order to forming the material layer of character line, and cause the problem of high-aspect-ratio, make etching be difficult for.In addition, because the conductive structure 205 employed three step etch processs of patterning strip of the present invention, it is the technological parameter that is designed at each layer of material, it utilizes different etching selectivities so that in the etching process of the polysilicon layer 204a that forms several islands, can not injure the thin dielectric layer 202 of silica material, even eating thrown thin dielectric layer 202 is arranged and damage the situation on substrate 200 surfaces.
Comprehensive the above, the present invention has following advantage:
1. the manufacture method of memory component of the present invention can be avoided in the known method because of the conductive structure of while etching strip and the high-aspect-ratio problem that causes in order to the material layer that forms character line.
2. the manufacture method of polysilicon island thing of the present invention, its etch process parameters can avoid the thin dielectric layer (for example tunnel oxide) of polysilicon island thing below to suffer damage with substrate.
Claims (17)
1, a kind of manufacture method of memory component is characterized in that, this method comprises the following steps:
In a substrate, form a thin dielectric layer;
Form the conductive structure of a strip on this thin dielectric layer, wherein the conductive structure of this strip comprises a polysilicon layer and a cap layer;
In the conductive structure substrate on two sides of this strip, form an embedded type bit line;
Above this substrate, form a bottom anti-reflection layer, cover conductive structure and this embedded type bit line of this strip;
With the direction perpendicular to the conductive structure of this strip, the conductive structure of this bottom anti-reflection layer of patterning and this strip is to form the conductive structure of a plurality of islands;
Between the conductive structure of those islands, insert an insulating barrier;
Remove this cap layer of the conductive structure of those islands; And
On this polysilicon layer of the conductive structure of those islands, form a character line.
2, the manufacture method of memory component as claimed in claim 1 is characterized in that, the method for the conductive structure of those strips of patterning comprises: form with a plurality of etch processs with different etching selectivities.
3, the manufacture method of memory component as claimed in claim 2, it is characterized in that, the method of the conductive structure of those strips of patterning comprises: carry out one first etch process, one bottom anti-reflection layer of this first etch process and the etching selectivity of cap layer are about 1, carry out one second etch process afterwards, one cap layer of this second etch process and the etching selectivity of bottom anti-reflection layer are greater than 5, carry out one the 3rd etch process afterwards, a polysilicon layer of the 3rd etch process and the etching selectivity of thin dielectric layer are greater than 50.
4, the manufacture method of memory component as claimed in claim 3, it is characterized in that, the hydrogen bromide of this first etch process use 10sccm to 20sccm and the carbon tetrafluoride of 70sccm to 90sccm are as the gas source of an etching plasma, and a gas pressure of this first etch process is 10mTorr to 20mTorr.
5, the manufacture method of memory component as claimed in claim 3, it is characterized in that, the argon gas of the carbon tetrafluoride (CF4) of this second etch process use 10sccm to 20sccm, three fluorocarbonss of 50sccm to 70sccm and 100sccm to 200sccm is as the gas source of an etching plasma, and a gas pressure of this second etch process is 100mTorr to 150mTorr.
6, the manufacture method of memory component as claimed in claim 3, it is characterized in that, helium-oxygen of the hydrogen bromide of the 3rd etch process use 150sccm to 250sccm, the helium of 50sccm to 150sccm and 3sccm to 10sccm is as the gas source of an etching plasma, and a gas pressure of the 3rd etch process is 60mTorr to 80mTorr.
7, the manufacture method of memory component as claimed in claim 1 is characterized in that, this thin dielectric layer comprises a tunnel oxide.
8, the manufacture method of memory component as claimed in claim 1 is characterized in that, the material of this cap layer comprises silicon nitride.
9, a kind of manufacture method of polysilicon island thing is characterized in that, this method comprises the following steps:
In a substrate, form an oxide layer;
Form the conductive structure of a strip on this oxide layer, wherein the conductive structure of this strip comprises a polysilicon layer and a cap layer;
Above this substrate, form a bottom anti-reflection layer, cover the conductive structure of this strip; And
With direction perpendicular to the conductive structure of this strip, the conductive structure of this bottom anti-reflection layer of patterning and this strip, forming a plurality of polysilicon island things,
Wherein the method for the conductive structure of those strips of patterning comprises that a plurality of etch processs to have different etching selectivities form.
10, the manufacture method of polysilicon island thing as claimed in claim 9, it is characterized in that, the method of the conductive structure of this strip of patterning comprises carries out one first etch process, one bottom anti-reflection layer of this first etch process and the etching selectivity of cap layer are about 1, carry out one second etch process afterwards, one cap layer of this second etch process and the etching selectivity of bottom anti-reflection layer are greater than 5, carry out one the 3rd etch process afterwards, a polysilicon layer of the 3rd etch process and the etching selectivity of oxide layer are greater than 50.
11, the manufacture method of polysilicon island thing as claimed in claim 10, it is characterized in that, the hydrogen bromide of this first etch process use 10sccm to 20sccm and the carbon tetrafluoride of 70sccm to 90sccm are as the gas source of an etching plasma, and a gas pressure of this first etch process is 10mTorr to 20mTorr.
12, the manufacture method of polysilicon island thing as claimed in claim 11 is characterized in that, this first etch process carries out in a high-density plasma etching chamber.
13, the manufacture method of polysilicon island thing as claimed in claim 10, it is characterized in that, the argon gas of the carbon tetrafluoride of this second etch process use 10sccm to 20sccm, three fluorocarbonss of 50sccm to 70sccm and 100sccm to 200sccm is as the gas source of an etching plasma, and a gas pressure of this second etch process is 100mTorr to 150mTorr.
14, the manufacture method of polysilicon island thing as claimed in claim 13 is characterized in that, this second etch process carries out in heavier-duty reactive ion etching chamber, a magnetic field.
15, the manufacture method of polysilicon island thing as claimed in claim 10, it is characterized in that, helium-oxygen of the hydrogen bromide of the 3rd etch process use 150sccm to 250sccm, the helium of 50sccm to 150sccm and 3sccm to 10sccm is as the gas source of an etching plasma, and a gas pressure of the 3rd etch process is 60mTorr to 80mTorr.
16, the manufacture method of polysilicon island thing as claimed in claim 15 is characterized in that, this second etch process carries out in a high-density plasma etching chamber.
17, the manufacture method of polysilicon island thing as claimed in claim 9 is characterized in that, the material of this cap layer comprises silicon nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02102504 CN1261999C (en) | 2002-01-23 | 2002-01-23 | Method for making memroy element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02102504 CN1261999C (en) | 2002-01-23 | 2002-01-23 | Method for making memroy element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1434503A true CN1434503A (en) | 2003-08-06 |
| CN1261999C CN1261999C (en) | 2006-06-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02102504 Expired - Fee Related CN1261999C (en) | 2002-01-23 | 2002-01-23 | Method for making memroy element |
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| CN (1) | CN1261999C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100338761C (en) * | 2004-01-02 | 2007-09-19 | 因芬尼昂技术股份公司 | Method of manufacturing a layer sequence and a method of manufacturing an integrated circuit |
| CN102800582A (en) * | 2011-05-23 | 2012-11-28 | 南亚科技股份有限公司 | Method for forming a recess array device structure in a semiconductor substrate |
| CN107527809A (en) * | 2016-06-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic installation |
-
2002
- 2002-01-23 CN CN 02102504 patent/CN1261999C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100338761C (en) * | 2004-01-02 | 2007-09-19 | 因芬尼昂技术股份公司 | Method of manufacturing a layer sequence and a method of manufacturing an integrated circuit |
| CN102800582A (en) * | 2011-05-23 | 2012-11-28 | 南亚科技股份有限公司 | Method for forming a recess array device structure in a semiconductor substrate |
| CN102800582B (en) * | 2011-05-23 | 2015-03-25 | 南亚科技股份有限公司 | Method for forming a recess array device structure in a semiconductor substrate |
| CN107527809A (en) * | 2016-06-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method, electronic installation |
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| Publication number | Publication date |
|---|---|
| CN1261999C (en) | 2006-06-28 |
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