CN1428932A

CN1428932A - Low power consumption analogue signal sample retaining circuit and its application method

Info

Publication number: CN1428932A
Application number: CN 01143452
Authority: CN
Inventors: 吴南健; 旷章曲; 陈杰; 寿国梁; 杨军
Original assignee: LIUHE WANTONG MICROELECTRONIC TECHNOLOGY Co Ltd BEIJING
Current assignee: Beijing LHWT Microelectronics Inc.
Priority date: 2001-12-28
Filing date: 2001-12-28
Publication date: 2003-07-09
Anticipated expiration: 2021-12-28
Also published as: CN1194469C

Abstract

The present invention relates to an analog signal sampling/holding circuit with low power consumption and its application method. Said invention includes at least three-stage amplification circuit, sampling and holding circuit, and it is characterized by that three control switches are added, and a control signal is newly added, and can be used for respectively controlling the described control switches, and the last one-stage amplification circuit input end can be used for controlling control signal inversion of switch and other control switches. When the neural operation amplification sampling/holding circuit is in the rest state, the power consumption of the circuit only is formed from electric leakage of tube, so that it possesses the advantages of low power consumption, and when the circuit is in the restoration state, its sampling signal can be normally outputted.

Description

The analogue signal sample retaining circuit of low-power consumption and using method thereof

Technical field

The invention belongs to the analogue signal sample retaining circuit field, especially the analogue signal sample retaining circuit of low-power consumption and using method thereof.

Background technology

Analogue signal sample retaining circuit was sampled to input signal in the short time, entered the stable signal that is sampled of hold mode and exported the signal that is kept when needed in the rest period time.Present common analogue signal sample retaining circuit, by three-stage amplifier, sampling and holding circuit are formed at least, comprise an input signal, an output signal and a control signal, have only sampling and keep two states, metal-oxide-semiconductor in the analogue signal sample retaining circuit under any circumstance, all the time be in saturation condition, therefore, the power consumption of circuit is bigger.

After input signal was handled through the one-level analogue signal sample retaining circuit, output signal and input signal were anti-phase.

Summary of the invention

One of purpose of the present invention provides a kind of analogue signal sample retaining circuit that can allow as required by stage work and rest, thereby saving power consumption, and when the analogue signal sample retaining circuit rest, still can preserve have a rest before institute's sampled signal, after starting working again, can normally export the analogue signal sample retaining circuit of the low-power consumption of institute's sampled signal before rest.

Another object of the present invention provides a kind of using method of analogue signal sample retaining circuit of above-mentioned low-power consumption.

Technical scheme of the present invention is: the analogue signal sample retaining circuit of low-power consumption comprises three-stage amplifier, sampling and holding circuit at least.It is characterized in that increasing by three control switchs.One of them is connected between the PMOS pipe and power supply that links to each other with power supply on final stage amplifying circuit each grade amplifying circuit before, to control switching on and off of described PMOS pipe and power supply; Another is connected between the NMOS pipe and earth polar that links to each other with the earth polar on final stage amplifying circuit each grade amplifying circuit before, to control switching on and off of described NMOS pipe and earth polar; Between the input and earth polar that the 3rd is connected the afterbody amplifying circuit.And increase a control signal newly and control described control switch respectively, and the control signal of afterbody input amplifier control switch and other control switchs is anti-phase.

Between the feedback capacity of described sampling and holding circuit and final stage amplification circuit output end, increase an alternative control switch newly, a control end of this switch connects the control signal of the control switch of intergrade amplifying circuit increase, and another signal input part connects reference power source.

Described control switch is that the high-low level according to switch controlling signal disconnects with closed action.

Increase a control switch that is used for zero clearing at the input of the chopped-off head amplifying circuit of described neuron sampling hold circuit.

The using method of the analogue signal sample retaining circuit of low-power consumption is that the analogue signal sample retaining circuit of described low-power consumption adopts series system to connect.

Technique effect of the present invention is: owing to increased control switch and control signal corresponding on the original analog signal sampling hold circuit.Therefore, can be according to different working conditions, make the analog sampling holding circuit be in sampling, have a rest and export three kinds of operating states, some unit in the circuit can be preserved the state of circuit because the long period does not participate in computing, allows these unit break-ofves when the needs computing, start working again, when being in resting state, the power consumption of circuit is only produced by the electric leakage of metal-oxide-semiconductor, thereby reduces power consumption.And when resting state, circuit can be kept at sampled signal before having a rest in the circuit, and when starting working once more, the sampled signal of preserving in the circuit can normally be exported.

The using method that the neuron sampling hold circuit of low-power consumption adopts series system to connect, the input signal that can make circuit is exported in mode more accurately, and has solved circuit output signal and the anti-phase problem of input signal in the past.

The present invention is further illustrated below in conjunction with drawings and Examples.

The drawing explanation

Fig. 1 is the analogue signal sample retaining circuit schematic diagram of prior art;

Fig. 2 is an analogue signal sample retaining circuit schematic diagram of the present invention;

Fig. 3 is the control signal sequential chart;

Fig. 4 is the analogue signal sample retaining circuit of the present invention schematic diagram that is connected in series.

Embodiment

Among Fig. 1, be the analogue signal sample retaining circuit of three grades of common amplifications, Cin is an input end capacitor, and M1, M2 form first order amplifying circuit, and M3, M4 form second level amplifying circuit, and M5, M6 form third level amplifying circuit, and Cf is a feedback capacity.

Among Fig. 2, a kind of analogue signal sample retaining circuit of low-power consumption comprises three-stage amplifier, sampling and holding circuit, increases by three control switch Xsw3, Xsw4, Xsw5.Xsw4 is connected between the source electrode and power supply of the PMOS pipe that links to each other with power supply in final stage amplifying circuit each grade amplifying circuit before, to control switching on and off of described PMOS pipe and power supply, Xsw3 is connected between the source electrode and earth polar of the NMOS pipe that links to each other with the earth polar in final stage amplifying circuit each grade amplifying circuit before, to control switching on and off of described NMOS pipe and earth polar, Xsw5 is connected between the input and earth polar of afterbody amplifying circuit.And increase a control signal nen newly and control described control switch Xsw3 respectively, Xsw4, Xsw5, and afterbody input amplifier control switch Xsw5 and other control switchs Xsw3, the control signal of Xsw4 is anti-phase.

Between the feedback capacity Cf of described sampling and holding circuit and final stage amplification circuit output end, increase an alternative control switch Xmux newly, a control end of this switch connects the control signal nen of the control switch of intergrade amplifying circuit increase, and another signal input part meets reference power source Vref.

Described control switch is that the high-low level according to control signal nen disconnects with closed action.

By control signal control switch Xsw6, carry out zero clearing termly, discharge unnecessary electric charge, when circuit arrived output state, closed control switch Xsw6 connected reference power source Vref, discharges unnecessary electric charge, to guarantee the accuracy of output signal.

Among Fig. 3, in sample states, nsw1 is that high level, nen are that high level, nsw2 can be any level as required, at resting state, nsw1 is that low level, nen are low level, nsw2 low level, and at output state, nsw1 is that low level, nen are that high level, nsw2 are high level.

When sample states, nsw1 is that high level, nen are that high level, nsw2 can be any level as required.At this moment switch Xsw3, Xsw4 close and, switch Xsw5 disconnects, either-or switch gating contact 6, circuit can be regarded common neuron amplifier sampling hold circuit as, pipe M1, M2, M3, M4, M5, M6 are in saturation condition, at this moment the power consumption of circuit is bigger.

When resting state, nsw1 is that low level, nen are low level, nsw2 low level.At this moment switch Xsw3, Xsw4 disconnects, switch Xsw5 closure, alternative gating reference power source Vref.Because switch Xsw3 when Xsw4 disconnects, can regard switch as the very big resistance of resistance value.Therefore, the current potential of node 7 will reduce, and the current potential of node 10 raises, and the gate source voltage of pipe M1, M2, M3, M4 is reduced, and the resistance of M1, M2, M3, M4 increases, and the electric current that flows through them reduces, and their power consumption is reduced.Because the Xsw5 closure, the current potential of forced node 5 is placed near 0 current potential, make M5 by, the electric current that flows through M5, M6 will have only their leakage current, therefore, their power consumption will be very low.Input signal keeps by input capacitance Cin and C2, and when circuit arrived output state, the signal that remains on capacitor C in and the C2 was not destroyed, and can normally export.The pole plate of capacitor C f is linked on the Vref by alternative, and the accuracy that improve to keep prolongs the retention time, in addition, alternative Xmux can be when circuit be regenerated gating Vref.

At output state, nsw1 is that low level, nen, nsw2 are high level.Xsw2, Xsw3, Xsw4 closure, Xsw1, Xsw5 disconnect.At this moment circuit returns to normal condition, alternative Xmux gating node 6.There is the signal among Cin and the C2, outputs to the nout port.Pipe M1, M2, M3, M4, M5, M6 are in saturation condition, and at this moment the power consumption of circuit is bigger.

Among Fig. 4, two neuron amplifier sampling hold

circuits

11,21 that reduce power consumptions are connected in series, can guarantee that input signal export more accurately, thus the quality of raising output signal.

Claims

1, the analogue signal sample retaining circuit of low-power consumption, comprise three-stage amplifier at least, sampling and holding circuit, it is characterized in that increasing by three control switchs, one of them is connected between the PMOS pipe and power supply that links to each other with power supply on final stage amplifying circuit each grade amplifying circuit before, to control switching on and off of described PMOS pipe and power supply, another is connected between the NMOS pipe and earth polar that links to each other with the earth polar on final stage amplifying circuit each grade amplifying circuit before, to control switching on and off of described NMOS pipe and earth polar, between the input and earth polar that the 3rd is connected the afterbody amplifying circuit, and increase a control signal newly and control described control switch respectively, and the control signal of afterbody input amplifier control switch and other control switchs is anti-phase.

2, the analog signal of low-power consumption according to claim 1 adopts holding circuit, it is characterized in that between the feedback capacity of described sampling and holding circuit and final stage amplification circuit output end, increasing an alternative control switch newly, a control end of this switch connects the control signal of the control switch of intergrade amplifying circuit increase, and another signal input part connects reference power source.

3, the analogue signal sample retaining circuit of low-power consumption according to claim 1 and 2 is characterized in that described control switch is that high-low level according to switch controlling signal disconnects with closed action.

4, the analogue signal sample retaining circuit of low-power consumption according to claim 3 is characterized in that input at the chopped-off head amplifying circuit of described neuron sampling hold circuit increases a control switch that is used for zero clearing.

5, the using method of the analogue signal sample retaining circuit of a kind of claim 1 or 2 or 4 described low-power consumption is characterized in that the analogue signal sample retaining circuit of described low-power consumption adopts series system to connect.