CN1426095A - Method for forming oxide layer-nitride layer-oxide layer in single reactor - Google Patents
Method for forming oxide layer-nitride layer-oxide layer in single reactor Download PDFInfo
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- CN1426095A CN1426095A CN 01143861 CN01143861A CN1426095A CN 1426095 A CN1426095 A CN 1426095A CN 01143861 CN01143861 CN 01143861 CN 01143861 A CN01143861 A CN 01143861A CN 1426095 A CN1426095 A CN 1426095A
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- oxide layer
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Abstract
The present invention relates to process of forming oxide layer-nitride layer-oxide layer in one single reactor. The process includes providing one substrate, forming the first oxide layer on the substrate, forming the first buffering layer on the oxide layer, forming SiN layer on the first buffering layer, forming the second buffering layer on the SiN layer, and forming the second oxide layer on the second buffering layer successively.
Description
Technical field
The relevant a kind of method that in memory, forms the oxide layer-nitride layer-oxide layer structure of the present invention, particularly relevant a kind of method that in single reactor, forms the oxide layer-nitride layer-oxide layer structure.
Background technology
Flash memory is the memory product of at present tool potentiality.Because flash memory has the feature of can electricity removing (electrically erasable) and (mechanisms) able to programme, and can carry out electricity to each flash memory structure cell in the whole memory arrays (array) simultaneously removes and programming, therefore being employed widely can need can repetitive read-write memory of data, for example basic input output system of the egative film of digital camera or motherboard because of power interruptions disappears as the various data that store of both having needed.Therefore, how to promote the performance and the cost that reduces flash memory of flash memory, just become an important problem.
The traditional type flash memory structure is shown in Figure 1A.At first, it is top to limit active area to provide semiconductor ground 100, one field oxides 101 to be formed on this ground 100 by the regional area oxidizing process, and a tunnel oxide (tunnel oxide) 102 is on ground 100.One floats gate 104 on tunnel oxide 102.Tunnel oxide 102 is a dielectric layer with oxide layer-nitride layer-oxide layer (ONO) structure.The gate 104 of floating stores for polysilicon can be used as and clears data.One dielectric layer 106 is on oxide layer-nitride layer-oxide layer (ONO), control grid (control gate) 108 is on the gate of floating (floating gate) 104, and a dielectric layer 106 of oxide layer-nitride layer-oxide layer structure that comprises the sandwich kenel is at control grid 108 and float between the gate 104.Oxide layer-nitride layer-oxide layer (ONO) comprises three layers; The called after first oxide layer 106a, nitration case 106b and the second oxide layer 106c.One N type source/drain 110/112 is in ground 100 the insides, and is positioned at float gate 104 and control grid 108 next doors, and it avoids undermined with the protection electric crystal.
The feature operation of flash memory is as follows, when a positive voltage imposes on drain 112 with above the control grid 108, float above the gate 104 forcing electronics to jump near the ground at drain 112 places by ground, when the data that will eliminate this memory, be pressed on control grid 108 and a positive electricity and be pressed on source electrode 110 and make electronics jump out of tunnel oxide 102 as long as impose a negative electricity.
The oxide layer-nitride layer-oxide layer sandwich structure of traditional flash memory is shown in Figure 1B, and the step of its formation comprises provides silicomethane (SiH
4) and nitrous oxide (N
2O) with the bottom oxide layer 106A in deposited oxide layer-nitration case-oxide layer (ONO) sandwich structure, to finish when this reaction, next step provides silicomethane (SiH
4) and ammonia (NH
3) come cvd nitride layer 106B, the 3rd step provides silicomethane (SiH
4) and nitrous oxide (N
2Therefore O) deposit upper strata oxide layer 106C, finish this complete ONO sandwich structure.
Oxide layer-nitride layer-oxide layer in traditional flash memory (ONO) sandwich structure 106 be with Low Pressure Chemical Vapor Deposition between about 400 to 500 ℃, mode with batch formula (batch) is carried out deposition process in different boiler tubes, brilliant boat approximately carries 150 wafers in the process.The shortcoming of criticizing the formula mode is may cause very big Value Loss when circuit is short-circuited.
In traditional flash memory ONO structure processing procedure, must use different boiler tubes and make oxide layer and nitride layer.Different boiler tubes are used in the manufacturing of carrying out the ONO structure and consume the much time, particularly work as the heat treatment process that involves in the step of its formation, must use the reformation that drawing process is carried out structure organization, owing to drawing process needs for a long time, if in case outage will cause short circuit and loss economically.
The defective of another ONO structure is that the degree of contrast of this roughness can cause the speed obstacle of flash memory owing in the ONO structure a higher nitride layer film roughness (roughness) is arranged.
Therefore as can be known, provide a kind of method that in single reactor, forms the oxide layer-nitride layer-oxide layer structure, can improve nitration case roughness problem in the ONO structure by above prior art.
Summary of the invention
Main purpose of the present invention provides a kind of method that forms the oxide layer-nitride layer-oxide layer structure in single reactor, with increase flash memory velocity efficiency and in order to improve the problem of nitration case roughness in the ONO structure.
For for achieving the above object, the method that forms the oxide layer-nitride layer-oxide layer structure in single reactor according to an aspect of the present invention is characterized in may further comprise the steps: a ground is provided; Form one first oxide layer on this ground; Form one first resilient coating on this first oxide layer; Form a nitration case on this first resilient coating; Form one second resilient coating on this nitration case; And form one second oxide layer on this second resilient coating.
The method of formation oxide layer-nitride layer-oxide layer structure according to a further aspect of the invention is characterized in may further comprise the steps: a ground is provided; Form one first oxide layer on this ground, wherein this first oxide layer is to form via importing silane and nitrous oxide gas; Form one first silicon oxynitride layer on this first oxide layer, wherein this first silicon oxynitride layer is to form by importing silane, nitrous oxide and ammonia gas; Form a nitration case on this first resilient coating, wherein this silicon nitride layer is to form by importing silane and ammonia gas; Form one second silicon oxynitride layer on this nitration case, wherein this second silicon oxynitride layer is to form by importing silane, nitrous oxide and ammonia gas; And form one second oxide layer on this second silicon oxynitride layer, and wherein this second oxide layer is to form by importing silane and nitrous oxide gas, wherein this above-mentioned layer is formed in single reactor and the single brilliant unit.
For clearer understanding purpose of the present invention, characteristics and advantage, preferred embodiment of the present invention is elaborated below in conjunction with accompanying drawing.
Description of drawings
Flash memory has one oxide layer-nitride layer-oxide layer structural representation to Figure 1A in traditional technology in order to use;
Figure 1B is the oxide layer-nitride layer-oxide layer structural representation;
Fig. 2 A is the construction schematic diagram of expression preferred embodiment flash memory of the present invention; And
Fig. 2 B is the structural representation of the oxide layer-silicon oxynitride layer-nitration case-silicon oxynitride layer-oxide layer of expression flash memory.
Embodiment
Some embodiments of the present invention will be described in detail as follows.Yet except describing in detail, the present invention can also be widely implements at other embodiment, and scope of the present invention do not limit by it, and is as the criterion with the claim that claims were limited.
In addition, the different piece of semiconductor element is not drawn according to size.Some yardstick is compared with other scale dependents and is exaggerated, so that clearer description and understanding of the present invention to be provided.
Though here the embodiment of Huaing shows in the two dimension of different phase to have the width and the degree of depth, should be well understood to very much shown zone is the some of the three-dimensional structure cell (cell) of wafer, and wherein wafer may comprise many structure cells of arranging in three dimensions.Relatively, when making actual element, illustrated zone has three-dimensional length, width and height.
Shown in Fig. 2 A, be flash memory structure of the present invention.At first, it is top to limit active area to provide a ground 200, one field oxides 201 to be formed on this ground 200 by the regional area oxidizing process, and a tunnel oxide (tunnel oxide) 202 is on ground 200.Semiconductor substrate 200 comprises silicon at least.One floats gate 204 on tunnel oxide 202.Tunnel oxide 202 is a dielectric layer with ONO structure 206.The gate 204 of floating stores for polysilicon can be used as and clears data.Control grid (control gate) 208 is on the gate of floating (floating gate) 204, and the dielectric layer 206 that comprises oxide layer-oxynitride layer-nitration case-oxynitride layer-oxide layer (O-SiON-N-SiON-O) is at control grid 208 and float between the gate 204.Oxide layer-oxynitride layer-nitration case-oxynitride layer-oxide layer comprises five layers; The called after first oxide layer 206a, the first resilient coating 206b, nitration case 206c, the second resilient coating 206d are with the second oxide layer 206e.One N type source/drain 210/212 is in ground 200 the insides, and is positioned at float gate 204 and control grid 208 next doors, and it avoids undermined with the protection electric crystal.
The feature operation of flash memory is as follows, when a positive voltage imposes on drain 212 with above the control grid 208, float above the gate 204 forcing electronics to jump near the ground at drain 212 places by ground, when the data that will eliminate this memory, be pressed on control grid 208 and a positive electricity and be pressed on source electrode 210 and make electronics jump out of tunnel oxide 202 as long as impose a negative electricity.
Shown in Fig. 2 B, the oxide layer-silicon oxynitride layer of flash memory of the present invention-silicon nitride layer-silicon oxynitride layer-oxide layer structure.Oxide layer-silicon oxynitride layer-silicon nitride layer-silicon oxynitride layer-oxide layer structure 206 comprises that the first oxide layer 206a is covered on the gate 204 of floating.The first resilient coating 206b is covered on the first oxide layer 206a.Nitration case 206c is covered on the first resilient coating 206b.The second resilient coating 206d is covered on the nitration case 206c.The second oxide layer 206e is covered on the second resilient coating 206d.Deposited oxide layer-silicon oxynitride layer-nitration case-silicon oxynitride layer-oxide layer structure 206 is in the single brilliant unit of single reactor.It similarly is the NROM element that oxide layer-silicon oxynitride layer-nitration case-silicon oxynitride layer-oxide layer structure 206 also can be applicable to other elements with ONO structure.
The first oxide layer 206a is formed on the gate 204 of floating, and thickness is approximately between 30 to 100 dusts, by continuous importing silane (SiH
4) between about 5 to 200 seconds of the gas with nitrous oxide (N
2O) between about 5 to 200 seconds of the gas.The deposition rate of the first oxide layer 206a is approximately between 5 to 200 (dusts/second).The flow of silane gas is approximately between 0.1 to 100sccm.The flow of nitrous oxide gas is approximately between 10 to 100sccm.The first oxide layer 206a forms by Low Pressure Chemical Vapor Deposition.The low-pressure chemical vapor deposition step is carried out under 500 to 2000 ℃ greatly.In the present embodiment, the optimum temperature that deposits this layer is 800 ℃.
The first resilient coating 206b is formed on the first oxide layer 206a, and thickness is approximately between 0.5 to 5 dust.Form and pass through to import continuously silane (SiH by Low Pressure Chemical Vapor Deposition
4) between about 0.5 to 20 second of the gas, nitrous oxide (N
2O) between about 0.5 to 20 second of the gas with ammonia (NH
3) between about 0.5 to 20 second of the gas.The deposition rate of the first resilient coating 206b is approximately between 0.1 to 5 (dust/second).The low-pressure chemical vapor deposition processing procedure carries out under 500 to 2000 ℃ greatly.In the present embodiment, the optimum temperature that deposits this layer is 800 ℃.The flow of silane gas is approximately between 0.1 to 100sccm.The deposition rate of nitrous oxide gas is approximately between 0.1 to 5 (dust/second).The flow of nitrous oxide gas is approximately between 0.1 to 1000sccm.The flow of ammonia gas is approximately between 0.1 to 1000sccm.The first resilient coating 206b is a silicon oxynitride layer.Depositing the first resilient coating 206b by reducing the supply of nitrous oxide step by step, simultaneously, increase the quantity delivered of ammonia step by step, is to provide silane gas for reaction continuously in this step.
The second resilient coating 206d is formed on the nitration case 206c, and thickness is approximately between 0.5 to 5 dust.Form and pass through to import silane (SiH by Low Pressure Chemical Vapor Deposition
4) between about 0.5 to 20 second of the gas, nitrous oxide (N
2O) between about 0.5 to 20 second of the gas with ammonia (NH
3) between about 0.5 to 20 second of the gas.The deposition rate of the second resilient coating 206d is approximately between 0.1 to 5 (dust/second).The low-pressure chemical vapor deposition step is carried out under 500 to 2000 ℃ greatly.In the present embodiment, the optimum temperature that deposits this layer is 800 ℃.The flow of silane gas is approximately between 0.1 to 100sccm.The flow of nitrous oxide gas is approximately between 0.1 to 1000seem.The deposition rate of ammonia gas is approximately between 0.1 to 1000 (dust/second).The flow of ammonia gas is approximately between 0.1 to 1000sccm.The second resilient coating 206d is a silicon oxynitride layer.Deposit the second resilient coating 206d by reducing the quantity delivered of ammonia step by step, simultaneously, increase the quantity delivered of nitrogen oxide (oxide nitride) step by step.Also provide silane (silane) gas for reaction continuously in this step.
The second oxide layer 206e is formed on the second resilient coating 206d, and thickness is approximately between 30 to 100 dusts, by continuous importing silane (SiH
4) between about 5 to 200 seconds of the gas with nitrous oxide (N
2O) between about 5 to 200 seconds of the gas.The deposition rate of the second oxide layer 206e is approximately between 0.1 to 20 (dust/second).The flow of silane gas is approximately between 0.1 to 100seem.The flow of nitrous oxide gas is approximately between 10 to 1000sccm.The second oxide layer 206e forms by Low Pressure Chemical Vapor Deposition.The low-pressure chemical vapor deposition step is carried out under 500 to 2000 ℃ greatly.In the present embodiment, the optimum temperature that deposits this layer is 800 ℃.Deposit the second oxide layer 206e by stopping the supply of ammonia, the supply of nitrogen oxide (oxide nitride) only is provided.Provide silane (silane) gas for reaction simultaneously in this step.
Therefore, can in original ONO structure, add smooth resilient coating silicon oxynitride layer (SiON) to reduce the excessive situation of border roughness.Silicon oxynitride layer between first oxide layer and nitration case (SiON) has and just begins oxygen containing composition, gradually enter into nitrogenous composition, up to becoming nitrogenous composition fully.Under the middle situation of the nitrogenate layer and second oxide layer, then there is second silicon oxynitride layer (SiON) to have and just begins nitrogenous composition, little by little enter into oxygen containing composition, up to becoming complete oxygen containing composition.This smooth resilient coating can be found out by the variation of reflection coefficient, just having begun first oxidation is 1.46 layer by layer, and the reflection coefficient that becomes nitride layer 2.0 gradually, in oxide layer-silicon oxynitride layer-nitride layer-silicon oxynitride layer-oxide layer (O-SiON-N-SiON-O) structure, first silicon oxynitride layer (SiON) has a reflection coefficient to taper to 1.46 by 2.0, and second silicon oxynitride layer (SiON) has a reflection coefficient to taper to 2.0 by 1.46.
Silicon oxynitride (SiON) layer is to be used as resilient coating between oxide layer-nitride layer-oxide layer (ONO) to reduce layer the roughness with interlayer between oxide layer-nitride layer and nitride-oxide layer.
Comprehensive the above, the present invention is in the traditional flash memory in the oxide layer-nitride layer-oxide layer structure, one oxide layer-silicon oxynitride layer-nitration case-silicon oxynitride layer-oxide layer (O-SiON-N-SiON-O) structure is provided, forming the smooth two-layer silicon oxynitride layer (SiON) of resilient coating generation is positioned in the middle of first oxide layer-nitration case and nitration case-second oxide layer, smooth resilient coating is to be used for the roughness of oxide layer-nitration case-thin oxide layer in the traditional structure, and promotes the velocity efficiency of flash memory.Make the roughness on border be improved, and manufacture process is carried out in the first single boiler tube of single crystalline substance, this manufacture process is finished oxide layer-silicon oxynitride layer-nitration case-silicon oxynitride layer-oxide layer (O-SiON-N-SiON-O) structure in the mode of finishing single brilliant unit in the same boiler tube, and reduces in batch formula manufacture process because the massive losses that down circuitry caused.
The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from that the equivalence finished under the disclosed spirit changes or equivalence is replaced, and all should be included in the claim that claims limit.
Claims (10)
1. method that forms the oxide layer-nitride layer-oxide layer structure in single reactor is characterized in that may further comprise the steps:
One ground is provided;
Form one first oxide layer on this ground;
Form one first resilient coating on this first oxide layer;
Form a nitration case on this first resilient coating;
Form one second resilient coating on this nitration case; And
Form one second oxide layer on this second resilient coating.
2. the method for claim 1 is characterized in that, this first oxide layer is to form by importing silane and nitrous oxide gas.
3. the method for claim 1 is characterized in that, this first resilient coating is a silicon oxynitride layer.
4. method as claimed in claim 3 is characterized in that, this first resilient coating is to form by importing silane, nitrous oxide and ammonia gas.
5. the method for claim 1 is characterized in that, this nitration case is to form by importing silane and ammonia gas.
6. the method for claim 1 is characterized in that, described second resilient coating is a silicon oxynitride layer.
7. method as claimed in claim 6 is characterized in that, this second resilient coating is to form by importing silane, nitrous oxide and ammonia gas.
8. the method for claim 1 is characterized in that, described this second oxide layer is to form by importing silane and nitrous oxide gas.
9. the method for claim 1 is characterized in that, described oxide layer-nitride layer-oxide layer structure is to form in single brilliant unit.
10. method that forms the oxide layer-nitride layer-oxide layer structure is characterized in that may further comprise the steps:
One ground is provided;
Form one first oxide layer on this ground, wherein this first oxide layer is to form via importing silane and nitrous oxide gas;
Form one first silicon oxynitride layer on this first oxide layer, wherein this first silicon oxynitride layer is to form by importing silane, nitrous oxide and ammonia gas;
Form a nitration case on this first resilient coating, wherein this silicon nitride layer is to form by importing silane and ammonia gas;
Form one second silicon oxynitride layer on this nitration case, wherein this second silicon oxynitride layer is to form by importing silane, nitrous oxide and ammonia gas; And
Form one second oxide layer on this second silicon oxynitride layer, wherein this second oxide layer is to form by importing silane and nitrous oxide gas, and wherein this above-mentioned layer is formed in single reactor and the single brilliant unit.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206747A (en) * | 2016-09-20 | 2016-12-07 | 上海华力微电子有限公司 | A kind of ONO inter polysilicon dielectric layer structure and preparation method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106206747A (en) * | 2016-09-20 | 2016-12-07 | 上海华力微电子有限公司 | A kind of ONO inter polysilicon dielectric layer structure and preparation method |
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