CN1410884B

CN1410884B - Guess execution command cancel device combined with exception treatment

Info

Publication number: CN1410884B
Application number: CN 01141496
Authority: CN
Inventors: 胡伟武; 王海洋
Original assignee: Institute of Computing Technology of CAS
Current assignee: Institute of Computing Technology of CAS
Priority date: 2001-09-27
Filing date: 2001-09-27
Publication date: 2010-04-14
Anticipated expiration: 2021-09-27
Also published as: CN1410884A

Abstract

The device includes the general purpose register and its mapper, the floating point register and its mapper and the assembly for executing the jump instruction, which writes the result back to the operation queue, based on the jump condition to carry out the judgement. The interruption handling with accuracy is adopted in the invention so as to guarantee the accuracy of the site recovery. Combining the branching error with the interruption handling as well as reducing the logic complexity are good for realizing and increasing the primary frequency. Comparing with the mechanism for canceling instruction of other processor, the invention possesses the features of the simple structure and the accuracy of the site recovery.

Description

Handle the conjecture execution command cancellation device that combines with exception

Technical field

The present invention relates to micro-processor architecture, particularly a kind of conjecture execution command cancellation device that combines with the exception processing.

Background technology

Current various microprocessor is generally taked following two kinds of schemes in the solution branch transition:

(1) time-out is got finger, comes out up to branch outcome.This way can take to add the method that postpones groove usually in order to reduce delay, but whether success generally all can cause certain delay no matter shift.As: the R4000 microprocessor of MIPS, see Joe Heinrich, MIPS R4000 MicroprocessorUser ' s manual, MIPS Technology, Inc..

(2) take to a certain degree conjecture, before branch outcome is come out, just get finger by the address of conjecture.This method does not cause time-delay when conjecture is correct, but when conjecture is wrong, will cancels the instruction of having got into and get finger again, thereby causes the streamline cutout, has increased time-delay.As: microprocessors such as the R10000 of MIPS, see Kenneth C.Yeager, The Mips R10000Superscalar Microprocessor, IEEE Micro 1996 Apr.

Second kind of scheme is the current popular scheme, adopted by most of microprocessors, and the dynamic dispatching technology of common and streamline combines.Two key problems are arranged in this scheme: the one, improve the conjecture accuracy, thereby reduce to cancel the probability of instruction.The 2nd, take effectively instruction cancellation mechanism, thus the influence that streamline is caused when reducing to guess wrong.

In current processor, the streamline that brings for fear of sequential firing blocks (because branch instruction will wait operand to be ready to just emission usually), and dynamic emission is taked in the meeting that has, as: the MIPS R10000 microprocessor of SGI/MIPS company.In R10000, branch instruction still can dynamically be launched, but thus when the wrong cancellation instruction of conjecture, has brought some problems:

(1) R10000 backups to optional address and each register in branch's storehouse (branch stack) when running into branch instruction, and in order to recovery later on, this way is brought the complicacy of steering logic and design inevitably; As shown in Figure 1, find transfer instruction, the mapping table of register and relevant control bit are saved in shift in the stack when when decoding.When prediction error, just from shift stack, recover these information.But some Cache operation is expendable.

(2) this cancellation mechanism of R10000 may be brought some spinoffs (side effects), as: the state of the Cache that nonuniformity Cache operation (non-coherent cached operations) brings and the variation of data are expendable, recover on-the-spot out of true thereby make, therefore to lean in accordance with some standards and reduce this situation, see Joe Heinrich, MIPS R10000 MicroprocessorUser ' s manual, MIPS Technology, Inc..

Summary of the invention

The purpose of this invention is to provide a kind of conjecture execution command cancellation device that combines with the exception processing, branch's mistake as a kind of special Interrupt Process, as prediction error takes place, has then been put a kind of special interruption, notify each parts to recover site disposal.

For achieving the above object, a kind of conjecture execution command cancellation device that combines with the exception processing, comprising: general-purpose register and mapping table thereof, flating point register and mapping table thereof is characterized in that also comprising:

Operation queue sends control signal;

Carry out the parts of transfer instruction, it is judged according to jump condition, and the result is write back to operation queue;

When decoding, find transfer instruction, do not do individual processing; When prediction error, produce a special interruption according to the processing mode of interrupting, instruct cancellation and scene to recover.

The Interrupt Process that the present invention adopts has accuracy, has guaranteed the accuracy of on-the-spot recovery; Because branch's mistake and Interrupt Process are combined, reduce the complexity of logic again simultaneously, be more conducive to realize and improve dominant frequency.Compare with the instruction cancellation mechanism of other processor, the present invention has the accurate characteristics in scene simple in structure.

Description of drawings

Fig. 1 is that structural drawing recovers in prior art branch.

Fig. 2 is that structural drawing recovers in branch of the present invention.

The working of an invention mode

Transfer instruction is carried out by ALU (arithmetic and logic unit) or floating-point FALU (floating point unit), and information such as shifting success or not write back to operation queue, whether result's decision of carrying out according to transfer instruction again when transfer instruction finishes cancels the follow-up operation of having guessed execution.Therefore when emission, need not wait for that operand is ready to.If the required operand of transfer instruction is not ready for, wait at reservation station as normal operations.When ALU or FALU executive condition transfer instruction, judge, and the result is write back to operation queue (for conditional branch instruction, the result is that 1 expression is shifted successfully) according to jump condition.The transfer instruction JR of goal displacement address in register, JALR etc. utilize the reservation station of ALU to wait for required destination address also by ALU.

When the jump condition of conditional transfer was determined, the operation of back may be transmitted into functional part and carry out, and the operation that has may write back.If transfer instruction is guessed wrong, the instruction after we have utilized cancellation logic that exception handles to the transfer instruction of guessing wrong is dexterously cancelled.Promptly when transfer instruction writes back, to form the ex (ex=1 represents to make an exception) of exception vector and write operation formation corresponding entry and excode (when the ex=1 according to the result, excode represents the reason that makes an exception) territory, transfer instruction is guessed wrong as a kind of special exception, the path that utilizes exception to handle when transfer instruction finishes notifies each functional part cancellation the current operation of carrying out, and cancels the instruction that get into the back.Thereby solved instruction cancellation problem.Fig. 2 provides a specific embodiment, finds transfer instruction when decoding, does not do individual processing; When prediction error, produce a special interruption according to the processing mode of interrupting, instruct cancellation and scene to recover.Because it is accurate interrupting,, recovered the logic of interrupting (in this example, represent to have interruption to take place, represent that with Excode=111111 this interruption is caused by transfer) simultaneously with EX=1 so all scenes all are accurate.

Claims

1. a conjecture execution command of handling to combine with exception is cancelled device, and comprising: general-purpose register and mapping table thereof, flating point register and mapping table thereof is characterized in that also comprising:

Operation queue sends control signal;

2. device according to claim 1 is characterized in that described transfer instruction parts comprise arithmetic and logic unit and floating point unit.

3. device according to claim 1 is characterized in that when transfer instruction finishes, and the path that utilizes exception to handle notifies each functional part cancellation the current operation of carrying out, and cancels the instruction that get into the back.