CN1410877A - High speed floating point addition and subtraction part capable of direct matching exponents and need not calculating exponential difference - Google Patents

Abstract

The assembly includes the two shifter used to shift the mantissa, the logic for comparing the magnitude of the exponent used to generate the selection signal of the result shifted, the two gates used to output the result shifted. The invention not only suits the system architecture of single channel, but also suits the system architecture of two channels. In the system architecture of two channels, the floating point adding and substracting with two steps of basic addition can be realized. In the system architecture of single channel, the floating point adding and substracting with three steps of basic addition can be realized. The invention increases the arithmetic speed of the floating point adding and subtracting.

Description

Needn't the gauge index difference and directly to the high-speed floating point plus-minus parts on rank

Technical field

The present invention relates to micro-processor architecture, particularly directly the high-speed floating point on rank is added and subtracted parts.

Background technology

Along with the increase of virtual reality, more and more higher to the rate request of floating-point operation with the multimedia application of using three-dimensional animation.The floating-point plus-minus is again a kind of operation the most basic in the floating-point operation, is to improve the key factor of whole floating-point calculation component performance so improve the speed of floating-point plus-minus parts.The most basic floating add cuts algorithm can be with reference to [seeing D.A.Patterson and J.L.Henessy.Computer Architecture.A Quantitative Approach.Morgan KaufmannPublishers, second edition. (1996)], mainly comprise following 8 steps:

1. the index that calculates two floating numbers is poor.

2. according to the move to right mantissa of the little floating number of index of the index difference of two floating numbers, realize rank.

3. mantissa's summation.

4. if mantissa and be negative is so to mantissa and supplement sign indicating number.

Mantissa and in first position probing of 1 (Leading-one detection).

6. mantissa and normalization.

7. round off.

8. cause the result to shift out if round off, so again normalization.

At present existing many gordian techniquies are used to reduce the delay of whole floating-point plus-minus parts, to improve the arithmetic speed of floating-point plus-minus parts, picture binary channel (Two-path) algorithm, monic position prediction (leading one prediction, LOP) algorithm, algorithm and floating-point that some are advanced plus-minus architecture etc. in advance rounds off.

The binary channel algorithm is about to an original floating add subtrahend and is divided into two data paths according to path: CLOSE path and FAR path.The CLOSE path is handled the index difference smaller or equal to 1 subtraction, and the FAR path is handled the index difference greater than subtraction and all additive operations of 1.On two data paths of binary channel algorithm, realize rank and normalization are all only needed a single place shift device and a total length shift unit.The logic of single place shift device is simply more than the total length shift unit, is needing two total length shift units to compare so cut algorithm with basic floating add in rank and the normalization process, and the delay that a total length shift unit of binary channel algorithm adds a single place shift device is littler.

The LOP algorithm can make several processes and mantissa ask to add parallel the execution, direct first position of one after two operands prediction summations, thus avoided summation and several one serial structure, hidden several one delay.

Rounding off in advance was meant before normalization and does earlier and round off, and calculate mantissa and in, calculate all possible round-off result, rounding procedure only needs to select one according to the logic that rounds off (can with mantissa sue for peace parallel computation) from existing result.Need take into full account normalized influence during owing to round off, can also avoid standardizing again so round off in advance.

Also have some optimizations in addition, can compare mantissa's size concurrently in the time of such as the gauge index difference, thereby obtain the sign bit of net result, just needn't consider in the calculating process like this-symbol of operand, simplified processing logic floating-point plus-minus architecture.Again by the swap operation number, guarantee mantissa and be positive number all the time, omitted a step of mantissa and supplement.In addition, can simplify mantissa and supplement sign indicating number process,, have promptly when the mantissa of A-B be negative according to following equation $-(A-B)=\stackrel{\‾}{A+\stackrel{\‾}{B}},$ Because A-B is obtained by A+ B+1, and in order to round off in advance, A+ B and A+ B+1 have been calculated simultaneously, so can avoid adding in the complementary process one delay by A+ B negate is realized mantissa and supplement.

At list of references (S.F.Oberman, M.J.Flynn.A Variable Latency PipelinedFloating-Point Adder.Technical Report No.CSL-TR-96-689 ComputerSystems Laboratory, Stanford University, February 1996.) in provided the architecture of binary channel floating-point plus-minus parts shown in Figure 1.If an addition or total length displacement are defined as a basic addition step-length (addition step), so in these binary channel floating-point plus-minus parts, the delay of FAR path is three addition step-lengths, and the delay of CLOSE path is two addition step-lengths.

In existing various processors, floating-point plus-minus parts generally adopt the unipath structure.The architecture of the unipath floating-point plus-minus parts that in MipsR10000, provide as shown in Figure 2, total delay is four addition step-lengths.

From Fig. 1 and Fig. 2 as can be seen, adopted the advanced technology of introducing above, postpone to reduce greatly, the delay of the floating-point plus-minus parts of forms data path changes 4 addition step-lengths into by 8 basic addition step-lengths in the original floating-point plus-minus rudimentary algorithm, 3 addition step-lengths are reduced in the delay of binary channel algorithm, but in order to satisfy the continuous growth of various application to the floating-point operation rate request, the speed of floating-point plus-minus arithmetic unit also needs further raising.Two kinds of architectures of synthesizing map 1 and Fig. 2, as can be seen, no matter in existing unipath still was the binary channel architecture, critical path had all comprised two addition step-lengths: ask the index difference and to rank.

Summary of the invention

The purpose of this invention is to provide a kind of needn't the gauge index difference and,, construct a floating-point more at a high speed and add and subtract parts so that shorten the operating delay of floating-point plus-minus parts directly to the high-speed floating point plus-minus parts on rank, thereby improve the operation efficiency of whole floating point unit.

For achieving the above object, high-speed floating point plus-minus parts the rank process is comprised:

Two shift units are used to the mantissa that is shifted;

The exponential size Compare Logic is used to generate shift result and selects signal;

Two gates are used to export the result after the displacement.

The present invention is not only applicable to the unipath architecture, also be applicable to the binary channel architecture, in the binary channel architecture, can realize having only the floating-point plus-minus of two basic addition step-lengths, in unipath architecture, can realize the floating-point plus-minus of three basic addition step-lengths, further improve floating-point plus-minus arithmetic speed.

Description of drawings

For ease of more clearly introducing feature of the present invention, effect and implementation, the present invention will be further described below in conjunction with accompanying drawing.

Fig. 1 is conventional binary channel floating-point plus-minus element architecture figure.

Fig. 2 is conventional unipath floating-point plus-minus element architecture figure.

Fig. 3 is binary channel floating-point plus-minus element architecture figure of the present invention.

Fig. 4 is unipath of the present invention floating-point plus-minus element architecture figure.

Fig. 5 is of the present invention to rank process one-piece construction figure.

Fig. 6 is the structural drawing to shift unit in the process of rank of the present invention.

Fig. 7 displacement output logic of one digit number certificate wherein when carrying out 16 bit shifts in the shift unit of the present invention.

The working of an invention mode

From Fig. 3 and Fig. 1, Fig. 4 and Fig. 2 more as can be seen, gauge index difference process is omitted in Fig. 3 and Fig. 4 among Fig. 1 and Fig. 2, therefore adopt provided by the invention as shown in Figure 3 and Figure 4 needn't the gauge index difference and directly to the method on rank, can will ask the index difference on the critical path among Fig. 1 and Fig. 2 and the delay of two the addition step-lengths in rank be shortened to an addition step-length, thereby reduce the time delay of critical path.

Fig. 5 provides is one-piece construction figure to the rank process, mainly comprise two shift units, because it is former unlike size than two operand indexes to rank, so can't judge that the index of which operand is less and only less index is shifted, therefore must be shifted to two mantissa simultaneously.The size of two operand indexes relatively can with mantissa's parallel processing that is shifted, select correct shift result according to the size that obtains two operand indexes more at last.Such as the index of the operand A index greater than operand B, the output of gate 1 should be the result after the displacement of B mantissa so, and gate 2 is output as the mantissa of the A that remains unchanged.

Fig. 6 is the structural drawing to shift unit in the process of rank, and it realizes the displacement to mantissa in the process of rank.With generally different to the rank shift unit, its input is not shifted data and number of shift bits, but shifted data and two indexes.In shift unit inside, the operand index of giving tacit consent to this mantissa's correspondence is one less in two operand indexes, because otherwise should be to this mantissa's displacement.Introduce in detail the realization mechanism of the shift unit (corresponding displaced device 1 in Fig. 5) that the mantissa to operand A is shifted below in conjunction with Fig. 6, in current shift unit, give tacit consent to A＜B.

The shift unit that among Fig. 6 rank is used is a shift unit stage by stage, at first carries out the single place shift of mantissa, carries out two bit shifts then, four bit shifts, eight bit shifts, sixteen bit displacement, 32 bit shifts and 64 bit shifts.Conditional indicator is respectively ExpA=a ₁₀a ₉a ₈a ₇a ₆a ₅a ₄a ₃a ₂a ₁a ₀And ExpB=b ₁₀b ₉b ₈b ₇b ₆b ₅b ₄b ₃b ₂b ₁b ₀The steering logic of single place shift can be from a so ₀, b ₀Obtain.One lt steering logic $\mathrm{LeftShift}1=a_0\stackrel{\‾}{b_0},$ A is worked as in expression ₀=1, b ₀=0 o'clock, if A aligns to B, index was to reduce so, and mantissa just should increase, so mantissa should move to left 2 ⁰=1.One gt steering logic $\mathrm{RightShift}1=\stackrel{\‾}{a_0}{b}_0$ A is worked as in expression ₀=0, b ₀=1 o'clock, if A aligns to B, index was to increase so, and mantissa just should reduce, so mantissa should move to right 2 ⁰=1.The steering logic of other two, four, eight and sixteen bit displacement and the steering logic of single place shift are identical, just use index respectively the 1st, 2,3,4.Because by one, two, four, eight and sixteen bit displacement, can shift out 31 bit data to the left or to the right at most, and move into again in these data may be afterwards 32 or 64 bit shifts, so the input 115 bit shift data in except comprising a mantissa of 53 that will be shifted, about mantissa, also respectively put 31 0, be used to preserve the data that shift out.

32, the major function of 64 bit shift steering logics is to obtain three variate-values, first variable R ightShift32 represents whether need 32 gts, second variable R ightShift64 represents whether need 64 gts, and the 3rd variable SelAlignRes represents whether select shift result.

Definition diff=b ₁₀b ₉b ₈b ₇b ₆b ₅b ₄b ₃b ₂b ₁b ₀-a ₁₀a ₉a ₈a ₇a ₆a ₅a ₄a ₃a ₂a ₁a ₀, high 5 difference is diff1=b ₁₀b ₉b ₈b ₇b ₆-a ₁₀a ₉a ₈a ₇a ₆, the 5th difference is diff2=b ₅-a ₅, low 5 difference is diff3=b ₄b ₃b ₂b ₁b ₀-a ₄a ₃a ₂a ₁a ₀, diff=diff1*64+diff2*32+diff3 is arranged so.Because acquiescence A＜B is so only consider the situation of diff＞0.Below the various values of diff are discussed respectively to obtain the logical expression of top three variablees.

If diff1＞1, high 5 contributions to diff of index are greater than 2 * 64=128 so, and no matter low 6 get any numerical value, low 6 to the contribution of diff necessarily between-63 and 63, so the index of two operands poor 〉=128-63=65＞64.When the index difference greater than 64 the time because the significance bit of mantissa has only 53, so mantissa all shifts out certainly, need not be shifted just can directly obtain the result, comprises 55 0 and sticky positions.The Sticky position is every or a logic of 53 mantissa, comprises one 1 at least in the expression shift-out bit, is mainly used in and rounds off.

If diff1=1, so high 5 indexes are 1 * 64=64 to the contribution of diff.Work as a ₅=0, b ₅=1, promptly during diff2=1, the 5th contribution to diff of index is 1 * 32=32.No matter low 5 is any numerical value, and low 5 contributions to diff are necessarily between-31 and 31.So this moment diff 〉=64+32-31=65＞64, processing in this case is identical with the situation of diff1＞1, can indirect assignment, do not fetch data from shift unit.Work as a ₅=1, b ₅=0, promptly during diff2=-1, high 6 indexes are 64-32=32 to total contribution of diff, and at this moment mantissa need carry out 32 gts on the basis one, two, four, eight, sixteen bit displacement.Work as a ₅=b ₅The time, diff2=0, high 6 total contributions to diff are 64, at this moment mantissa need carry out 64 gts on the basis one, two, four, eight, sixteen bit displacement.

If diff1=0 is when so high 5 indexes are 0 to the contribution of diff.Because acquiescence diff＞0 is so only analyze the situation of diff2＞=0.Work as a ₅=0, b ₅=1, promptly during diff2=1, the 5th contribution to diff of index is 32, so whole high 6 indexes are 32 to the contribution of diff, need carry out 32 gts on the basis one, two, four, eight, sixteen bit displacement.Work as a ₅=0, b ₅=0 when being diff2=1, and high 6 indexes are 0 to the contribution of diff, and mantissa does not make 32 or 64 bit shifts.

Above comprehensive to the discussion under three kinds of spans of diff1, the expression formula that can obtain the steering logic of 32 and 64 bit shifts and whether select three variablees such as shift result.

Definition $g_i=a_i\stackrel{\‾}{b_i},s_i=\stackrel{\‾}{a_i}{b}_i,e_i=a_i{b}_i+\stackrel{\‾}{a_i{b}_i}.$ Diff1=1 can represent with following formula:

diff1_eq_1＝e[10]e[9]e[8]e[7]s[6]+

e[10]e[9]e[8]s[7]g[6]+

e[10]e[9]s[8]g[7]g[6]+

e[10]s[9]g[8]g[7]g[6]+

S[10] g[9] g[8] g[7] g[6]; Diff1=0 can represent with following formula:

Diff1_eq_0=e[10] e[9] e[8] e[7] e[6]; Select shift result variable sel_alignres:

SelAlignRes=diff1_eq_1 (g5+e5)+diff1_eq_0 s5; 32 the steering logic of moving to right is:

RightShift32=diff1_eq_1 g5+diff1_eq_0_s5; 64 the steering logic of moving to right is:

RightShift64＝diff1_eq_1e5。

Be identical from single place shift to six 14 logic with shift realization mechanisms among Fig. 6,, provided wherein one the displacement output logic in the 115 bit shift data so be example with the sixteen bit displacement at Fig. 7.

Claims (4)

1. One kind needn't the gauge index difference and, it is characterized in that comprising directly to the high-speed floating point plus-minus parts on rank:

   Two shift units are used to the mantissa that is shifted;

   The exponential size Compare Logic is used to generate shift result and selects signal;

   Two gates are used to export the result after the displacement.
2. 2. by the described parts of claim 1, it is characterized in that it is one less in two operand indexes that described shift unit is given tacit consent to the operand index of this mantissa's correspondence.
3. 3. by the described parts of claim 1, it is characterized in that described shift unit is the segmentation shift unit.
4. 4. by the described parts of claim 3, it is characterized in that described segmentation shift unit at first carries out one, two, four, eight, the displacement of sixteen bit mantissa according to low 5 of two indexes, and calculate 32 and 64 logic controls that are shifted by high 6 of index concurrently, then, finish 32 and the displacement of 64 mantissa according to 32 and 64 s' steering logic.

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