CN1407626A - Vertical Nitride ROM - Google Patents

Abstract

A vertical nitride read-only memory unit is composed of a substrate with a ditch, a grid with a horizontal part covering the substrate and a vertical part embedded in the ditch and with one end adjacent to the horizontal part, a capture layer between the grid and the substrate, the first source/drain region in the substrate at another end of the vertical part of the grid, and the second source/drain region in the substrate at the edge of the ditch and connected with the vertical part and the horizontal part of the grid.

Description

Vertical Nitride ROM

technical field

The present invention relates to the structure of a semiconductor device, in particular to a nitride read-only memory cell (Nitride Read-Only-Memory cell, NROM cell) with a vertical structure.

Background technique

Known nitride read-only memory devices, in memory devices with metal oxide semiconductor transistors, use, for example, a silicon oxide-silicon nitride-silicon oxide layer (ONO layer) as a dielectric layer for trapping or trapping (Trap) charges, Then, the programming step is carried out, and the hot electrons (HotElectrons) are tunneled into the nitride layer through the silicon oxide layer under the silicon nitride layer, and through the function of trapping or trapping charges of the silicon nitride layer, and Charges are stored in the nitride layer to complete data storage. In more detail, when the programming voltage is provided to the source, drain and gate for programming, the silicon oxide-silicon nitride-silicon oxide layer above the channel region is affected by the programming voltage, while Hot electrons are collected in the nitride layer through the underlying silicon oxide layer.

In addition, in the known technology, the charge collected by the nitride layer is concentrated in the region adjacent to the source/drain, and the charge collected in the nitride layer will increase the threshold voltage (Threshold Voltage) of the channel region. When there is a concentrated charge in the memory cell (such as a programmed memory cell), the memory cell will be affected by the rise of the initial voltage, so that when the memory cell is reading data, because the read voltage is lower than The initial voltage makes the channel region a non-conductive region. Conversely, when there is no charge concentrated in the memory cell, the channel region becomes a conduction region because the read voltage exceeds the threshold voltage.

Known nitride read-only memory devices are used in read-only memory (read only memory, ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (Erasable Programmable ROM, EPROM), erasable Flash EPROM, Electrically Erasable Programmable ROM (EEPROM), or Flash Electrically Erasable Programmable ROM (FlashEEPROM). Since the nitride read-only memory device injects and traps hot electrons into the nitride layer through the channel region to program the memory cell, in the traditional programmable read-only memory device, when using the nitride read-only memory device, Deprogramming takes much longer than procedural time, increasing overall procedural and deprogramming times.

In addition, in the known nitride read-only memory devices, since the channel region is located under the gate, the length of the channel region will be gradually shortened under the requirements of faster, smaller, and denser integrated circuit design. trend to speed up device operation. However, when the length of the channel region is shortened to a certain extent, short channel effects (Short Channel Effects) and hot electron effects (Hot Electron Effects) will occur, which will lead to electrical failure of the device.

Contents of the invention

The invention provides a metal oxide semiconductor transistor structure, which can maintain better device characteristics while reducing the device size.

The invention provides a nitride read-only memory device structure, wherein the nitride read-only memory has a vertical structure, so that the channel area is distributed along the vertical direction, so as to effectively reduce the size of the device.

The invention provides a nitride read-only memory device structure, wherein the bit lines are distributed along the X direction, so as to further reduce the size of the device.

The invention provides a nitride read-only memory device structure, which can effectively reduce the joint capacitance of the device by increasing the length of the channel region, and at the same time improve the performance of the nitride read-only memory device and reduce the size of the device.

In order to achieve the above object, the present invention proposes a vertical nitride read-only memory cell, the structure of which includes a base with a trench, a horizontal portion covering the base, and a gate embedded in the trench with a vertical portion adjacent to the horizontal portion at one end. , a capture layer between the gate and the substrate, a first source/drain region in the substrate at the other end of the vertical portion of the gate, and a vertical and horizontal portion in the substrate at the edge of the trench and connected to the gate connected to the second source/drain region.

It can be known from the above that the required area of the vertical read-only memory device of the present invention is much smaller than that of the conventional horizontal read-only memory device, therefore, a highly dense memory device can be obtained.

It can be known from the above that the channel region of the present invention extends along the vertical direction, so the bit line extends along the X direction, which can further reduce the size of the nitride read-only memory cell.

From the above, it can be seen that the channel region of the present invention extends along the vertical direction, so the length of the channel region can be adjusted with the adjustment of the trench depth, thereby effectively reducing the demand for junction capacitance. Moreover, while reducing the size of the device, the occurrence of the short channel effect can be avoided, thereby effectively improving the stability of the device.

As can be seen from the above, the present invention can effectively reduce the resistance-capacitance delay time (RC delay time) while reducing the junction capacitance, therefore, can effectively increase the operating speed of the device, and then improve the performance of the device.

Description of drawings

1 to 6 are schematic diagrams of the manufacturing process of a vertical nitride read only memory cell according to a preferred embodiment of the present invention. Explanation of reference signs:

100: Semiconductor substrate

102: Ditch

103: Ion implantation

104: first source/drain region

106: Second source/drain region

108: General source/drain region

110, 114: Silicon dioxide layer

112: Silicon nitride layer

116: Gate conductor layer

Detailed ways

The invention describes the structure and manufacturing method of the vertical nitride read-only memory unit. Referring to FIG. 1 , a semiconductor substrate 100 is provided, and a trench 102 is formed in the semiconductor substrate 100 . The method of forming the trench 102 is, for example, using a conventional lithographic etching method, and a preferred etching method is, for example, using a suitable plasma gas mixture to perform anisotropic etching. In addition, additional treatment may also be performed, such as using a dilute H ₂ O ₂ solution to remove unnecessary oxides formed on the surface of the substrate 100 during the anisotropic etching process. In addition, as the etching production method, wet etching may be performed using an appropriate wet etchant. Next, a channel region ion implantation step (not shown) is performed to adjust the threshold voltage. For example, the channel region ion implantation method using the oblique angle implantation technique, using a dose between 3×10 ¹¹ ions/cm² and 5×10 ¹³ ions/cm² and an energy between 5KeV and 50KeV , implanting ions such as boron or boron fluoride into NMOS devices, or implanting ions such as arsenic or phosphorus into PMOS devices.

Next, referring to FIG. 2 , ion implantation 103 is performed to form a first source/drain region 104 and a second source/drain region 106 in the substrate at the edge of the trench, and a substrate at the bottom of the trench 102 A general source/drain region 108 is formed in the . The implantation method of the source/drain regions 104, 106, 108 is, for example, using a dose between 5×10 ¹² ions/cm 2 and 2×10 ¹⁶ ions/cm 2 and a temperature between 5 KeV and 80 KeV. Energy for implantation of boron fluoride, arsenic or phosphorus ions. In addition, after forming the source/drain regions 104, 106, 108, a heat treatment is performed to heat the device to 800°C between 10 seconds (rapid thermal response (RTA), high temperature) and 60 minutes (low temperature). degrees to 1100 degrees Celsius to activate the implanted dopant.

Next, as shown in FIGS. 3 to 5 , a capture layer is formed on the substrate and the trench. As shown in FIG. 5 , for example, a capture layer composed of silicon dioxide layer 110 -silicon nitride layer 112 -silicon dioxide layer 114 is formed on the substrate 100 and the trench 102 (shown in FIG. 1 ). Please refer to FIG. 3 , under the low temperature oxidation operation, a bottom silicon dioxide layer 110 with a thickness of 50 angstroms to 150 angstroms is formed on the substrate 100 and the trench 102 (as shown in FIG. 1 ), and the bottom two The preferred thickness of the silicon oxide layer 110 is about 80 angstroms. The oxidation temperature is between 750°C and 1000°C, preferably around 800°C.

Next, as shown in FIG. 4 , a silicon nitride layer 112 with a thickness between 20 angstroms and 150 angstroms is covered on the bottom silicon dioxide layer 110 by chemical vapor deposition, and the silicon nitride layer 112 is thicker. The optimum thickness is about 100 Angstroms. In addition, although the method of forming the silicon nitride layer 112 is described by taking the chemical vapor deposition method as an example, it is not limited thereto, and other deposition methods can also be used instead.

Next, as shown in FIG. 5 , a top silicon dioxide layer 114 is formed on the silicon nitride layer 112 by thermal oxidation. Although the method of forming the top silicon dioxide layer 114 is described by taking the thermal oxidation method as an example, it is not limited thereto, and a deposition method or a combination method can also be used instead. It should be noted that during the formation of the top silicon dioxide layer 114 by thermal oxidation, part of the silicon nitride layer 112 will be consumed, and the consumed thickness of the silicon nitride layer 112 is half of the formed thickness of the top silicon dioxide layer 114 . Therefore, if the predetermined formation thickness of the top silicon dioxide layer 114 is 100 angstroms, the thickness of the silicon nitride layer 112 is at least 50 angstroms greater than the final required thickness of the silicon nitride layer 112, in order to consume additional nitride silicon to form the top silicon dioxide layer 114. In addition, the preferred thickness of the top silicon dioxide layer 114 is 50 angstroms to 150 angstroms.

Next, please refer to FIG. 6 , on the substrate 100 , a gate conductor layer 116 is covered, and the trench 102 is filled (as shown in FIG. 1 ). The gate conductor layer 116 is, for example, a doped polysilicon layer. The gate conductor layer 116 is formed by, for example, using low pressure chemical vapor deposition (LPCVD) to cover a layer of undoped polysilicon layer on the substrate, and then implant active dopants into the undoped polysilicon layer. In order to form a doped polysilicon layer.

From the foregoing vertical nitride ROM transistors, it can be known that the required area of the vertical ROM device is much smaller than that of the traditional horizontal structure transistor. Furthermore, it can be seen from the current design rules that a device with a smaller required area can further increase the density of the device to obtain a highly dense circuit device. Therefore, using the vertical nitride read-only memory of the present invention, a highly dense storage device can be obtained.

It can be seen from the above vertical NROM transistor that since the channel region extends along the vertical direction, the bit line extends along the X direction, so the size of the NROM cell can be further reduced.

It can be seen from the vertical nitride ROM transistor above that since the channel region extends along the vertical direction, the length of the channel region can be adjusted with the adjustment of the trench depth, thereby effectively reducing the requirement of junction capacitance. Moreover, while reducing the size of the device, the occurrence of the short channel effect can be avoided, thereby effectively improving the stability of the device.

From the above, it can be known that the present invention can effectively reduce the resistance-capacitance delay time while reducing the junction capacitance. Therefore, the operating speed of the device can be effectively increased, thereby improving the performance of the device.

Although a nitride read-only memory transistor is used for illustration in this preferred embodiment, the present invention is not limited thereto, and can also be applied to other metal-oxide-semiconductor transistors without departing from the spirit and scope of the present invention. manufacture.

Although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention, and various modifications and modifications can be made without departing from the spirit and scope of the present invention. Various changes and modifications can also be made according to the spirit and scope defined by the claims of the present invention. All the embodiments and drawings used in the present invention are only used to illustrate the present invention and are not limited thereto.

Claims (26)

1. A vertical nitride read-only memory cell, characterized in that: comprising: a base with a ditch in the base; a grid, the grid includes a horizontal portion and a vertical portion, the horizontal portion covers the substrate, the vertical portion is embedded in the trench and one end is adjacent to the horizontal portion; a capture layer, located between the grid and the substrate; a first source/drain region located in the substrate at the other end of the vertical portion; A second source/drain region is located in the base of the trench edge and connected to the vertical portion and the horizontal portion. 2. The vertical nitride read-only memory cell according to claim 1, wherein the capture layer comprises a mixed dielectric layer comprising a silicon oxide layer-silicon nitride layer-silicon oxide layer layer. 3. The vertical nitride read only memory cell as claimed in claim 2, wherein the silicon oxide layer is formed by a low temperature thermal oxidation method. 4. The vertical nitride read only memory cell as claimed in claim 2, wherein the thickness of the silicon oxide layer is between 50 angstroms and 150 angstroms. 5. The vertical nitride read only memory cell as claimed in claim 2, wherein the silicon nitride layer is formed by a low pressure chemical vapor deposition method. 6. The vertical nitride read only memory cell as claimed in claim 2, wherein the thickness of the silicon nitride layer is between 20 angstroms and 150 angstroms. 7. The vertical nitride read-only memory cell as claimed in claim 1, wherein the material of the gate comprises a doped polysilicon layer, and the doped polysilicon layer is formed from an undoped polysilicon layer simultaneously Doped. 8. The vertical nitride read-only memory cell as claimed in claim 7, wherein the method for forming the doped polysilicon layer comprises a low pressure chemical vapor deposition method. 9. A metal oxide semiconductor transistor, characterized in that: comprising: a base having a ditch therein; a gate, the gate includes a horizontal portion and a vertical portion, wherein the horizontal portion covers the substrate, the vertical portion is embedded in the trench and one end is adjacent to the horizontal portion; a dielectric layer located between the grid and the substrate; a first source/drain region located in the substrate at the other end of the vertical portion; A second source/drain region is located in the base at the edge of the trench and connected to the vertical portion and the horizontal portion. 10. The metal-oxide-semiconductor transistor as claimed in claim 9, wherein the dielectric layer comprises a mixed dielectric layer, and the mixed dielectric layer comprises a silicon oxide layer-silicon nitride layer-silicon oxide layer. 11. The metal oxide semiconductor transistor according to claim 10, wherein the method for forming the silicon oxide layer comprises a low temperature thermal oxidation method. 12. The metal oxide semiconductor transistor as claimed in claim 10, wherein the thickness of the silicon oxide layer is between 50 angstroms and 150 angstroms. 13. The metal oxide semiconductor transistor as claimed in claim 10, wherein the silicon nitride layer is formed by a low pressure chemical vapor deposition method. 14. The metal oxide semiconductor transistor as claimed in claim 10, wherein the thickness of the silicon nitride layer is between 20 angstroms and 150 angstroms. 15. The metal oxide semiconductor transistor as claimed in claim 9, wherein the dielectric layer comprises a silicon oxide layer. 16. The metal oxide semiconductor transistor as claimed in claim 9, wherein the material of the gate comprises a doped polysilicon layer, and the doped polysilicon layer is simultaneously doped from an undoped polysilicon layer. 17. The metal oxide semiconductor transistor as claimed in claim 16, wherein the method for forming the doped polysilicon layer comprises a low pressure chemical vapor deposition method. 18. A vertical nitride read-only memory cell, characterized in that: comprising: a base having a ditch therein; A gate, the gate includes a horizontal portion and a vertical portion, wherein the horizontal portion covers the substrate, the vertical portion is embedded in the trench and one end is adjacent to the horizontal portion; a capture layer, located between the grid and the substrate; a general source/drain region in the base at the other end of the vertical portion; a first source/drain region located in the base of one edge of the trench and connected to the vertical portion and the horizontal portion; A second source/drain region is located in the base of the other edge of the trench and connected with the vertical portion and the horizontal portion. 19. The vertical nitride read-only memory cell as claimed in claim 18, wherein the capture layer comprises a mixed dielectric layer comprising a silicon oxide layer-silicon nitride layer-silicon oxide layer. 20. The vertical nitride read only memory cell as claimed in claim 19, wherein the silicon oxide layer is formed by a low temperature thermal oxidation method. 21. The vertical nitride read only memory cell as claimed in claim 19, wherein the thickness of the silicon oxide layer is between 50 angstroms and 150 angstroms. 22. The vertical nitride read only memory cell as claimed in claim 19, wherein the silicon nitride layer is formed by a low pressure chemical vapor deposition method. 23. The vertical nitride read only memory cell as claimed in claim 19, wherein the thickness of the silicon nitride layer is between 20 angstroms and 150 angstroms. 24. The vertical nitride read-only memory cell as claimed in claim 18, wherein the gate material comprises a doped polysilicon layer, and the doped polysilicon layer is simultaneously doped by an undoped polysilicon layer and get. 25. The vertical nitride read-only memory cell as claimed in claim 24, wherein the method of forming the doped polysilicon layer comprises a low pressure chemical vapor deposition method. 26. A semiconductor structure, one of the active regions of the semiconductor structure has a first conduction form, one of the first conduction forms is: the substrate at least includes a trench, embedded in the trench and has a horizontal portion and a vertical Part of a gate electrode, wherein the horizontal portion covers the substrate, the vertical portion is vertically embedded in the trench and one end is adjacent to the horizontal portion, and at least a capture layer is covered near the vertical portion, and the semiconductor structure is characterized in that it includes: : a first source/drain region located in the substrate at the other end of the vertical portion; A second source/drain region is located in the base at the edge of the trench and connected to the vertical portion and the horizontal portion.

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