CN1407626A - Vertical nitride read out-only memory unit - Google Patents
Vertical nitride read out-only memory unit Download PDFInfo
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- CN1407626A CN1407626A CN 01131319 CN01131319A CN1407626A CN 1407626 A CN1407626 A CN 1407626A CN 01131319 CN01131319 CN 01131319 CN 01131319 A CN01131319 A CN 01131319A CN 1407626 A CN1407626 A CN 1407626A
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Abstract
A vertical nitride ROM unit consists of a substrate with a canal, a grid with a horizontal portion covering the substrate and a vertical part inlaid in the canal, a catching layer between the grid and the substrate, the first source/drain region located on the surface of the canal bottom, and the second source/drain region on the top surface of the substrate.
Description
Technical field
The invention relates to a kind of structure of semiconductor device, particularly about a kind of nitride read-only memory unit with vertical stratification (Nitride Read-Only-Memory cell, NROMcell).
Background technology
Known nitride read only memory device, in having the metal oxide semiconductor transistor memory device, utilize for example is that silica-silicon-nitride and silicon oxide layer (ONO layer) is as the dielectric layer of catching or being absorbed in (Trap) electric charge, carry out the step of sequencing again, hot electron (HotElectrons) process is arranged in the silicon oxide layer tunnelling (Tunneling) of silicon nitride layer below to nitride layer, and the seizure by silicon nitride layer or be absorbed in the function of electric charge, and with Charge Storage in nitride layer, to finish the storage of data.In more detail, be when providing sequencing voltage to carry out sequencing to source electrode, drain electrode and grid, be positioned at channel region top silica-the silicon-nitride and silicon oxide layer is subjected to the influence of sequencing voltage, and the silicon oxide layer that makes hot electron pass bottom is collected in the nitride layer.
In addition, in technique known, the collected charge concentration of nitride layer is in the zone of contiguous source/drain, and the electric charge that is collected in nitride layer can increase the start voltage (Threshold Voltage) of channel region.When memory cell is having concentrated electric charge (for example memory cell after the sequencing), this memory cell can be subjected to the influence that start voltage raises, and make this memory cell carry out data when reading, be lower than start voltage and make channel region become non-conducting region because of reading voltage.Otherwise, when in memory cell, not concentrating electric charge, then can surpass start voltage, and make channel region become conducting region because of reading voltage.
Known nitride read only memory device is used in read-only memory (read onlymemory, ROM), programmable read only memory (programmable ROM, PROM), Erasable Programmable Read Only Memory EPROM (Erasable Programmable ROM, EPROM), the read-only flash memory of erasable programmable (Flash EPROM), can remove programmable read only memory (Electrically Erasable Programmable ROM by electricity, EEPROM), or can electricity remove read-only flash memory able to programme (Flash Electrically Erasable Programmable ROM, FlashEEPROM) in.Because nitride read only memory device injects hot electron via channel region and sinks into nitride layer to carry out the sequencing of memory cell, but therefore in traditional program read-only memory device, when using nitride read only memory device, eliminating the employed time of sequencing can be much larger than the employed time of sequencing, and then global proceduresization and the time of eliminating sequencing are increased.
In addition, in known nitride read only memory device, because channel region is positioned at the grid below, therefore under the integrated circuit (IC) design demand of quicker, more miniaturization, more intensive package, the length of channel region will have the trend that thereupon shortens gradually, so that the service speed of device is accelerated.Yet, when the contraction in length of channel region after to a certain degree, can produce short channel effect (Short Channel Effects) and thermoelectronic effect (Hot Electron Effects), and then cause the result of the electrical inefficacy of device.
Summary of the invention
The invention provides a kind of metal-oxide semiconductor transistor construction,, still can keep preferable device property with when reducing device size.
The invention provides a kind of nitride read only memory device structure, wherein this nitride ROM has vertical stratification, so that channel region distributes along vertical direction, to reduce device size effectively.
The invention provides a kind of nitride read only memory device structure, its neutrality line distributes along directions X, with reduction of device size further.
The invention provides a kind of nitride read only memory device structure, when the junction capacitance of device can be reduced effectively, can improve the performance of nitride read only memory device simultaneously and reduce device size with length by the increase channel region.
In order to reach above-mentioned purpose, the present invention proposes a kind of rectilinear nitride read-only memory unit, its structure comprises substrate with irrigation canals and ditches, have the horizontal component that covers substrate and be embedded in an end and the vertical component of horizontal component adjacency in the irrigation canals and ditches grid, the seizure layer between grid and substrate, be arranged in the grid vertical component the other end substrate first source/drain regions and be arranged in the substrate at irrigation canals and ditches edge and second source/drain regions that is connected with the vertical component and the horizontal component of grid.
From the above, therefore the required area of rectilinear read only memory device of the present invention, can obtain having the memory device of highly dense degree much smaller than traditional horizontal read only memory device.
From the above, channel region of the present invention is extended along vertical direction, so bit line extends along directions X, can further dwindle the size of nitride read-only memory unit.
From the above, channel region of the present invention is extended along vertical direction, so the length of channel region can adjust along with the adjustment of the irrigation canals and ditches degree of depth, and then reduces the demand of junction capacitance effectively.And can when reducing device size, avoid the generation of short channel effect, and then the stability of boost device effectively.
From the above, the present invention can reduce resistance-capacitance time of delay (RC delay time) effectively when reducing junction capacitance, therefore, can increase the service speed of device effectively, and then improve the performance of device.
Description of drawings
Fig. 1 is to the schematic diagram of the manufacture process of the rectilinear nitride read-only memory unit that Figure 6 shows that a preferred embodiment of the present invention.Description of reference numerals:
100: the semiconductor-based end
102: irrigation canals and ditches
103: ion is implanted
104: the first source/drain regions
106: the second source/drain regions
108: general source/drain regions
110,114: silicon dioxide layer
112: silicon nitride layer
116: gate conductor layer
Embodiment
The present invention narrates structure and its manufacture method of rectilinear nitride read-only memory unit.Please refer to shown in Figure 1ly, the semiconductor-based end 100 is provided, and in the semiconductor-based end 100, form irrigation canals and ditches 102.The method that forms irrigation canals and ditches 102 for example is to use traditional lithography manufacture method, and preferable etching manufacture method for example is to use suitable electricity slurry mist to carry out anisotropic etching.In addition, also can carry out extra processing, for example be to utilize thin H
2O
2Solution is with formed unnecessary oxide removal in etching manufacturing process such as substrate 100 surperficial Yu Fei.In addition, etching manufacture method also can use suitable wet etchant to carry out Wet-type etching.Then, carry out channel region ion implantation step (not shown), to adjust start voltage.For example be to use the method for the channel region ion implantation of oblique angle implanted prosthetics, utilize between 3 * 10
11Ion/square centimeter is to 5 * 10
13The dosage of ion/square centimeter centimetre and between the energy between the 5KeV to 50KeV will be implanted in the nmos device such as boron or boron fluoride ion, or will implant in the PMOS device such as arsenic or phosphonium ion.
Then, please refer to shown in Figure 2ly, carry out ion and implant 103, in the substrate at irrigation canals and ditches edge, forming first source/drain regions 104 and second source/drain regions 106, and in the bottom substrate of irrigation canals and ditches 102 the general source/drain regions 108 of formation.The method for implantation of source/drain regions 104,106,108 for example is to use between 5 * 10
12Ion/square centimeter is to 2 * 10
16Dosage between ion/square centimeter and between the energy between the 5KeV to 80KeV carries out the implantation of boron fluoride, arsenic or phosphonium ion.In addition, after forming source/drain regions 104,106,108, carry out a heat treatment, so that (Rapid Thermal was reacted (RTA) at 10 seconds, high temperature) between 60 minutes (low temperature), between device heats 800 degree extremely Celsius 1100 degree extremely Celsius, so that the admixture activate of being implanted.
Then, please refer to Fig. 3, on substrate and irrigation canals and ditches, form and catch layer to shown in Figure 5.As shown in Figure 5, for example be the seizure layer that is constituted by silicon dioxide layer 110-silicon nitride layer 112-silicon dioxide layer 114, be formed on substrate 100 and the irrigation canals and ditches 102 (as shown in Figure 1).Please refer to shown in Figure 3ly, under low-temperature oxidation operation, formation thickness is the end silicon dioxide layer 110 between 50 dust to 150 dusts on substrate 100 and irrigation canals and ditches 102 (as shown in Figure 1), and the preferred thickness of end silicon dioxide layer 110 is the 80 Izod right sides.Oxidizing temperature, is preferably about 800 degree Celsius between 1000 degree Celsius between 750 degree Celsius.
Then, please refer to shown in Figure 4ly, use chemical vapour deposition technique, covering the silicon nitride layer 112 of a layer thickness between 20 dust to 150 dusts on the end silicon dioxide layer 110, the preferred thickness of silicon nitride layer 112 is the 100 Izod right sides.Though form the method for silicon nitride layer 112 in addition is that example describes with the chemical vapour deposition technique, yet is not as limit, also can use other sedimentation instead.
Then, please refer to shown in Figure 5ly, utilize thermal oxidation method, on silicon nitride layer 112, form a top silicon dioxide layer 114.Form the method for top silicon dioxide layer 114, though be that example describes with the thermal oxidation method, be not as limit, also can use sedimentation or combined techniques instead.It should be noted that and utilize thermal oxidation method to form during the top silicon dioxide layer 114, can consume part silicon nitride layer 112, and the consumption thickness of silicon nitride layer 112 is half of formation thickness of top silicon dioxide layer 114.Therefore, if when the predetermined formation thickness of top silicon dioxide layer 114 is 100 dusts, then the thickness of silicon nitride layer 112 is Duoed 50 dusts than the thickness of last required silicon nitride layer 112 at least, to form top silicon dioxide layer 114 by consuming extra silicon nitride.In addition, the preferred thickness of top silicon dioxide layer 114 is 50 dust to 150 dusts.
Then, please refer to shown in Figure 6ly, on substrate 100, cover one deck gate conductor layer 116, and fill up irrigation canals and ditches 102 (shown in the 1st figure).Gate conductor layer 116 for example is a doped polysilicon layer.The formation method of gate conductor layer 116 for example is to utilize Low Pressure Chemical Vapor Deposition (low pressure chemical vapor deposition, LPCVD), in substrate, cover one deck undoped polycrystalline silicon layer, again active admixture is implanted in the undoped polycrystalline silicon layer, to form doped polysilicon layer.
Can learn that by above-mentioned rectilinear nitride ROM transistor the required area of rectilinear read only memory device is much smaller than traditional horizontal configuration transistor.Again as can be known, by existing Design Rule the device with less demand area further boost device closeness and obtain the circuit devcie of highly dense degree.Therefore, use rectilinear nitride ROM of the present invention, can obtain the memory device of highly dense degree.
Can learn that by above-mentioned rectilinear nitride ROM transistor because channel region extends along vertical direction, so bit line extends along directions X, so can further dwindle the size of nitride read-only memory unit.
Can learn that by above-mentioned rectilinear nitride ROM transistor because channel region extends along vertical direction, so the length of channel region can adjust along with the adjustment of the irrigation canals and ditches degree of depth, and then reduces the demand of junction capacitance effectively.And can when reducing device size, avoid the generation of short channel effect, and then the stability of boost device effectively.
From the above, when the present invention reduces junction capacitance, can reduce resistance-capacitance time of delay effectively.Therefore can increase the service speed of device effectively, and then improve the performance of device.
Though be to describe in this preferred embodiment with the nitride ROM transistor, the present invention be not limited thereto, without departing from the spirit and scope of the present invention, also go for the manufacturing of other metal oxide semiconductor transistor.
Though the present invention openly as above, so be not with a preferred embodiment with since limit the present invention, without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.Also can be used for a variety of modifications and variations according to the spirit and scope that claim of the present invention defined.All employed in the present invention embodiment and accompanying drawing only are used for that the present invention will be described, not as limit.
Claims (26)
1. rectilinear nitride read-only memory unit is characterized in that: comprising:
One substrate has irrigation canals and ditches in this substrate;
One grid, this grid comprise a horizontal component and a vertical component, and this horizontal component covers in the substrate, and this vertical component embeds in the irrigation canals and ditches and an end and this horizontal component adjacency;
One catches layer, between grid and substrate;
One first source/drain regions is arranged in the substrate of this vertical component other end;
One second source/drain regions is arranged in the substrate at this irrigation canals and ditches edge, and is connected with this vertical component and this horizontal component.
2. rectilinear nitride read-only memory unit as claimed in claim 1 is characterized in that: this seizure layer comprises that one mixes dielectric layer, and this mixing dielectric layer comprises silicon oxide layer-silicon nitride-silicon oxide layer.
3. rectilinear nitride read-only memory unit as claimed in claim 2 is characterized in that: the formation method of silicon oxide layer comprises the low thermal oxidation method.
4. rectilinear nitride read-only memory unit as claimed in claim 2 is characterized in that: the thickness of silicon oxide layer is between 50 dust to 150 dusts.
5. rectilinear nitride read-only memory unit as claimed in claim 2 is characterized in that: the formation method of silicon nitride layer comprises Low Pressure Chemical Vapor Deposition.
6. rectilinear nitride read-only memory unit as claimed in claim 2 is characterized in that: the thickness of silicon nitride layer is between 20 dust to 150 dusts.
7. rectilinear nitride read-only memory unit as claimed in claim 1 is characterized in that: the material of this grid comprises a doped polysilicon layer, and this doped polysilicon layer is to be mixed simultaneously and got by a undoped polycrystalline silicon layer.
8. rectilinear nitride read-only memory unit as claimed in claim 7 is characterized in that: the formation method of this doped polysilicon layer comprises Low Pressure Chemical Vapor Deposition.
9. metal oxide semiconductor transistor is characterized in that: comprising:
One substrate has irrigation canals and ditches in this substrate;
One grid, this grid comprise a horizontal component and a vertical component, and wherein horizontal component covers in the substrate, and vertical component embeds in the irrigation canals and ditches and an end and this horizontal component adjacency;
One dielectric layer is between grid and substrate;
One first source/drain regions is arranged in the substrate of the vertical component other end;
One second source/drain regions is arranged in the substrate at irrigation canals and ditches edge, and is connected with this vertical component and this horizontal component.
10. metal oxide semiconductor transistor as claimed in claim 9 is characterized in that: this dielectric layer comprises that one mixes dielectric layer, and this mixing dielectric layer comprises silicon oxide layer-silicon nitride-silicon oxide layer.
11. metal oxide semiconductor transistor as claimed in claim 10 is characterized in that: the formation method of silicon oxide layer comprises the low thermal oxidation method.
12. metal oxide semiconductor transistor as claimed in claim 10 is characterized in that: the thickness of silicon oxide layer is between 50 dust to 150 dusts.
13. metal oxide semiconductor transistor as claimed in claim 10 is characterized in that: the formation method of silicon nitride layer comprises Low Pressure Chemical Vapor Deposition.
14. metal oxide semiconductor transistor as claimed in claim 10 is characterized in that: the thickness of silicon nitride layer is between 20 dust to 150 dusts.
15. metal oxide semiconductor transistor as claimed in claim 9 is characterized in that: this dielectric layer comprises silicon oxide layer.
16. metal oxide semiconductor transistor as claimed in claim 9 is characterized in that: the material of this grid comprises a doped polysilicon layer, and this doped polysilicon layer is mixed simultaneously by a undoped polycrystalline silicon layer and gets.
17. metal oxide semiconductor transistor as claimed in claim 16 is characterized in that: the formation method of this doped polysilicon layer comprises Low Pressure Chemical Vapor Deposition.
18. a rectilinear nitride read-only memory unit is characterized in that: comprising:
One substrate has irrigation canals and ditches in this substrate;
One grid, this grid comprise a horizontal component and a vertical component, and wherein this horizontal component covers in the substrate, and this vertical component embeds in the irrigation canals and ditches and an end and this horizontal component adjacency;
One catches layer, between grid and substrate;
One general source/drain regions is arranged in the substrate of this vertical component other end;
One first source/drain regions is arranged in the substrate of irrigation canals and ditches one end margin, and is connected with this vertical component and this horizontal component;
One second source/drain regions is arranged in the substrate at irrigation canals and ditches other end edge, and is connected with this vertical component and this horizontal component.
19. rectilinear nitride read-only memory unit as claimed in claim 18 is characterized in that: this seizure layer comprises that one mixes dielectric layer, and this mixing dielectric layer comprises silicon oxide layer-silicon nitride-silicon oxide layer.
20. rectilinear nitride read-only memory unit as claimed in claim 19 is characterized in that: the formation method of silicon oxide layer comprises the low thermal oxidation method.
21. rectilinear nitride read-only memory unit as claimed in claim 19 is characterized in that: the thickness of silicon oxide layer is between 50 dust to 150 dusts.
22. rectilinear nitride read-only memory unit as claimed in claim 19 is characterized in that: the formation method of silicon nitride layer comprises Low Pressure Chemical Vapor Deposition.
23. rectilinear nitride read-only memory unit as claimed in claim 19 is characterized in that: the thickness of silicon nitride layer is between 20 dust to 150 dusts.
24. rectilinear nitride read-only memory unit as claimed in claim 18 is characterized in that: the material of this grid comprises a doped polysilicon layer, this doped polysilicon layer is mixed simultaneously by a undoped polycrystalline silicon layer and gets.
25. rectilinear nitride read-only memory unit as claimed in claim 24 is characterized in that: the formation method of this doped polysilicon layer comprises Low Pressure Chemical Vapor Deposition.
26. semiconductor structure, has one first conductive form in one of this semiconductor structure active region, the a kind of of this first conductive form is: substrate comprises irrigation canals and ditches at least, is embedded in the irrigation canals and ditches and has a horizontal component and a gate electrode of a vertical component, wherein this horizontal component covers in the substrate, this vertical component vertically embeds in the irrigation canals and ditches and an end and this horizontal component adjacency, at least cover one and catch layer near this vertical component, this semiconductor structure is characterised in that: comprising:
One first source/drain regions is arranged in the substrate of this vertical component other end;
One second source/drain regions is arranged in the substrate at irrigation canals and ditches edge, and is connected with this vertical component and this horizontal component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01131319 CN1407626A (en) | 2001-09-06 | 2001-09-06 | Vertical nitride read out-only memory unit |
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| CN 01131319 CN1407626A (en) | 2001-09-06 | 2001-09-06 | Vertical nitride read out-only memory unit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1326233C (en) * | 2003-08-22 | 2007-07-11 | 南亚科技股份有限公司 | Multi-element vertical memory and its manufacture |
| CN100343980C (en) * | 2004-03-29 | 2007-10-17 | 力晶半导体股份有限公司 | Non-volatile memory element and its making method |
| CN100362664C (en) * | 2004-03-26 | 2008-01-16 | 力晶半导体股份有限公司 | Non-volatile memory location and producing method thereof |
| CN101385087B (en) * | 2005-12-22 | 2012-01-11 | Nxp股份有限公司 | SONOS memory device with reduced short-channel effects |
-
2001
- 2001-09-06 CN CN 01131319 patent/CN1407626A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1326233C (en) * | 2003-08-22 | 2007-07-11 | 南亚科技股份有限公司 | Multi-element vertical memory and its manufacture |
| CN100362664C (en) * | 2004-03-26 | 2008-01-16 | 力晶半导体股份有限公司 | Non-volatile memory location and producing method thereof |
| CN100343980C (en) * | 2004-03-29 | 2007-10-17 | 力晶半导体股份有限公司 | Non-volatile memory element and its making method |
| CN101385087B (en) * | 2005-12-22 | 2012-01-11 | Nxp股份有限公司 | SONOS memory device with reduced short-channel effects |
| US8525250B2 (en) | 2005-12-22 | 2013-09-03 | Nxp B.V. | SONOS memory device with reduced short-channel effects |
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