CN1405676A - Method for turning-on computer capable of using debugging system, computer system and its bridge connector - Google Patents
Method for turning-on computer capable of using debugging system, computer system and its bridge connector Download PDFInfo
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- CN1405676A CN1405676A CN 02151356 CN02151356A CN1405676A CN 1405676 A CN1405676 A CN 1405676A CN 02151356 CN02151356 CN 02151356 CN 02151356 A CN02151356 A CN 02151356A CN 1405676 A CN1405676 A CN 1405676A
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Abstract
The invention includes following steps. The CPU sends the data request from the system bus to the ROM. The north bridge transfers the data request on the systems bus to the peripheral bus. The south bridge is switched to the normal mode. Under the normal mode, the south bridge responds to the data request located on the peripheal bus by the program code of the BIOS stored in the ROM. The program code of the BIOS is loaded into the CPU. The south bridge is switched to the debug mode. Under the debug mode, the south bridge can not respond to the data request located on the peripheral bus. The debug system replacing the south bridge responds to the data request by the program code of another BIOS, and the program code of the BIOS is loaded to the CPU.
Description
Technical field
The present invention relates to a kind of method of computer system start, be particularly related to a kind of computer system and method for using the debuggers start, can when Basic Input or Output System (BIOS) (BIOS) program code or its ROM (read-only memory) (ROM) fault, still can carry out boot program and carry out misarrangement.
Background technology
In general, the framework of computer system is made up of a plurality of different levels.Lowermost layer is actual hardware layer, and top be application software with user's interaction.Between hardware and application software then is system software.System software itself also can be divided into a plurality of parts, has comprised operating system kernel and skin, device driver or multitask executive routine.
Usually between hardware and system software, also can comprise the software layer of a low order, be referred to as Basic Input or Output System (BIOS) (BIOS).BIOS provides basic output to go into service function between system or application software and hardware, and handles the interruptive command (interrupt) that is sent by system.Use via interruptive command can be carried out necessary control to computer system.These interruptive commands can be sent by microprocessor, system hardware or software.BIOS then handles these interruptive commands in the mode of Digital Logic.When an interruptive command produced, the control of computer system just can be handed on the interrupt vector (interrupt vector), and interrupt vector has defined in BIOS, joined section displacement (segment:offset) address of the route of giving certain interruption code.
BIOS Interrupt Service Routine (ISRs, Interrupt Service Routines) is handled the interruptive command that is sent by hardware unit.Interrupt Service Routine has used the temporal data (register) in central processing unit and the BIOS data area.And BIOS device service routine (DSRs, Device Service Routines) is then handled the software interruption order by using the INT instruction to be sent.
BIOS is except the above-mentioned service that provides during computer system operation, and when the unified start of department of computer science, the essential bios program code of carrying out earlier is to carry out the work of initialization and configuration and setting for whole computer system.BIOS can carry out one at this moment and open the beginning program, is referred to as power initiation selftest (POST) program.This program can be carried out the work of many necessity, has comprised that the test of random access memory, examination are installed on devices all in the computer system, floppy disk, hard disk, keyboard, parallel port, serial port and other device (as CD-ROM or sound card or the like) that is installed in the computer system are carried out configuration and setting, will provide the computer hardware of necessary specific function (as plug and play, power management etc.) to carry out initialization.If these work can both successfully be finished, then BIOS will begin the load operation system, as disc operating system (DOS) (DOS), LINUX, WINDOW95, WINDOW98 or the like, finishes whole in-cycle work at last.
Because the in-cycle work of computer system is very complicated, no matter be that BIOS or operating system all may make a mistake when starting and causes boot failure, make whole computer system can't operate at all, especially control the BIOS of groundwork in the in-cycle work.Therefore, for responsible BIOS designed system chipset fabricator, it is crucial work that bios program code is carried out misarrangement (debug).
Yet when system bios was carried out misarrangement, the situation of making us perplexing most was when system bios makes a mistake, computer system or the running of chipset can't start at all, and have no idea to learn the wrong reason that takes place.Must use this moment the most basic analytics just might locate errors reason, very labor intensive and time in the mode of direct measurement pin signal.
Summary of the invention
In order to address the above problem, the object of the present invention is to provide a kind of method and computer system of using the debuggers start, respond central processing unit to bios program code access requirement by making debuggers replace periphery/expansion bus bridge (south bridge), and can ignore the BIOS of fault, and, by debuggers BISO is carried out the work that error reason is analyzed again afterwards by debuggers catcher boot program.
The invention provides a kind of method of using the debuggers start, be applicable to a computer system, this computer system has the ROM (read-only memory) that a central processing unit, a system bus, a peripheral bus, an expansion bus, first and second bridge and are connected to this expansion bus and store the first Basic Input or Output System (BIOS) program code, this debuggers system is connected to this peripheral bus, and this method may further comprise the steps: the data demand that is sent this ROM (read-only memory) of sensing by this central processing unit on this system bus; The data demand that will be positioned on this system bus by this first bridge transfers on this peripheral bus; This second bridge is switched to a normal mode, under this normal mode, make this second bridge respond the data demand that is positioned on this peripheral bus, and this first Basic Input or Output System (BIOS) program code is loaded this central processing unit with the first Basic Input or Output System (BIOS) program code that is stored in this ROM (read-only memory); And this second bridge switched to a misarrangement pattern, under this misarrangement pattern, make this second bridge can't respond the data demand that is positioned on this peripheral bus, respond this data demand and this debuggers replaces this second bridge with one second Basic Input or Output System (BIOS) program code, and this second Basic Input or Output System (BIOS) program code is loaded this central processing unit.
The present invention also provides a kind of computer system of using the debuggers start, comprising: a central processing unit; One system, periphery and expansion bus, wherein this central processing unit sends a data demand to this system bus, and this debuggers system is connected to this peripheral bus; One ROM (read-only memory) is connected to this expansion bus and stores one first basic output and goes into program code, and this data demand points to this ROM (read-only memory); One first bridge, this data demand that will be positioned on this system bus is transferred to this peripheral bus; And one second bridge, switch under a normal mode and the misarrangement pattern, wherein under this normal mode, this second bridge responds the data demand that is positioned on this peripheral bus with the first Basic Input or Output System (BIOS) program code that is stored in this ROM (read-only memory), and this first Basic Input or Output System (BIOS) program code is loaded this central processing unit, and under this misarrangement pattern, this second bridge can't respond the data demand that is positioned on this peripheral bus, respond this data demand and this debuggers replaces this second bridge with one second Basic Input or Output System (BIOS) program code, and this second Basic Input or Output System (BIOS) program code is loaded this central processing unit.
The present invention also provides a kind of periphery/expansion bus bridge, be used for the computer system that to use debuggers to start shooting, wherein this computer system has a central processing unit, one system bus, one peripheral bus, one expansion bus, one system/peripheral bus bridge joint device and is connected to this expansion bus and stores the ROM (read-only memory) of the first Basic Input or Output System (BIOS) program code, this debuggers system is connected to this peripheral bus, this periphery/expansion bus bridge comprises: a switching device shifter should switch between a normal mode and the misarrangement pattern by periphery/expansion bus bridge; An and address decoder, when this periphery/when the expansion bus bridge is switched to this normal mode, this address decoder is deciphered the address in the data demand that this central processing unit sent and point to this ROM (read-only memory), and make this periphery/expansion bus bridge select signal to this peripheral bus and according to this address, to read this relative first Basic Input or Output System (BIOS) program code to respond this data demand from this ROM (read-only memory) by sending a device, so that this first Basic Input or Output System (BIOS) program code is loaded this central processing unit, and when this periphery/expansion bus bridge was switched to this misarrangement pattern, this address decoder was failure to actuate.Wherein, when this periphery/expansion bus bridge is switched to this misarrangement pattern, this debuggers replaces this periphery/expansion bus bridge and responds this data demand with the second Basic Input or Output System (BIOS) program code, so that this second Basic Input or Output System (BIOS) program code is loaded this central processing unit.
Thereby, in the present invention, utilize the constraint pin (strappingpin) of periphery/expansion bus (south bridge) to decide its address decoder whether to act on, when this address code translator is not done the time spent, south bridge just can't require to do response to the access of bios program code, and can ignore the bios program code or the ROM (read-only memory) of fault, again by the misarrangement clamping hand boot program on the peripheral bus.
Description of drawings
Below, with regard to the description of drawings computer system of debuggers start and the embodiment of method of using of the present invention.
Fig. 1 has shown the computer system block scheme that can use the debuggers start in one embodiment of the invention.
Fig. 2 has shown the employed signal sequence of the computer system of Fig. 1.
[symbol description]
The 10-central processing unit;
The 12-system bus;
The 13-high-speed cache;
The 16-ROM (read-only memory);
The 18-peripheral bus;
The 20-north bridge chips;
The 22-display card;
24-misarrangement adapter;
The 28-South Bridge chip;
281-retrains pin;
The 282-change-over switch;
The 283-address decoder;
The 30-expansion bus;
32a, 32b, 32c-expansion bus slot;
The 34-slot; And
4-misarrangement computer system.
Embodiment
Fig. 1 has shown the computer system block scheme that can use the debuggers start in one embodiment of the invention.In computer system, all assemblies and bus be arranged on one can provide necessary coiling, slot, and the motherboard (figure shows) of other coupling arrangement of all kinds on.Computer system has a central processing unit 10, mainly is made of microprocessor, as intel pentium the 4th generation (Intel Pentium4).Central processing unit 10 is connected to a system bus 12, also has a high-speed cache 13 and is connected with it.
There is multiple different device can be connected to peripheral bus 18, as image processor (display card) 22.In addition, a misarrangement adapter 24 also is connected to peripheral bus 18.Connecting interface between the computer system that the function of misarrangement adapter 24 is to use as computer system and another misarrangement.
There is multiple different device to be connected to expansion bus 30 via slot 32a, 32b and 32c.ROM (read-only memory) 16 is connected to expansion bus 30 via slot 34.ROM (read-only memory) 16 has stored the employed program code of BIOS.
Fig. 2 has shown the signal sequence of computer system when using the start of ROM (read-only memory) 16 or debuggers.In fact, in the communications protocol of pci bus, used very many signals, only shown the signal relevant herein with the present invention.
As shown in Figure 2, signal CLK is the clock pulse signal that comes from system, and signal RESET resets signal, and when reseting, signal RESET can produce a logic high earlier, returns default low level afterwards.
At first, north bridge chips 20 will be sent the ROM (read-only memory) access signal on pci bus 18 according to the communications protocol of bus after being reset.The data demand that sends an indication ROM (read-only memory) read cycle at central processing unit 10 is during to system bus 12, and north bridge chips 20 will trigger pip ROMSEL$.As use habit, adding behind the signal name that " $ " symbol is to represent this signal to have low logic level (active low) when being triggered.The ROM (read-only memory) address that is required access will be sent along with data demand, and will be transferred on the pci bus 18 by north bridge chips 20.Simultaneously, also being loaded with relevant control signal in the data demand is required to represent a read cycle.According to the communications protocol of pci bus, the device that is pointed to by data demand should be in this read cycle after the phase place of address three clock cycles select signal DEVSEL$ with interior response one device, with presentation address effectively and can decipher.Therefore, when South Bridge chip 28 operates in normal mode, South Bridge chip 28 just can use the signal ROMSEL$ from north bridge chips 20 to touch that its address decoder 283 is deciphered and at response DEVSEL$ signal within three clock cycles on pci bus 18, after finishing, decoding can read simultaneously in the ROM (read-only memory) 16 and the relative bios program code data of institute's decoding address, so that it is loaded in central processing unit 10.On the other hand, when South Bridge chip 28 operates in the misarrangement pattern, because its address decoder 283 is failure to actuate, therefore can't do response to the ROMSEL$ signal that north bridge chips 20 is sent, the substitute is, misarrangement adapter 24 can produce the DEVSEL$ signal and respond on pci bus 18, and the address in the data requirement is deciphered, according to the address after the decoding, the bios program code data that itself store are sent and loaded in the central processing unit 10.
By above-mentioned operation as can be known, because when South Bridge chip 28 is switched to the misarrangement pattern, its address decoder 283 is failure to actuate, therefore debuggers just can replace South Bridge chip 28 and comes the ROMSEL$ signal that north bridge chips 20 is sent is responded, and with in the bios program code data load central processing unit 10 that itself stores.So, no matter ROM (read-only memory) 16, be stored in bios program code in the ROM (read-only memory) 16 or even South Bridge chip 28 when problems take place, can after using change-over switch 282 that South Bridge chip 28 is switched to the misarrangement pattern, ignore these problems, and directly start shooting by debuggers.In addition, because misarrangement adapter 24 is connected with the computer system 4 that another misarrangement is used, its stored bios program code also can be programmed via computer system 4.
When using debuggers to start shooting, can also carry out following program:
1. the computer system of using owing to misarrangement 4 is connected with pci bus, can in computer system 4, use the mode of software, when directly reading in in-cycle work and begin via misarrangement adapter 24 and north bridge chips 20, the stored data content of register in the central processing unit 10 (register).Traditionally, this step can only or be used oscillograph directly read the pin signal and finish with logic analysis.
2. do not have under the situation of damage at South Bridge chip 28 and ROM (read-only memory) 16, utilize computer system 4 to read and be stored in the bios program code data that may make a mistake in the ROM (read-only memory) 16, to analyse and compare via misarrangement adapter 24, South Bridge chip 28.
3. under the situation that South Bridge chip 28 and ROM (read-only memory) 16 do not have to damage, utilize computer system 4 via misarrangement adapter 24, South Bridge chip 28 with in the burned ROM (read-only memory) 16 of correct bios program code.
Comprehensively above-mentioned, the invention provides a kind of method and computer system of using the debuggers start, utilize the constraint pin (strapping pin) of periphery/expansion bus (south bridge) to decide its address decoder whether to act on, when this address code translator is not done the time spent, south bridge just can't require to do response to the access of bios program code, and can ignore the bios program code or the ROM (read-only memory) of fault, again by the misarrangement clamping hand boot program on the peripheral bus, carry out necessary misarrangement action.
Though the present invention discloses as above with a preferred embodiment; yet it is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; can do some and change and retouching, so protection scope of the present invention should be looked being as the criterion that accompanying Claim defines.
Claims (11)
1. the method that can use debuggers start, be applicable to a computer system, this computer system has the ROM (read-only memory) that a central processing unit, a system bus, a peripheral bus, an expansion bus, first and second bridge and are connected to this expansion bus and store the first Basic Input or Output System (BIOS) program code, this debuggers system is connected to this peripheral bus, and this method may further comprise the steps:
On this system bus, send the data demand of this ROM (read-only memory) of sensing by this central processing unit;
The data demand that will be positioned on this system bus by this first bridge is transferred on this peripheral bus;
This second bridge is switched to a normal mode, under this normal mode, make this second bridge respond the data demand that is positioned on this peripheral bus, and this first Basic Input or Output System (BIOS) program code is loaded this central processing unit with the first Basic Input or Output System (BIOS) program code that is stored in this ROM (read-only memory); And
This second bridge is switched to a misarrangement pattern, under this misarrangement pattern, make this second bridge can't respond the data demand that is positioned on this peripheral bus, respond this data demand and this debuggers replaces this second bridge with one second Basic Input or Output System (BIOS) program code, and this second Basic Input or Output System (BIOS) program code is loaded this central processing unit.
2. the method for using the debuggers start as claimed in claim 1, wherein further comprising the steps of:
When this second bridge is switched to this misarrangement pattern, read and show the stored contents of a plurality of registers in this central processing unit by this debuggers.
3. the method for using the debuggers start as claimed in claim 1, wherein further comprising the steps of:
When this second bridge is switched to this misarrangement pattern, from this ROM (read-only memory), read this first Basic Input or Output System (BIOS) program code via this second bridge by this debuggers.
4. the method for using the debuggers start as claimed in claim 1, wherein further comprising the steps of:
When this second bridge is switched to this misarrangement pattern, by this debuggers via this second bridge with in burned this ROM (read-only memory) of this second Basic Input or Output System (BIOS) program code.
5. the computer system that can use debuggers start comprises:
One central processing unit;
One system, periphery and expansion bus, wherein this central processing unit sends a data demand to this system bus, and this debuggers system is connected to this peripheral bus;
One ROM (read-only memory) is connected to this expansion bus and stores one first basic output and goes into program code, and this data demand points to this ROM (read-only memory);
One first bridge, this data demand that will be positioned on this system bus is transferred to this peripheral bus; And
One second bridge, switch under a normal mode and the misarrangement pattern, wherein under this normal mode, this second bridge responds the data demand that is positioned on this peripheral bus with the first Basic Input or Output System (BIOS) program code that is stored in this ROM (read-only memory), and this first Basic Input or Output System (BIOS) program code is loaded this central processing unit, and under this misarrangement pattern, this second bridge can't respond the data demand that is positioned on this peripheral bus, respond this data demand and this debuggers replaces this second bridge with one second Basic Input or Output System (BIOS) program code, and this second Basic Input or Output System (BIOS) program code is loaded this central processing unit.
6. the computer system of using the debuggers start as claimed in claim 5, wherein this second Basic Input or Output System (BIOS) program code is programmed by this debuggers, and this debuggers comprises:
One adapter is connected to this peripheral bus; And
One second computer system is connected to this adapter.
7. the computer system of using the debuggers start as claimed in claim 5, wherein when this second bridge was switched to this misarrangement pattern, this debuggers read and shows the stored contents of a plurality of registers in this central processing unit.
8. the computer system of using the debuggers start as claimed in claim 5, wherein when this second bridge was switched to this misarrangement pattern, this debuggers read this first Basic Input or Output System (BIOS) program code via this second bridge from this ROM (read-only memory).
9. the computer system of using the debuggers start as claimed in claim 5, wherein when this second bridge is switched to this misarrangement pattern, this debuggers via this second bridge with in burned this ROM (read-only memory) of this second Basic Input or Output System (BIOS) program code.
10. the computer system of using the debuggers start as claimed in claim 5, wherein this second bridge has a constraint pin (strapping pin), in order to carry out the switching between normal mode and misarrangement pattern.
11. periphery/expansion bus bridge, be used for the computer system that to use debuggers to start shooting, wherein this computer system has the ROM (read-only memory) that a central processing unit, a system bus, a peripheral bus, an expansion bus, one system/peripheral bus bridge joint device and are connected to this expansion bus and store the first Basic Input or Output System (BIOS) program code, this debuggers is connected to this peripheral bus, and this periphery/expansion bus bridge comprises:
One switching device shifter should switch between a normal mode and the misarrangement pattern by periphery/expansion bus bridge; And
One address decoder, when this periphery/when the expansion bus bridge is switched to this normal mode, this address decoder is deciphered the address in the data demand that this central processing unit sent and point to this ROM (read-only memory), and make this periphery/expansion bus bridge select signal to this peripheral bus and according to this address, to read this relative first Basic Input or Output System (BIOS) program code to respond this data demand from this ROM (read-only memory) by sending a device, so that this first Basic Input or Output System (BIOS) program code is loaded this central processing unit, and when this periphery/expansion bus bridge was switched to this misarrangement pattern, this address decoder was failure to actuate;
Wherein, when this periphery/expansion bus bridge is switched to this misarrangement pattern, this debuggers replaces this periphery/expansion bus bridge and responds this data demand with the second Basic Input or Output System (BIOS) program code, so that this second Basic Input or Output System (BIOS) program code is loaded this central processing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021513562A CN1194294C (en) | 2002-11-18 | 2002-11-18 | Method for turning-on computer capable of using debugging system, computer system and its bridge connector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021513562A CN1194294C (en) | 2002-11-18 | 2002-11-18 | Method for turning-on computer capable of using debugging system, computer system and its bridge connector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1405676A true CN1405676A (en) | 2003-03-26 |
| CN1194294C CN1194294C (en) | 2005-03-23 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021513562A Expired - Lifetime CN1194294C (en) | 2002-11-18 | 2002-11-18 | Method for turning-on computer capable of using debugging system, computer system and its bridge connector |
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| CN (1) | CN1194294C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100334556C (en) * | 2003-09-30 | 2007-08-29 | 宏达国际电子股份有限公司 | Method of starting operated during CPU shutdown and computer system thereof |
| CN100375941C (en) * | 2004-12-10 | 2008-03-19 | 威盛电子股份有限公司 | Computer system, basic input output system and system reset method |
| CN100432952C (en) * | 2006-06-20 | 2008-11-12 | 威盛电子股份有限公司 | System for pick-up bus transmission and its method |
-
2002
- 2002-11-18 CN CNB021513562A patent/CN1194294C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100334556C (en) * | 2003-09-30 | 2007-08-29 | 宏达国际电子股份有限公司 | Method of starting operated during CPU shutdown and computer system thereof |
| CN100375941C (en) * | 2004-12-10 | 2008-03-19 | 威盛电子股份有限公司 | Computer system, basic input output system and system reset method |
| CN100432952C (en) * | 2006-06-20 | 2008-11-12 | 威盛电子股份有限公司 | System for pick-up bus transmission and its method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1194294C (en) | 2005-03-23 |
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