CN1384366A - Flexible modular semiconductor test system - Google Patents
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- CN1384366A CN1384366A CN 01115701 CN01115701A CN1384366A CN 1384366 A CN1384366 A CN 1384366A CN 01115701 CN01115701 CN 01115701 CN 01115701 A CN01115701 A CN 01115701A CN 1384366 A CN1384366 A CN 1384366A
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Abstract
The present invention is one semiconductor test system of several tester modules, by means of which different semiconductor test system may be constituted easily. The semiconductor test system includes two or more different tester modules; one test head for holding the said tester modules; one connector for connecting electrically the tester modules and the tested device; and one computer connected via tester bus to tester modules to control the operation of the test system. The tester modules have one performance type of high speed and high time sequence precision and one other performance type of low speed and low time sequence precision. Each event tester module includes one tester board configurated as one event-based tester.
Description
The present invention relates to a kind of semiconductor test system, be used for the measuring semiconductor integrated circuit, large scale integrated circuit (LSI) for example, more particularly, relate to a kind of semiconductor test system based on module, this system can hold the combination of the proving installation of dissimilar modular constructions, so that easily constitute the semiconductor test system of required type.In addition, in semiconductor test system of the present invention, a small amount of high-speed high-performance proving installation (tester module) and a large amount of low speed low performance proving installation (tester module) are freely made up, thereby set up a low cost test system.In semiconductor test system of the present invention, the tester module disposes as the tester based on incident with the board testei that is used for the tester module, to produce the test pattern based on incident, is used for the measuring semiconductor integrated circuit.
Shown in Figure 1 is the block diagram of the semiconductor test system example in the routine techniques, is used for measuring semiconductor integrated circuit (following " IC device ", " the tested LSI " or " measured device " of also being referred to as).
In the example of Fig. 1, test processor 11 is application specific processors, and it is arranged in this semiconductor test system, by tester bus TB, to control the operation of this test macro.According to the mode data that this test processor 11 provides, mode generator 12 provides time series data and Wave data to timing sequencer 13 and waveform format device 14 respectively.The time series data that Wave data that waveform format device 14 employing mode generators 12 provide and timing sequencer 13 provide, to produce test pattern, this test pattern is applied in measured device (DUT) 19 by driver 15.
Cause that by this test pattern this DUT 19 produces a response signal, this signal is logical signal by an analog comparator 16 according to the predetermined threshold value voltage level conversion.By logic comparator 17 the expectation value data that this logical signal and mode generator provide are compared, the result of this logic comparison is stored in the fault memorizer 18 to address that should DUT 19.The switch (not shown) that driver 15, analog comparator 16 and being used for changes the pin of measured device is set at pin electronic circuit 20.
Above-mentioned circuit structure is set to each test pin of this semiconductor test system, therefore, because the large-scale semiconductive test macro is provided with a large amount of test pin, from 256 to 1048 test pin for example, then need make up the circuit structure of equal number, and each circuit structure as shown in Figure 1, and actual semiconductor test system becomes a very big system.Shown in Figure 2 is the example of the profile of this semiconductor test system, and this semiconductor test system mainly is made of main frame 22, measuring head 24 and workstation 26.
This workstation 26 is computing machines, for example disposes graphical user interface (GUI), and its function is as the interface between this test macro and the user.The execution of the operation of this test macro, the generation of test procedure and this test procedure is all implemented by this workstation.Main frame 22 comprises a large amount of test channel, and as shown in Figure 1, each passage is provided with test processor 11, mode generator 12, timing sequencer 13, waveform format device 14 and comparer 17, and corresponding with test pin.
Measuring head 24 comprises a large amount of printed circuit board (PCB)s, and each circuit board is provided with pin electronic circuit 20 shown in Figure 1.For example, this measuring head 24 is provided with a right cylinder, and wherein, the printed circuit board (PCB) that constitutes this pin electronic circuit is arranged along radial direction.At the upper surface of this measuring head 24, measured device 19 is inserted among the operation panel 28 near the test trough the heart.
Be provided with a pin (test) stationary installation 27 between pin electronic circuit and operation panel 28, this device is a kind of contact physical construction, is used for the transmission of electric signal.This pin stationary installation 27 comprises a large amount of contactors, and for example pogo pin (pogo-pins) is used to be electrically connected pin electronic circuit and operation panel.Measured device 19 is from pin electronic circuit acceptance test mode signal, and generation response output signal.
In the semiconductor test system of routine, in order to produce the test pattern that puts on measured device, employed test data is to adopt to be referred to as based on the form in cycle to describe.In the form based on the cycle, determining of each parameter in the test pattern is that each test period (tester frequency) with this semiconductor test system is a benchmark.More precisely, the test period in this test data (tester frequency) description, waveform (type of waveform and edge sequential) description and vector description have been stipulated the test pattern in the fc-specific test FC cycle.
In the design phase of measured device, under the workbench of computer-aided design (CAD) (CAD), handle to finish a logical simulation by a test board, thereby identify the design data that is drawn.Yet, describe based on the form of incident by this design appraising datum employing that test board obtains.In form based on incident, each change point (incident) in the certain test modes, for example from " 0 " to " 1 " or from " 1 " to " 0 ", describe according to the time period.For example, this time period is represented as since the absolute time section of a predetermined reference point or the relative time section between two proximal events.
In Application No. is 09/340, in 371 the file, the present inventor discloses the comparison of two kinds of test patterns between constituting, and a kind of test pattern constitutes and adopts this test data based on the form in cycle, and another kind of test pattern constitutes the test data that adopts based on the form of incident.The inventor of this invention has also proposed a kind of test macro based on incident as semiconductor test system, also as a kind of new ideas test macro.Be in 09/406,300 the application in the Application No. of the common assignee that belongs to this invention, provided detailed description for the structure and the operation of this test macro based on incident.
As mentioned above, in semiconductor test system, be provided with a large amount of printed circuit board (PCB)s and the like thing etc., its quantity is equal to or greater than the quantity of test pin, causes a very large on the whole system.In the semiconductor test system of routine, printed circuit board (PCB) etc. are identical mutually.
For example, in a high speed and high-resolution semiconductor test system, for example test frequency is 500MHz, and time sequence precision is 80 psecs, printed circuit board (PCB) all has same performance for all test pin, and each pin can both satisfy this test frequency and time sequence precision.Therefore, the semiconductor test system of this routine becomes the system of a cost costliness inevitably.And owing to adopt identical circuit structure in each test pin, this test macro can only be implemented limited test-types.
Yet, in the measured device of reality,, be not all pins of this measured device almost always at the pin of the peak performance that requires this semiconductor test system.For example, in tested typical logic large scale integrated circuit (LSI) device, be provided with a hundreds of pin, in fact have only several pins to be operated in top speed, therefore and require the top speed test signal, and other hundreds of pin is operated in quite low speed, and the test signal of low speed is enough for these pins like this.For system-on-a-chip (system-on-chip is abbreviated as SOC) also is that so this chip is a kind of up-to-date semiconductor devices of showing great attention to that causes in the industry.Therefore, the high speed test signal only is that the pin of a spot of SOC is required, and to other pin, low-speed test signal is just enough.
In the semiconductor test system of routine, just the needed high test performance of a small amount of pin of measured device but is equipped with to all test pin, causes the cost of this test macro to increase.And, because the structure of the included circuit of conventional semiconductor test system all is identical with performance for all test pin, thereby can not the while carry out dissimilar tests with parallel mode.
Why conventional semiconductor test system is provided with identical circuit structure in aforesaid all test pin, the result causes carrying out two or more dissimilar tests simultaneously, and one of its reason is that the configuration of this test macro is by adopting the test data based on the cycle to produce test pattern.Adopting notion to produce in the processing of test pattern based on the cycle, it is complicated that its software and hardware all is tending towards, and therefore, comprise different circuit structures and the software relevant with different circuit in this test macro, be practically impossible, do to make this test macro complicated more like this.
For more clearly explaining above-mentioned reason, according to waveform shown in Figure 3, two kinds of test patterns formations are done simple comparison, and a kind of test pattern constitutes the test data that adopts based on the form in cycle, and another kind of test pattern constitutes the test data that adopts based on the form of incident.Relatively be disclosed in more detail in the above-mentioned U.S. Patent application, this application belongs to the assignee identical with the present invention.
Shown in the example of Fig. 3, wherein, the generation of test pattern is according to the resulting data of implementing in the design phase of this integrated circuit (LSI) of logical simulation, and is stored in the dump file (dump file) 37.This dump file is output as the data based on the form of incident, represents the variation in the input and output of designed LSI (large scale integrated circuit) device, and contains the explanation 48 shown in Fig. 3 lower right, for example, is used to represent waveform 41.
In this example, suppose to constitute the test pattern shown in waveform 41 by adopting such explanation, this waveform 41 is illustrated as the test pattern of pin (tester pin or test channel) Sa and Sb generation respectively.The event data of describing this waveform is made up of set edge San, Sbn and sequential thereof the time period of a reference point (for example, since), reset edge Ran, Rbn and sequential thereof.
According to the notion based on the cycle, for generation is used for the test pattern of conventional semiconductor test system, this test data must be divided into test period (tester frequency), waveform (type of waveform and edge sequential thereof) and vector.The example of this description is as among Fig. 3 and shown in the left part.In the test pattern based on the cycle, shown in the waveform 43 of the left part of Fig. 3, test pattern is divided into waveform and the sequential (time-delay) of each test period (T1, T2 and T3) to describe each test period in detail.
For the example of the data declaration of this waveform, sequential and test period referring to shown in the time series data (test plan) 46.The example of the logical one of waveform, " 0 " or " Z " is shown in vector data (mode data) 45.For example, in time series data 46, test period is described by " frequency (rate) ", to define the time interval between test period; Waveform is described by RZ (making zero), NRZ (not making zero) and XOR (XOR).In addition, the sequential of each waveform is limited by the time-delay from one of corresponding test period predetermined sides edge.
As indicated above, because conventional semiconductor test system produces test pattern in the process based on the cycle, it is complicated that hardware configuration in mode generator, timing sequencer and the waveform format device is tending towards, and correspondingly, used software also becomes complicated in such hardware.In addition, owing to all test pin (for example Sa in above example and Sb) were limited by common test period, thereby the impossible test pattern that in each test pin, produces different cycles simultaneously.
Therefore, in the semiconductor test system of routine, same circuit structure is used to all test pin, can not make up the printed circuit board (PCB) of different circuit structures therein.Consequently, for example, the high speed test system also needs to comprise the hardware configuration (for example high voltage and large amplitude produce circuit and driver disable circuit, or the like) of low speed, and in such test macro, high speed performance can not get sufficient improvement.
On the contrary, for by adopting the method based on incident to produce test pattern, only need read the set/reset data and relevant time series data that are stored in the event memory, required hardware and software structure is very simple.And whether each test pin can have any incident and work independently according to it, rather than according to test period, therefore, can produce the test pattern of difference in functionality and frequency range simultaneously.
As mentioned above, the inventor of this invention has proposed the semiconductor test system based on incident.In this test macro,, a kind of total test macro that wherein is provided with different hardware and software might be proposed because the hardware and software that it comprised is all very simple on structure and content based on incident.And, because each test pin can work independently of each other, can be simultaneously carry out two or more different tests mutually on function and frequency range with parallel mode.
Therefore, the object of the present invention is to provide a kind of semiconductor test system, this system is provided with the different tester module of performance and corresponding with test pin.
Another object of the present invention is to provide a kind of semiconductor test system, in this system, by with the specification standardization that is connected between tester module and the tester main frame, make tester module can be mounted freely in the tester main frame (or measuring head) with different number of pins and performance.
Another purpose of the present invention is to provide a kind of semiconductor test system, and this system can freely hold high speed test device module and low speed tester module, thereby can test fully measured device with quite low cost.
Another purpose of the present invention is to provide a kind of semiconductor test system, this system is provided with a measuring head, according to the travelling speed of tester module, high speed test device module (board testei) and low speed tester module (board testei) are set differently in this measuring head.
Another purpose of the present invention is to provide a kind of testing efficiency height, semiconductor test system that testing cost is low, and the measured device that this system can test is for wherein being provided with the system-on-a-chip of a plurality of difference in functionality cores.
Semiconductor test system of the present invention comprises the mutually different tester module of two or more performances; A measuring head is used to hold the different tester module of these two or more performances; Be arranged on this measuring head and be used to be electrically connected the device of tester module and measured device; And a principal computer, it connects with the tester module by the tester bus, to control the overall operation of this test macro.The performance of tester module is a kind of to be the high time sequence precision of high speed, and the another kind of performance low time sequence precision that is low speed.
In semiconductor test system of the present invention, each tester module comprises a plurality of event tester plates, under the control of this principal computer, each board testei provides the respective pins of test pattern to measured device, and identifies the output signal that measured device produces therefrom.
In another aspect of this invention, in this measuring head, test fixing device and operation panel are more approached compared with the position of low accuracy test device module of low speed or board testei in the set position of high-speed, high precision tester module or board testei.
In a first aspect of the present invention, because semiconductor test system of the present invention has modular construction, required test macro can freely constitute according to the type of measured device and test purpose.If measured device is a high speed logic integrated circuit (IC), wherein in fact has only small part logical circuit high speed operation.Therefore, in order to test this high speed logic IC, a small amount of tester pin must carry out high speed test.In semiconductor test system of the present invention, the connection specification (interface) between measuring head and the tester module is standardized.Thereby any tester module with standard interface can both be installed in any position in this measuring head.Like this, in the present invention, by a large amount of low speed tester modules and a spot of high speed test device module combinations are got up, high speed device just can be tested with low cost.
In a second aspect of the present invention, in this system, be used for the position of installation testing device module or plate, determine according to aforesaid travelling speed.For example, the position that high-speed, high precision tester module or board testei are set will be more near measured device (therefore, also more near test fixing device and operation panel) compared with low accuracy test device module of low speed or the set position of board testei.In a first aspect of the present invention, in system, then different in a second aspect of the present invention, the position of its board testei can not freely change the tester module by independent assortment.Yet in a second aspect of the present invention, the test macro of desired properties can build up with low cost.
As mentioned above, in semiconductor test system of the present invention, tester module (board testei) the structure of employing based on incident be set, wherein carrying out the required full detail of test is with the format analysis processing based on incident.Therefore, no longer need employed frequency signal or mode generator in the routine techniques, this frequency signal is represented the beginning sequential of each test period, this mode generator and this frequency signal synchronous operation.Because do not need to comprise this frequency signal or this mode generator, in this test macro based on incident, each test pin can separately be carried out work in other test pin.And, owing to adopt structure, should can be reduced widely, and the software that is used to control the tester module also can be simplified significantly based on test system hardware of incident based on incident.Thereby, should can be reduced based on the total physical size of the test macro of incident, further reduce cost, reduce floor space therefrom and save relevant cost.
In addition, in semiconductor test system of the present invention, in the designs stage in the electric design automation workbench, logic simulation data can be directly used in the generation test pattern, with the device of Test Identification in the stage.Therefore, can significantly reduce the turnaround time between the evaluation of designs and device, thereby further reduce testing cost, improve testing efficiency simultaneously.
Further specify the present invention below in conjunction with accompanying drawing and preferred embodiment.
Fig. 1 is the basic configuration block scheme of a kind of semiconductor test system (LSI tester) in the routine techniques;
Fig. 2 is the profile synoptic diagram of a kind of semiconductor test system example in the routine techniques;
Fig. 3 is the chart that is used for two examples of comparison, one of them example is the explanation that produces in conventional semiconductor test system based on the test pattern in cycle, and another example is the explanation that produces in the present invention's semiconductor test system based on the test pattern of incident;
The synoptic diagram of Fig. 4 represents that to set up a semiconductor test system, the test pin that this system was provided with is divided by the difference of performance by making up a plurality of test modules of the present invention;
Fig. 5 is the block scheme according to the example of circuit arrangement in the event tester of the present invention, and this event tester is arranged in the event tester plate, and this event tester plate is combined in the tester module;
Fig. 6 is the profile synoptic diagram of semiconductor test system example of the present invention;
Fig. 7 is the block scheme of the example of semiconductor test system structure, this system is by the tester module (board testei) of a plurality of different test speeds of combination, be applicable to the measured device of test as system-on-a-chip, the structure based on incident among the present invention is adopted in the configuration of this system;
The synoptic diagram of Fig. 8 A and Fig. 8 B is represented the level according to test performance, and the example of the board testei of different test performances is set in measuring head.
According to Fig. 4 to Fig. 8 embodiments of the invention are described.Fig. 4 is the synoptic diagram of expression the present invention's first aspect.In semiconductor test system of the present invention, the configuration of measuring head (tester main frame) is that one or more modular testing devices (hereinafter referred to as " tester module ") selectively, freely are installed therein.The tester module of being installed can be a plurality of identical tester module that depends on required tester number of pins, or the combination of different tester modules, for example high-speed module HSM and low-speed module LSM.
Measuring head 124 disposes a plurality of tester modules, and for example this configuration is the number of pins that depends on test fixing device 127, the type of measured device and the number of pins of measured device.As described hereinafter, the interface between this test fixing device and the test module (connection) specification is standardized, so that make any tester module can be installed in any position in this measuring head.
Each tester module is provided with the pin set of predetermined quantity.For example, high-speed module HSM is installed in the printed circuit board (PCB) of corresponding 128 test pin (test channel), and low-speed module LSM is installed in the printed circuit board (PCB) of corresponding 256 test pin.List these numbers just for for the purpose of illustrating, the test pin of other different numbers also is possible.
High speed test device module is the tester module with high travelling speed and high time sequence precision, and for example test frequency is that 500MHz, time sequence precision are 80 psecs.Low speed tester module is the tester module with low travelling speed and low time sequence precision, and for example test frequency is that 125MHz, time sequence precision are 200 psecs.
As mentioned above, every block of plate in the tester module is provided with event tester, and each event tester produces test pattern, and by operation panel 128 test pattern is put on the corresponding pin of measured device.This measured device responds the output signal of this test pattern, is to be sent to event tester plate in the tester module by operation panel 128, and thus, this output signal is compared with wanted signal, to determine that this measured device is qualified or fault is arranged.
Each tester block configuration has an interface (connector) 126.The configuration of this connector 126 is suitable for the standard specification of test fixing device 127.For example, in the standard specification of this test fixing device 127, the regulation of the distance (pin-pitch) between the structure of connector pinout, the impedance of pin, the pin and the relative position of pin is the measuring head that is used to expect.By on all tester modules, adopting the interface (connector) 126 that adapts with this standard specification, can freely set up the test macro of the various various combinations of tester module.
Because structure of the present invention can be set up the test macro with the optimum performance price ratio that adapts with measured device.And, by replacing one or more test modules, can improve the performance of this test macro, therefore, can prolong this test macro total serviceable life.In addition, test macro of the present invention can hold a plurality of performances different test module mutually, thereby adopts corresponding test module, can directly realize the performance that this test macro is required.So, can easily directly improve the performance of this test macro,
The profile example synoptic diagram as shown in Figure 6 of semiconductor test system of the present invention.In Fig. 6, for example, a principal computer (main system computing machine) 62 is for being provided with a workstation of graphical user interface (GUI).The effect of this principal computer is as user interface and controller, to control the overall operation of this test macro.Principal computer 62 is by system bus 54 link to each other with this test macro internal hardware (seeing Fig. 5 and Fig. 7).
According to the mode generator and the timing sequencer that are adopted in the conventional semiconductor test system that notion disposed based on the cycle, in the present invention's test macro, but do not need based on incident.Therefore, by all modular event testers are installed, might reduce the physical size of whole test system greatly in measuring head (or tester main frame) 124.
The block scheme of Fig. 5 is represented the topology example of the event tester plate in the tester module.In above-mentioned Application No. 09/406,300 and Application No. 09/259,401 this test macro based on incident has been made more detailed description, these two patented claims belong to the assignee identical with this invention.
For example, controller 67 is set in each event tester plate, and the operation in the control event board testei, comprises the generation of incident (test pattern), the evaluation of measured device output signal and the collection of fault data.Controller 67 can be arranged at each board testei or whenever on several board testeis.In addition, controller 67 does not need to set up in the event tester plate, still, and can be by principal computer 62 directly to the firm and hard existing identical control function of event tester.
For example in the simplest situation, address control unit 58 is a programmable counter.These address control unit 58 controls offer the address of fault data storer 57 and event memory 60.The event-order serie data are sent to event memory 60 by principal computer, as test procedure, and are stored in wherein.
The aforesaid event-order serie data of event memory 60 storage, this data definition the sequential of each incident (from " 1 " to " 0 " and change point) from " 0 " to " 1 ".For example, the event-order serie data are stored as two kinds of data, a kind of integral multiple of representing the reference clock cycle, the fraction part of another kind of this reference clock of expression.Preferably, restore after these event-order serie data are compressed in the event memory 60.
The compression time series data decompress(ion) (reduction) that decompress(ion) unit 62 provides event memory 60.One sequential counting/calibration logic 63 produces the time span data of each incident by total or modification to the event-order serie data.These time span data are to represent the sequential of each incident from the time span (time-delay) of a reference point of being scheduled to.
In the above event tester of summarizing, adopt data based on the form of incident, produce the input signal that puts on measured device, and the wanted signal of comparing with the measured device output signal.In this form based on incident, the information in test signal and the wanted signal on the change point is made up of action message (set and/or reset) and temporal information (from the time span of a specified point).
As mentioned above, in conventional semiconductor test system, be the method that adopts based on the cycle, the desired memory capacity of this method is compared with little based on the desired capacity of the structure of incident.In the test macro based on the cycle, the temporal information of input signal and wanted signal is made up of cycle information (frequency or synchronizing signal) and delayed data.Input signal and wanted signal action message form by waveform mode data and mode data.In such configuration, delayed data can only be limited by the finite data amount.And, have adaptive mode data in order to produce, this test procedure must comprise therein a lot of circulations and (or) subroutine.Therefore, conventional semiconductor test system requires that complicated structure and working routine are arranged.
In test macro based on incident, there is no need to adopt based on structure and working routine so complicated in the conventionally test system in cycle, therefore increase easily test pin quantity and (or) in identical test macro, make up the test pin of different performance.Although the test macro based on incident needs jumbo storer, the increase of sort memory capacity is not a subject matter, because now, the increase of memory density and the reduction of memory cost have all obtained promptly, development constantly.
Example shown in Figure 7 represents that semiconductor test system of the present invention is used to test the situation of system-on-a-chip (system-on-chip).In this test macro, a plurality of tester modules are assigned to function corresponding core in this system-on-a-chip, so that identify interface and whole system-on-a-chip between each function core, each core.
As mentioned above, in a lot of situations of test high-speed semiconductor device, the test signal of small number of devices pin requirement high speed and high time sequence precision is only arranged, and the test of other device pin employing low speed and low time sequence precision test signal are just enough.The present invention is adapted to this actual conditions in the device detection, can carry out low cost, high-performance and high efficiency test to device.
Configuration of the present invention also is applicable to be tested the up-to-date semiconductor devices that wherein has built in self testing (BIST) function.The semiconductor devices of this BIST of having function comprises a BIST controller, and this controller is connected with internal circuit, and when this internal circuit of test, this controller has an external test.As relevant boundary scan TAP controller among the IEEE-1149.1 (standard) regulation, being connected of this BIST controller and tester is the interface of forming by by 5 pins, this interface requirement high-speed cruising.Therefore, in the example of Fig. 7, the tester module that is used for this purpose is represented by interface pin group (IPG) module.
In the example of Fig. 7, tester module 661 is a low-speed module (LSM), and tester module 662 is a high-speed module (HSM), and tester module 663 is BIST interface modules (IPG), and tester module 664 and 665 is low-speed module.In this example, suppose that the microprocessor core in this system-on-a-chip needs high speed test, and the function core of corresponding tester module 663 has the BIST function.Number of pins for each tester module 66 is distributed, and is the pin according to measured device (function core).The distribution of this number of pins can change according to the instruction that principal computer provides.
In the configuration of Fig. 7 system-on-a-chip being identified, is not directly to identify this system-on-a-chip, is to be tested by corresponding tester module corresponding to prepared each silicon integrated circuit (IC) of each function core.By system bus 54, main system (master) computing machine 62 provides the test board data to each tester module, and these data result from the design phase of this system-on-a-chip.According to these test board data, produce test pattern by the tester module.Made more detailed description for the evaluation of system-on-a-chip function in Application No. 09/428,746, this patented claim belongs to the assignee identical with this invention.
The synoptic diagram of Fig. 8 has shown a second aspect of the present invention, the figure illustrates the ios dhcp sample configuration IOS DHCP of printed circuit board (PCB) in the measuring head 224 of this semiconductor test system.For high speed and high time sequence precision tester module (or board testei), be necessary the signal path lengths between tester module and the measured device is reduced to minimum.On the other hand, for low speed and low time sequence precision tester module, allow to the longer signal path of measured device.
Therefore, shown in Fig. 8 A and Fig. 8 B, high speed test device module or high speed test device plate are set in the upper position of measuring head 224, and low speed tester module is set in the lower position of measuring head 224.In this was provided with, the signal path lengths by test fixing device 227 between high speed test device module and measured device can be shortened, thereby realized the high speed test operation.
In a second aspect of the present invention, the position of installation testing device module or plate is determined according to aforesaid travelling speed in this system.Be that the tester module freely is combined in this system in a first aspect of the present invention, then different in this example, the position of board testei can not arbitrarily change.This is to be fixed because the position of board testei is a travelling speed according to this board testei.Yet in a second aspect of the present invention, the test macro of desired properties can constitute with low cost.
As indicated above, because semiconductor test system of the present invention has modular construction, thereby can freely constitute required test macro according to the type and the test purpose of measured device.If measured device is a kind of high speed logic IC, small part logical circuit high-speed cruising is wherein in fact only arranged, therefore,, must there be a small amount of tester pin to have high speed performance in order to test this high speed logic IC.Therefore in the present invention, by making up a large amount of low speed tester modules and a small amount of high speed test device module, can realize a high speed test device with low cost.
And in semiconductor test system of the present invention, tester module (board testei) is configured to the structure based on incident, and wherein being used to carry out all required information of test all is with the format analysis processing based on incident.Therefore, be used for the frequency signal that the routine techniques expression begins sequential each test period, or with the mode generator of this frequency signal synchronous operation, all no longer needed.Owing to do not need to comprise frequency signal or mode generator, in this test macro based on incident, each test pin can be independent of other test pin and work.In addition,, should can be reduced significantly, and the software that is used to control the tester module can be simplified significantly based on the test system hardware of incident owing to adopt structure based on incident.Thereby, should can be reduced based on the total physical size of the test macro of incident, thereby cause further reducing cost, reducing floor space and save relevant cost.
Further, in semiconductor test system of the present invention, in the designs stage in electric design automation (EDA) workbench, logic simulation data can be directly used in the generation test pattern, is used at the validation phase test component.Therefore, can significantly reduce the turnaround time between the evaluation of designs and device, thereby further reduce testing cost, improve testing efficiency simultaneously.
Although only preferred embodiment has been done specific description and description here, has been understandable that according to the above with in the scope of accessory claim, without prejudice to spirit of the present invention and preset range, the present invention might make many modifications and variations.
Claims (14)
1, a kind of semiconductor test system comprises:
A measuring head is used to hold the different tester module of two or more performances;
Be arranged on this measuring head and be used to be electrically connected the coupling arrangement of tester module and measured device; And
One principal computer is used to control the overall operation of this test macro, and it connects with the tester module by a tester bus.
2, semiconductor test system according to claim 1, wherein, the performance of tester module is a kind of to be the high time sequence precision of high speed, and the another kind of performance low time sequence precision that is low speed.
3, semiconductor test system according to claim 1, wherein, the arrangements of electric connection between tester module and measured device is standardized with the specification that is connected of tester intermodule.
4, semiconductor test system according to claim 1, wherein, arrangements of electric connection between tester module and measured device is made up of an operation panel and a test fixing device, operation panel is provided with the mechanical hook-up that is used to install measured device, test fixing device is provided with the connection mechanical hook-up, is used for the electrical connection between this operation panel and the tester module.
5, semiconductor test system according to claim 1, wherein, a plurality of tester pins can be assigned to the tester module with changing.
6, semiconductor test system according to claim 1, wherein, a plurality of tester pins can be assigned to the tester module with changing, and the distribution of this test pin and change thereof are to be controlled by the address date of principal computer.
7, semiconductor test system according to claim 1, wherein, each tester module comprises a plurality of event tester plates, each event tester plate is assigned to the test pin of predetermined quantity.
8, semiconductor test system according to claim 7, wherein, each tester module is corresponding to an event tester plate.
9, semiconductor test system according to claim 1, wherein, each tester module comprises an internal controller, the instruction that this internal controller provides according to principal computer, control produces test pattern by this tester module, and identifies the output signal of measured device.
10, semiconductor test system according to claim 7, wherein, each tester module comprises a plurality of event tester plates, wherein each event tester plate comprises an internal controller, the instruction that this internal controller provides according to principal computer, control produces test pattern by this tester module, and identifies the output signal of measured device.
11, semiconductor test system according to claim 2, wherein, in this measuring head, this coupling arrangement is more approached compared with the position of the tester module of the low time sequence precision of low speed in the set position of the tester module of the high time sequence precision of high speed.
12, semiconductor test system according to claim 3, wherein, in measuring head, this coupling arrangement is more approached compared with the position of the tester module of the low time sequence precision of low speed in the set position of the tester module of the high time sequence precision of high speed.
13, semiconductor test system according to claim 1, wherein, measured device has BIST (built in self testing) function, and the tester module links to each other with BIST controller in the measured device, and produces the signal of IEEE 1149 prescribed by standard.
14, semiconductor test system according to claim 1, wherein, each tester module comprises a plurality of event tester plates, and each event tester plate is assigned to a test pin, and wherein each event tester plate comprises:
One controller, according to the instruction that principal computer provides, control produces test pattern by this tester module, and identifies the output signal of measured device;
One event memory is used to store the time series data of each incident;
One address sequence generator under the control of this controller, provides address date to this event memory;
Produce the device of test pattern according to the time series data of this event memory; And
One pin electronic circuit is used for test pattern is sent to the corresponding pin of measured device, and receives the response output signal of measured device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 01115701 CN1384366A (en) | 2001-04-29 | 2001-04-29 | Flexible modular semiconductor test system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 01115701 CN1384366A (en) | 2001-04-29 | 2001-04-29 | Flexible modular semiconductor test system |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456042C (en) * | 2003-09-03 | 2009-01-28 | 爱德万测试株式会社 | Test apparatus |
| CN101932943A (en) * | 2007-12-10 | 2010-12-29 | 株式会社It&T | Semiconductor device test system |
| US7919974B2 (en) | 2004-07-23 | 2011-04-05 | Advantest Corporation | Electronic device test apparatus and method of configuring electronic device test apparatus |
| CN104065528A (en) * | 2013-03-15 | 2014-09-24 | 美国网件公司 | Method And Apparatus For Analyzing And Verifying Functionality Of Multiple Network Devices |
| CN105874341A (en) * | 2013-11-19 | 2016-08-17 | 泰拉丁公司 | Automated test system with edge steering |
| CN112462248A (en) * | 2021-01-06 | 2021-03-09 | 浙江杭可仪器有限公司 | Test signal output system and use method thereof |
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2001
- 2001-04-29 CN CN 01115701 patent/CN1384366A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100456042C (en) * | 2003-09-03 | 2009-01-28 | 爱德万测试株式会社 | Test apparatus |
| US7919974B2 (en) | 2004-07-23 | 2011-04-05 | Advantest Corporation | Electronic device test apparatus and method of configuring electronic device test apparatus |
| CN101932943A (en) * | 2007-12-10 | 2010-12-29 | 株式会社It&T | Semiconductor device test system |
| CN101932943B (en) * | 2007-12-10 | 2013-03-20 | 株式会社It&T | Semiconductor device test system |
| CN104065528A (en) * | 2013-03-15 | 2014-09-24 | 美国网件公司 | Method And Apparatus For Analyzing And Verifying Functionality Of Multiple Network Devices |
| CN104065528B (en) * | 2013-03-15 | 2019-09-13 | 美国网件公司 | For analyzing and examining functional method and apparatus of multiple network equipments |
| CN105874341A (en) * | 2013-11-19 | 2016-08-17 | 泰拉丁公司 | Automated test system with edge steering |
| CN105874341B (en) * | 2013-11-19 | 2019-07-12 | 泰拉丁公司 | Automatization test system with edge guiding |
| CN112462248A (en) * | 2021-01-06 | 2021-03-09 | 浙江杭可仪器有限公司 | Test signal output system and use method thereof |
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