CN1379468A - Electrostatic protector of chip - Google Patents
Electrostatic protector of chip Download PDFInfo
- Publication number
- CN1379468A CN1379468A CN01110316A CN01110316A CN1379468A CN 1379468 A CN1379468 A CN 1379468A CN 01110316 A CN01110316 A CN 01110316A CN 01110316 A CN01110316 A CN 01110316A CN 1379468 A CN1379468 A CN 1379468A
- Authority
- CN
- China
- Prior art keywords
- pin
- chip
- conducting strip
- idle
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Elimination Of Static Electricity (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
This invention discloses a chip electrostatic protection device which includes setting up a conductive plate on the chip surface to be electrically connected with idle connecting legs on chips to lead the static electricity accumulated on the idle connecting leg to the conducting plate, then to eliminate the static electricity using the discharging of equivalent capacity between the conductive plate and the chip, or lead the static electricity to the earth, or to the power source by electric connection of the conductive plate with other connecting legs so as to avoid idle connecting leg transient discharging causing damage to surrounding connecting legs.
Description
The present invention relates to a kind of protective device of chip, and be particularly related to a kind of conductive characteristic that utilizes conducting strip, eliminate the static that is accumulated on the chip pin, with the electrostatic protection device of avoiding pin to damage.
Along with science and technology is constantly progressive, the volume of integrated circuit package also constantly dwindles, and integrated level also improves day by day; Therefore, how strong the and pin count of little, the function of volume has become the main characteristic of current chip.In general practical application, for normal some elasticity of the configuration of chip pin; The common practice lies in required functional pin and sets up several idle pins outward in addition, in case of need; Wherein these functional pins can couple with power end, earth terminal or signal end, to possess this function.Because chip volume is little and pin count is many, so pin distance to each other is narrow and small unusually, when the situation of discharge takes place a certain pin, often cause near the damage of its pin, its detailed situation will be in hereinafter being narrated.
As noted before, general in the configuration of chip pin, regular meeting arranges several idle pins in case of need, and the elasticity can increase circuit layout the time.Please refer to Fig. 1, it represents a kind of allocation plan of existing chip pin.For the purpose of simplified, only express ground connection pin 110, power pin 120, functional pin 130 and the idle pin 140 of chip 100 among the figure; Wherein ground connection pin 110 is suitable for being coupled to earth terminal, power pin 120 is fitted with power end and is coupled, functional pin 130 then can be input port (input port), output port (output port) or the input/output port (I/O port) etc. of chip, the window that inputs or outputs as signal.As shown in the figure, 110a couples brace (bonding pad) in ground connection pin 110 and the chip 100, power pin 120 couples with brace 120a in the chip 100,130 of functional pins and chip 100 interior brace 130a couple, to keep the normal operation of chip; In addition, idle pin 140 with chip 100 in any braces do not couple, so in the ordinary course of things, for chip 100, idle pin 140 does not have any function, only as the usefulness of standby pin.
Generally speaking, when chip 100 work, can gather static on the idle pin 140, when charges accumulated surpasses critical value, promptly can take place the static discharge phenomenon (electrostaticdischarge, ESD).Because the pin configuration scenario of current chip is quite intensive, so when ESD betided on the idle pin 140, this ESD stress (ESD stress) just directly influenced the functional pin around it, pin damages near causing.Some research reports point out that ESD stress seldom is lower than 3.5 kilovolts (KV), when the moment that ESD stress takes place, can produce big electric current (for example 1.0 to 1.7 amperes) at idle pin 140 and 130 of functional pins; Usually, the idle pin 140 of peak current (peak current) received on functional pin 130 is high, so these electric discharge phenomena are also more serious than idle pin 140 to the influence that functional pin 130 causes.Therefore, because the static discharge phenomenon of idle 140 pairs of functional pins 130 of pin often causes functional pin seriously to be damaged, make the chip 100 can't normal operation.
Therefore purpose of the present invention is exactly the electrostatic protection device that is to provide a kind of chip, can effectively eliminate the static that is gathered on the idle pin, avoids ESD stress that functional pin is caused damage, to keep the normal operation of chip.
For reaching above-mentioned and other purpose, the invention provides a kind of electrostatic protection device of chip, a conducting strip is set, and will leave unused pin and conducting strip couple on chip.So when idle pin is accumulated static, electric charge can be directed in the conductive plate, utilize the equivalent capacity effect of conductive plate and chip chamber, electric charge can be got rid of.Certainly, conducting strip more can couple with the ground connection pin, in order to electric charge is directed to earth terminal; Or couple with power end, directly static is absorbed.
Chip electrostatic protective device provided by the present invention can effectively prevent electrostatic accumulation in idle pin place, causes near the damage just like I/O port etc. of functional pin it when avoiding idle pin discharge, makes chip be able to operate as normal.Utilizing conducting strip that static is got rid of is one of important technology feature of the present invention.
For above and other objects of the present invention, feature and advantage can be become apparent, especially exemplified by a preferred embodiment, and conjunction with figs., be described in detail below:
Fig. 1 is a kind of allocation plan of known chip pin;
Fig. 2 A to Fig. 2 c is according to a preferred embodiment of the present invention, the electrostatic protection device schematic diagram of a kind of chip that is provided.
Wherein, parts and Reference numeral are respectively:
100 chips; 110 ground connection pins; The 110a brace;
120 power pins; The 120a brace; 130 functional pins;
The 130a brace; 140 idle pins;
20 chips; 200 conducting strips; 210 ground connection pins;
220 power pins; 230 functional pins; 240 idle pins.
Embodiment:
Please refer to Fig. 2 A to Fig. 2 C, is according to a preferred embodiment of the present invention, the electrostatic protection device schematic diagram of a kind of chip that is provided.Shown in Fig. 2 A, the surface of chip 20 is provided with conducting strip 200, and wherein conducting strip 200 can be a metal material or other can reach this similar materials with function.Idle pin 240 is and conducting strip 200 electric property couplings when idle pin 240 is accumulated static, can electric charge be imported conducting strips 200 by idle pin 240 by this annexation, and utilize the capacity effect of conducting strip 200 and 20 formation of chip that static is got rid of; So, can avoid buildup of static electricity on idle pin 240, also eliminate the harm that static discharge is caused functional pin 230.Fig. 2 B represents the device that another is similar, and conducting strip 200 also couples with ground connection pin 210 except that being coupled to idle pin 240, so, can directly electric charge be got rid of with the electric charge on the conducting strip 200 via ground connection pin 210 guiding earth points (not drawing).In addition, these electrostatic protection devices also can be realized that conducting strip 200 is except that being coupled to idle pin 240 by Fig. 2 c; also couple with power pin 220; because power pin 220 couples with conducting strip 200,, and has high potential so conducting strip itself promptly links to each other with power end.Therefore, the electric charge on the conducting strip 200 can be absorbed by power supply, to avoid electrostatic accumulation.
It should be noted that, though embodiments of the invention system implements the guiding work of static at the idle pin in the chip, yet be not in order to limiting using time of the present invention, the person skilled in the art is applied to these devices should not break away from spirit of the present invention on other chip pin.
The above only is preferred embodiment of the present invention; yet it is not in order to limit the present invention; any personnel that have the knack of this technology; without departing from the spirit and scope of the present invention; when can be used for various modifications and upgrading; therefore protection scope of the present invention should be as the criterion with the protection range that claims limit, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the claim scope of patent of the present invention.
Claims (10)
1. the electrostatic protection device of a chip is characterized in that comprising:
One conducting strip is located at this chip top;
One idle pin is electrically connected with this conducting strip;
One ground connection pin is electrically connected with this conducting strip.
2. device according to claim 1 is characterized in that: it comprises that also a power pin is electrically connected with this conducting strip.
3. device according to claim 1 and 2 is characterized in that: this conducting strip is a metal material.
4. the electrostatic protection device of a chip is characterized in that comprising:
One conducting strip is positioned at the surface of this chip;
One idle pin is electrically connected with this conducting strip;
One power pin is electrically connected with this conducting strip.
5. device according to claim 4 is characterized in that: it comprises that also a ground connection pin is electrically connected with this conducting strip.
6. according to claim 4 or 5 described devices, it is characterized in that: this conducting strip is a metal material.
7. the electrostatic protection device of a chip is characterized in that comprising:
One conducting strip is positioned at the surface of this chip;
One idle pin is electrically connected with this conducting strip;
One functional pin is electrically connected with this conducting strip.
8. device according to claim 7 is characterized in that: this functional pin is the ground connection pin.
9. device according to claim 8 is characterized in that: this functional pin is a power pin.
10. according to claim 7,8 or 9 described devices, it is characterized in that: this conducting strip is a metal material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011103167A CN1160788C (en) | 2001-04-03 | 2001-04-03 | Electrostatic protector of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011103167A CN1160788C (en) | 2001-04-03 | 2001-04-03 | Electrostatic protector of chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1379468A true CN1379468A (en) | 2002-11-13 |
| CN1160788C CN1160788C (en) | 2004-08-04 |
Family
ID=4658501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011103167A Expired - Fee Related CN1160788C (en) | 2001-04-03 | 2001-04-03 | Electrostatic protector of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1160788C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751263A (en) * | 2012-07-27 | 2012-10-24 | 上海华力微电子有限公司 | Static-proof integrated circuit structure |
| CN104614664A (en) * | 2015-01-29 | 2015-05-13 | 晶焱科技股份有限公司 | Static electricity eliminated testing method |
| CN110673452A (en) * | 2019-10-17 | 2020-01-10 | 中山市高尔乐塑胶制品有限公司 | Selenium drum shell convenient to assemble and assembling method of selenium drum shell |
| CN111627891A (en) * | 2020-06-05 | 2020-09-04 | 中芯集成电路（宁波）有限公司 | Semiconductor structure and chip packaging method |
| WO2020253302A1 (en) * | 2019-06-18 | 2020-12-24 | 京东方科技集团股份有限公司 | Electrode structure, capacitor, goa circuit, array substrate, and display panel and device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101414660B (en) * | 2007-10-19 | 2010-08-25 | 佳邦科技股份有限公司 | Procedure and structure for array type electrostatic protection element |
-
2001
- 2001-04-03 CN CNB011103167A patent/CN1160788C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102751263A (en) * | 2012-07-27 | 2012-10-24 | 上海华力微电子有限公司 | Static-proof integrated circuit structure |
| CN104614664A (en) * | 2015-01-29 | 2015-05-13 | 晶焱科技股份有限公司 | Static electricity eliminated testing method |
| CN104614664B (en) * | 2015-01-29 | 2018-03-23 | 晶焱科技股份有限公司 | Eliminate the method for testing of electrostatic |
| WO2020253302A1 (en) * | 2019-06-18 | 2020-12-24 | 京东方科技集团股份有限公司 | Electrode structure, capacitor, goa circuit, array substrate, and display panel and device |
| US11803088B2 (en) | 2019-06-18 | 2023-10-31 | Beijing Boe Technology Development Co., Ltd. | Electrode structure, capacitor, goa circuit, array substrate, display panel and display device |
| CN110673452A (en) * | 2019-10-17 | 2020-01-10 | 中山市高尔乐塑胶制品有限公司 | Selenium drum shell convenient to assemble and assembling method of selenium drum shell |
| CN111627891A (en) * | 2020-06-05 | 2020-09-04 | 中芯集成电路（宁波）有限公司 | Semiconductor structure and chip packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1160788C (en) | 2004-08-04 |
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| Date | Code | Title | Description |
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040804 |