CN1378253A - Method for producing semiconductor module with raised source/drain area - Google Patents
Method for producing semiconductor module with raised source/drain area Download PDFInfo
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- CN1378253A CN1378253A CN 01110417 CN01110417A CN1378253A CN 1378253 A CN1378253 A CN 1378253A CN 01110417 CN01110417 CN 01110417 CN 01110417 A CN01110417 A CN 01110417A CN 1378253 A CN1378253 A CN 1378253A
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Abstract
The semiconductor module producting process forms raised source and drain areas on the substrate. The raised source and drain areas are then used as reaction material in the subsequent metal silicide forming course and this can avoid the consumption of original silicon in the source and drain area. Raised silicon material areas are formed on the substrate in the source and drain areas of the semiconductor module to be formed. On the raised silicon material, grid dielectric layer and grid electrode layer are formed successively to form the grid structure. Doping implantation, forming the wall isolation and re-doping implantation are performed successively.
Description
The present invention relates to a kind of manufacturing method of semiconductor module, particularly a kind of MOS assembly manufacture method that is applicable to that deep-submicron (deep submicron) manufacturing process is made.
Along with the continuous evolution of manufacturing technology, the precision of manufacturing has progressed into the field of deep-submicron.In deep sub-micron fabrication, the component parameter of many component parameters (for example live width) during compared with existing technology is little a lot.Realize that with less size circuit unit no doubt has the advantage of high integration, but therefore manufacture method itself also meets with a more difficult problem.The present invention mainly is at the metal oxide semiconductor transistor with shallow junction structures (MOStransistor), owing to be subjected to the factor that size of components diminishes, and may aim at the problem of destroying shallow junction structures in the metal silication manufacture method automatically, a kind of new solution is proposed.
Shallow junction structures mainly is source electrode (source) and the drain electrode (drain) that is applied in the MOS assembly, makes the cloth of source electrode and drain electrode plant the more shallow junction structure of district's formation, can avoid horizontal proliferation, so as to improving the characteristic of MOS assembly.Along with diminishing of manufacturing process size, shallow junction structures also will be followed more and more shallowly in source electrode and drain electrode.In addition on the one hand, after finishing, the MOS assembly (formed corresponding grid, source electrode and drain electrode), generally can aim at the metal silication manufacturing process automatically, so that in grid, source electrode and drain electrode, form metal silicide, to improve the junction characteristic (that is reducing its contact resistance) between each assembly electrode and the follow-up wiring.Yet so automatic aligning silication technique for metal but may destroy the shallow junction structures in deep-submicron is made.
In the general automatic aligning silication technique for metal, be earlier to finish on the assembly metal material of question response, for example titanium (Ti) on the sputter.Impose high temperature again, make and carry out chemical reaction between the silicon materials of this metal level and below, form required metal silicide (TiSi for example
x).And other has neither part nor lot in the metal material of reaction, and for example the metal material on the sidewall spacers of grid side is then removed, and so just can form required metal silicide.By above description as can be known, metal silication reacts except needs jet-plating metallization material, and also needing originally, the silicon materials on each electrode just can carry out.Therefore, during as if formation metal silicide in the source/drain electrode of shallow junction, certainly will consume quite a large amount of silicon materials, special under the situation of shallow junction, probably can destroy the structure of former origin/drain electrode.
To the problems referred to above, the solution that is proposed mostly is before aiming at the metal silication manufacturing automatically so far, provides extra silicon materials to react earlier, avoids consuming the silicon that there is source/drain electrode in too much script.For example, after the making of finishing each electrode of assembly itself (as grid and source/drain electrode), plant the mode of (implant) silicon with cloth, extra silicon raw material on adding in source/drain electrode, or in the mode of selectivity crystal extension (epitaxial), the extra silicon of deposition in source/drain electrode.So these extra silicon that add just can participate in reaction in carrying out the metal silication reaction subsequently, with the consumption of silicon in minimizing source/drain region.
Yet therefore existing processing mode still can exist many problems owing to be to carry out after finishing assembly.For instance, can directly add silicon though cloth is planted the mode of silicon, be difficult to guarantee that the silicon that extra cloth is planted can not appear on the zone of non-source/drain electrode, similarly be on the sidewall spacers (sidewall spacer) of grid side.In other words, these cloth are implanted in the silicon in zone outside source/drain electrode, also may participate in the metal silication reaction and produce metal silicide, make the inter-module electrode phenomenon of short circuit occur.Similarly be selectivity brilliant mode of heap of stone in addition, no doubt the zone of its silicon wafer growth can be controlled, and the temperature during still general enforcement all is considerably high, about 800 ℃～1100 ℃, all is unfavorable for manufacturing cost and production efficiency greatly.
In view of this, main purpose of the present invention, be to provide the assembly manufacture method of a kind of bed hedgehopping source/drain region, except solving the problem that is caused when automatic aligning metal silication is reflected at shallow junction, not only can not cause the interelectrode short circuit phenomenon of assembly, simultaneously do not need special high-temperature process yet, can implement.
Purpose of the present invention can reach by following measure:
The assembly manufacture method of a kind of bed hedgehopping source/drain region comprises the following steps:
If a bed hedgehopping uses silicon material layer on a substrate, and place the source/drain region of semiconductor subassembly to be formed;
On this bed hedgehopping this substrate, establish a gate dielectric layer with silicon material layer and exposure;
On this gate dielectric layer, establish a grid electrode layer;
This grid electrode layer of etching forms a grid structure on the gate regions of semiconductor subassembly to be formed;
To this bed hedgehopping silicon material layer and this substrate, the cloth that mixes is gently planted;
In the side of this grid structure, establish sidewall spacers; And
This bed hedgehopping with silicon material layer and this substrate, is carried out heavy doping cloth and plants.
The assembly manufacture method of a kind of bed hedgehopping source/drain region comprises the following steps:
If a bed hedgehopping uses silicon material layer on a substrate, and place the source/drain region of semiconductor subassembly to be formed;
On the gate regions of semiconductor subassembly to be formed, establish a grid structure of this semiconductor subassembly, this bed hedgehopping is an isolation with the electrode in silicon material layer and this grid structure; And
Cloth is planted this bed hedgehopping and is used silicon material layer and this substrate in the source/drain region of semiconductor subassembly to be formed, to form the source/drain electrode of this semiconductor subassembly;
Whereby, this bed hedgehopping in follow-up gold layer silication made, can form corresponding automatically gold layer silicide area with silicon material layer in order to react with a metal material layer in the source/drain electrode of this semiconductor subassembly.
The invention still further relates to the assembly manufacture method of a kind of bed hedgehopping source/drain region in addition, comprise the following steps:
If a bed hedgehopping uses silicon material layer on a substrate, and place the source/drain region of semiconductor subassembly to be formed;
On the gate regions of semiconductor subassembly to be formed, establish a grid structure of this semiconductor subassembly, this bed hedgehopping is an isolation with the electrode in silicon material layer and this grid structure;
Cloth is planted this bed hedgehopping and is used silicon material layer and this substrate in the source/drain region of semiconductor subassembly to be formed, to form the source/drain electrode of this semiconductor subassembly;
In this grid structure and this source/drain electrode of this semiconductor subassembly, establish a metal level; And
This bed hedgehopping silicon material layer in the source/drain electrode of this metal level of thermal response and this semiconductor subassembly, so as in this source/drain electrode forms and to aim at metal silicide automatically.
The present invention has following advantage compared to existing technology:
According to above-mentioned purpose, the present invention proposes a kind of method for producing semiconductor module, in order to form the semiconductor subassembly of the source/drain region with bed hedgehopping on substrate.Before forming semiconductor subassembly, at first form a bed hedgehopping and use silicon material layer on substrate, it places the source/drain region of semiconductor subassembly to be formed.Between the pre-defined gate position of this bed hedgehopping, there is a spacer region, can reserves the position of sidewall spacers whereby, also avoid contingent contact problems between electrode with silicon material layer and semiconductor subassembly.
Then, form gate dielectric layer and grid electrode layer at bed hedgehopping in regular turn on silicon material layer.By etch processes, just can form grid structure.Then as at present the MOS assembly manufacture method is identical, carries out light dope cloth in regular turn and plants, and forms sidewall spacers and carries out heavy doping cloth and plant.The bed hedgehopping that is exposed silicon material layer just can be used as the raw material that metal silication reacts, so that aim at the metal silication manufacture method automatically.
Manufacturing method of semiconductor module of the present invention, be applicable to the MOS assembly that deep-submicron (deepsubmicron) manufacturing process is made, the MOS assembly of manufacturing has the source electrode and the drain electrode of bed hedgehopping (elevated), can be at follow-up automatic aligning metal silication manufacture method (self-aligned silicidization, salicide) in, utilize the source electrode and the drain portion of bed hedgehopping to assign to carry out the metal silication reaction, avoid destroying utmost point shallow junction (ultra-shallowjunction) structure, improve the qualification rate that manufactures a product.
In an embodiment, this bed hedgehopping silicon material layer is to adopt polysilicon as material, and its thickness then titanium amount and the reaction condition of visual response decides.
In the present invention, forming above-mentioned bed hedgehopping can carry out according to following mode with silicon material layer.
First kind of mode is to form one earlier to sacrifice dielectric substance layer on substrate, utilizes the optical etching method again, and the etch sacrificial dielectric substance layer becomes a grid cover curtain (mask), with the gate regions that covers semiconductor subassembly to be formed.Then form a silicon material layer on grid cover curtain and substrate, remove top and peripheral part that silicon material layer places the grid cover curtain again, in order to form the bed hedgehopping silicon material layer.The mode of removing can be utilized the grid light shield to reach for the mode of cover curtain, or utilize chemical-mechanical polishing (CMP) mode to reach.At last remove above-mentioned grid cover curtain again, so just formed required bed hedgehopping silicon material layer.
The second way is to form a silicon material layer and a dielectric substance layer in regular turn on substrate.Then according to the grid light shield, and use the technology of photoetch, in the above-mentioned dielectric substance layer of etching in the part of semiconductor subassembly gate regions to be formed, so as to exposing above-mentioned silicon material layer.With exposed portions in the above-mentioned silicon material layer of thermal oxidation, make it form a thermal oxide layer again.The last nubbin of removing above-mentioned thermal oxide layer and above-mentioned dielectric substance layer again is so just formed required bed hedgehopping silicon material layer.
Utilize the source electrode and the drain portion of bed hedgehopping to assign to carry out the metal silication reaction, avoid destroying super shallow junction (ultra-shallow junction) structure, improve rate of finished products.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below:
Illustrate
Fig. 1 to Figure 11 represents the section schematic flow sheet of the method for producing semiconductor module in the first embodiment of the invention.
Figure 12 to Figure 15 represents the section schematic flow sheet of the method for producing semiconductor module in the second embodiment of the invention, particularly forms the processing section of bed hedgehopping with compound crystal silicon layer.
Figure 16 to Figure 18 represents the section schematic flow sheet of the method for producing semiconductor module in the third embodiment of the invention, particularly forms the processing section of bed hedgehopping with compound crystal silicon layer.Symbol description:
1 ~ silicon substrate; 10 ~ sacrificial oxide layer; 10a, 10b ~ grid cover curtain; 12 ~ polysilicon layer; 12a ~ bed hedgehopping polysilicon layer; 16 ~ grid oxic horizon; 18 ~ gate polysilicon layer; 18a ~ gate electrode; 20 ~ lightly-doped source/drain region; 22 ~ heavy-doped source/drain region; 30 ~ sidewall spacers; 40 ~ titanium coating; 42 ~ (grid) titanium silicides; 44 ~ (source/drain electrode) titanium silicides; 60 ~ polysilicon layer; 62 ~ dielectric substance layer; 64 ~ thermal oxide layer; 97,98,99 ~ photoresist layer.
In order to solve the scheme that shallow junction structures may destroyed problem, also be to add the loss that the further silicon material comes silicon materials in minimizing source/drain electrode basically among the present invention, but the difference of this and prior art maximum is the opportunity that forms.Traditional way is after assembly basic structure is finished, the mode of utilizing selectivity crystal extension or cloth to plant again, the source/drain region in the bed hedgehopping MOS assembly.Yet as mentioned above, the cost of source/drain region is higher relatively in the bed hedgehopping MOS assembly at this moment, has other problem in addition.Therefore, solution proposed by the invention is that elder generation with the silicon materials bed hedgehopping, so just can utilize better simply mode to form source/drain region, has overcome the shortcoming of prior art before whole M OS assembly is made as yet.Below cooperate diagram, utilize a plurality of embodiment that technology contents of the present invention is described.
Embodiment one
Fig. 1 to Figure 11 represents the section schematic flow sheet of the method for producing semiconductor module in the embodiment of the invention one.As previously mentioned, characteristics of the present invention are the opportunity of bed hedgehopping source/drain region, that is before not forming the MOS assembly, carry out the processing of bed hedgehopping source/drain region.Order according to Fig. 1 to Figure 11, below describe the whole manufacturing process of MOS assembly in the present embodiment in detail, and this whole manufacturing process can be divided into four-stage, be respectively bed hedgehopping source/drain region (as shown in Figures 1 to 4), form grid structure (as shown in Figure 5 and Figure 6), the lightly doped drain of formation source/drain region (LDD) structure (extremely shown in Figure 9) as Fig. 7, and form aligning metal silicide (salicide) (as shown in Figure 10 and Figure 11) automatically.
A. bed hedgehopping source/drain region:
In Fig. 1, at first on silicon substrate 1, form a sacrificial oxide layer 10.The effect of sacrificial oxide layer 10 is the gate location that are used for protecting MOS assembly to be formed on the silicon substrate 1, the unlikely pollution that is subjected to follow-up manufacturing.In the present embodiment, the thickness of sacrificial oxide layer 10 greatly about about hundreds of , form then can adopt chemical vapour deposition (CVD) (chemically vapor deposition, CVD) or other depositional mode form.In addition, present embodiment is the example explanation with the oxide, but can use other dielectric material equally.Then then be the grid light shield that utilizes in making, on sacrificial oxide layer 10, define zone, photoresist layer 99 as shown in fig. 1 corresponding to grid.
With reference to figure 2, utilize photoresist layer 99 as etching mask, sacrificial oxide layer 10 can be etched into grid cover curtain 10a, cover the top of grid in the MOS assembly to be formed.Then, above grid cover curtain 10a and silicon substrate 1, deposit a compound crystal silicon layer 12.The effect of this polysilicon layer 12 promptly is to be used for the silicon materials of bed hedgehopping MOS assembly to be formed source/drain electrode.The thickness of the polysilicon layer 12 that is deposited, relevant with follow-up automatic aligning metal silication manufacturing process basically.As previously mentioned, the silicon materials of bed hedgehopping source/drain electrode are to be used for participating in silicification reaction, to avoid a large amount of silicon that are present in source/drain electrode originally that consume.So, the thickness that polysilicon layer 12 is required, apparent is aimed at titanium amount and the time of reaction and decide of metal silication in making automatically.In the present embodiment, about 200 s～400 s between, so must look practical application situation and make an amendment greatly by this thickness for polysilicon layer 12.
With reference to figure 3, then again with the grid light shield increase a set interval (be L '-L), with polysilicon layer 12 above grid cover curtain 10a and peripheral part remove, obtain required bed hedgehopping polysilicon layer 12a.2 mandatory declarations are arranged herein.The first, the set interval of being adopted in this step (L '-L), except being is used for keeping the space of predetermined formation sidewall spacers (sidewall spacer), the more important thing is the grid in the MOS assembly and source/drain electrode are kept apart, with the phenomenon of avoiding being short-circuited.The second, grid cover curtain 10a can reach the purpose in protection channel (channel) zone herein, that is is unlikely because of etched effect and is corrupted to the characteristic of silicon substrate 1 at channel region.
At last,, utilize B.O.E solution or hydrofluoric acid etc., remove the grid cover curtain 10a stay on the area of grid, source/drain region that so just can bed hedgehopping MOS assembly with reference to figure 4.
B. form grid structure:
Behind the source/drain region that utilizes compound crystal silicon bed hedgehopping MOS assembly, then be the grid part that forms assembly.As shown in Figure 5, use on polysilicon layer 12a and the silicon base 1 at bed hedgehopping in regular turn, form grid oxic horizon 16 and gate polysilicon layer 18.Grid oxic horizon 16 is generally quite thin, and as the interlayer structure of MOS assembly, gate polysilicon layer 18 then is after cloth is planted, as the electrode part of grid.
Then as shown in Figure 6, utilize the grid light shield,, define grid structure 18a with photolithography etch processes gate polysilicon layer 18.In addition, in Fig. 6, will not remove in the lump at the grid oxic horizon 16 of non-area of grid.The advantage that keeps grid oxic horizon 16 herein is to plant in the process of source/drain electrode at follow-up cloth, plants resilient coating as a cloth, is subjected to the direct bump that cloth is planted ion in order to avoid the bed hedgehopping in the present embodiment with polysilicon layer.Yet, can also in this step, define grid oxic horizon 16 in the lump during practical operation, still go for the present invention.At last as shown in Figure 6, can on silicon substrate 1, form required grid structure 18a.
C. the heavy and light cloth that forms source/drain electrode is planted the district:
It then then is the source/drain region that forms in the MOS assembly.Be that (lightly doped drain, LDD) the MOS assembly of structure is that example describes, but goes for equally in the MOS assembly of other type to have lightly doped drain in the present embodiment.At first, carry out light dope cloth and plant with structure shown in Figure 6.So can on the pairing silicon substrate of source/drain electrode 1 position, form the cloth that mixes gently and plant district 20.
Then be side formation sidewall spacers 30, as shown in Figure 8 at grid structure 18a.The general mode that forms sidewall spacers 30 is to deposit a uniform dielectric substance layer (for example silicon nitride or silica), then this dielectric substance layer of anisotropic etching earlier on the whole base plate surface.Because near the part of this dielectric substance layer grid side, the thickness on the vertical direction is bigger, therefore behind anisotropic etching, and still can be residual and form required sidewall spacers.In this step, script, then can be removed when making sidewall spacers 30 with the grid oxic horizon 16 on the polysilicon layer 12a in the lump at bed hedgehopping.
At last as shown in Figure 9, the cover curtain that utilizes sidewall spacers 30 to plant as cloth carries out heavy doping cloth and plants, and plants district 22 and form heavy doping cloth in the source/drain region of MOS assembly.District 22 planted by heavy doping cloth and the cloth that mixes is gently planted LDD structure source/drain region that district 20 promptly constitutes the MOS assembly.At this moment, the pith of whole M OS assembly has been finished making all, and bed hedgehopping then is exposed on the outside with polysilicon layer 12a.Plant creating conditions in detail of district and sidewall spacers and thin portion operating sequence as for forming the cloth that weigh/mixes gently in above-mentioned, identical with existing LDD manufacturing process basically, repeat no more herein.
D. form and aim at metal silicide automatically:
At last, utilize the bed hedgehopping polysilicon layer 12a that exposes, implement to aim at automatically the metal silication manufacturing process.In Figure 10,, on whole M OS assembly, form a titanium coating 40 at first with sputtering way.Titanium coating 40 herein is as the reaction metal in the metal silication reaction, yet for knowing art technology person, can also adopt other metal applicatory to react.
Then then be to carry out the metal silication reaction.At first utilize Rapid Thermal reaction, make Titanium in the titanium coating 40, with polysilicon in the grid and bed hedgehopping with the polysilicon of polysilicon layer 12a (being arranged in source/drain electrode), react generation TiSi
2(titanium silicide).The TiSi that produces
2The characteristic of the low contact impedance of each electrode can be provided.As for having neither part nor lot in reaction or the not Titanium of complete reaction, the particularly titanium on sidewall spacers 30, then be to utilize wet etching to be removed, and in grid and source/drain electrode, stay TiSi
2At last, as shown in figure 11, grid and source/drain electrode place at the MOS assembly produces titanium silicide 42 and titanium silicide 44 respectively.In the present embodiment, the titanium silicide 44 that source/drain electrode place forms mainly is to utilize bed hedgehopping to carry out silicification reaction with the silicon that provides among the polysilicon layer 12a, therefore, even may use the silicon that is present in silicon substrate 1 source/drain region, also be unlikely the structure that has influence on shallow junction.
According to the manufacturing step described in the present embodiment, not only can react to aim at metal silication automatically bed hedgehopping source/drain region, can not produce simultaneously as prior art problems yet.For example, when forming bed hedgehopping, do not need to use too high temperature with polysilicon layer 12a.On the other hand,, therefore can control its position easily, be unlikely the phenomenon that behind silicification reaction, causes short circuit in source/drain electrode because bed hedgehopping is a made before forming the MOS assembly with polysilicon layer 12a.
Embodiment two
As previously mentioned, key point of the present invention is the opportunity of bed hedgehopping source/drain region, then not necessarily is limited to as shown in Figures 1 to 4 mode as for the mode of bed hedgehopping.So present embodiment then is the mode that proposes another kind of bed hedgehopping source/drain region, and it remained before making the MOS assembly and implements.
Figure 12 to Figure 15 represents among second embodiment that expression is at the treatment step flow chart of bed hedgehopping source/drain electrode.Figure 12 to processing method shown in Figure 15 can be in order to replace the Fig. 1 to Fig. 4 among first embodiment, then identical as for its subsequent step with embodiment one.
In Figure 12, the same with first embodiment, on silicon substrate 1, form a sacrificial oxide layer 10.Sacrificial oxide layer 10 effect in the present embodiment also is used for protecting the gate location of MOS assembly to be formed on the silicon substrate 1, the unlikely pollution that is subjected to follow-up manufacturing, and its thickness forms and then can adopt CVD or other depositional mode to form greatly about about hundreds of .Then then be the grid light shield that utilizes in making, on sacrificial oxide layer 10, define zone, photoresist layer 98 as shown in Figure 12 corresponding to grid.But different with first embodiment herein is that the width that this moment, photoresist layer 98 was defined is L ', that is the length after adding set interval on the grid light shield.As for other processing, then identical with embodiment one those shown.
With reference to Figure 13, utilize photoresist layer 98 as etching mask, sacrificial oxide layer 10 can be etched into grid cover curtain 10a, cover the top of grid in the MOS assembly to be formed.Then, above grid cover curtain 10a and silicon substrate 1, deposit a polysilicon layer 12.The character of this polysilicon layer 12 is identical with situation among the embodiment one, repeats no more herein.
Next step is then different with embodiment one.With reference to Figure 14, then then be utilize chemical-mechanical polishing (chemically-mechanical polishing, CMP) to the polysilicon layer in the present embodiment 12 with and grid cover curtain 10a carry out planarization.As shown in figure 14, the upper portion branch at grid cover curtain 10a is removed formation grid cover curtain 10b; And polysilicon layer 12 also is removed with peripheral part above grid cover curtain 10a, forms bed hedgehopping compound crystal silicon layer 12a.In this step, the effect of grid cover curtain 10a is similar to a padding, so as to being separated out both allocations of MOS assembly area of grid.
At last,, can utilize B.O.E solution or hydrofluoric acid etc. equally, remove the grid cover curtain 10b stay on the area of grid, source/drain region that so just can bed hedgehopping MOS assembly with reference to Figure 15.
Be used for the method for bed hedgehopping source/drain region in the present embodiment, can obtain the every advantage described in embodiment one equally.In addition, utilize CMP to reduce the manufacturing step of one optical treatment in the present embodiment than embodiment one.But owing to all be to adopt the grid light shield to handle among first embodiment and second embodiment, therefore actual light shield quantity does not change.
Embodiment three
Present embodiment and embodiment two are similar, all are the processing methods at bed hedgehopping source/drain region, propose another kind of implementation step.In the present embodiment, mainly be to utilize thermal oxidation method (thermal oxidation) to come the polysilicon layer in definition source/drain electrode.Figure 16 to Figure 18 represents in the present embodiment the treatment step in order to bed hedgehopping source/drain region.
As shown in figure 16, at first on silicon substrate 1, form polysilicon layer 60 and dielectric substance layer 62 (being silicon nitride in the present embodiment) in regular turn.Polysilicon layer 60 promptly is to be used for the material layer of bed hedgehopping source/drain region.Then, utilize grid light shield and light etching process, on dielectric substance layer 62, define the zone of pre-defined gate, photoresist layer 97 as shown in figure 16.In this light etching process treatment step, be on the grid light shield, to add set interval equally, to prevent occurring short circuit between electrode.
Then, utilize photoresist layer 97, remove the dielectric substance layer 62 of part in the mode of dry ecthing as etching mask.At this moment, be positioned at the part of area of grid in the polysilicon layer 60, promptly can come out.60 of the polysilicon layers that exposes are to handle (passing through oxygen) by a high-temperature thermal oxidation, and the reaction back produces thermal oxide 64, as shown in figure 17.At the same time, because the polysilicon layer 60 of part is oxidized, and not oxidized polysilicon layer 60 promptly can be used for the source/drain region of bed hedgehopping MOS assembly.
At last, can utilize hot phosphoric acid (H
3PO
4) remove the dielectric substance layer 62 of silicon nitride composition, with B.O.E solution or hydrofluoric acid etc., remove formed thermal oxide 64 in the above-mentioned reaction again, promptly form structure as shown in figure 18.This embodiment also can reach the purpose that the present invention desires to reach.
In the above embodiments one, two and three, enumerate respectively can just first bed hedgehopping source/drain electrode before assembly forms method.Must be noted that the silicon of substrate and being used for the polysilicon of bed hedgehopping source/drain region is to belong to of a sort material, therefore can't be directly defines position on source/drain region in etched mode.Therefore in the above description, embodiment one and embodiment two utilize sacrificial oxide layer to come remote definition, and embodiment three removes unnecessary polysilicon segment with thermal oxidation method.Yet implementing the present invention is not the described method of the foregoing description that only is limited to, any other processing method can be before assembly forms bed hedgehopping source/drain region, all can reach purpose of the present invention.
Manufacturing method of semiconductor module of the present invention, be applicable to the MOS assembly that deep-submicron (deepsubmicron) manufacturing process is made, the MOS assembly of manufacturing has the source electrode and the drain electrode of bed hedgehopping (elevated), can be at follow-up automatic aligning metal silication manufacture method (self-aligned silicidization, salicide) in, utilize the source electrode and the drain portion of bed hedgehopping to assign to carry out the metal silication reaction, avoid destroying utmost point shallow junction (ultra-shallowjunction) structure, improve the qualification rate that manufactures a product.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly know art technology person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking accompanying Claim and being as the criterion in conjunction with specification and accompanying drawing.
Claims (24)
1. the assembly manufacture method of a bed hedgehopping source/drain region is characterized in that: comprise the following steps:
If a bed hedgehopping uses silicon material layer on a substrate, and place the source/drain region of semiconductor subassembly to be formed;
On this bed hedgehopping this substrate, establish a gate dielectric layer with silicon material layer and exposure;
On this gate dielectric layer, establish a grid electrode layer;
This grid electrode layer of etching forms a grid structure on the gate regions of semiconductor subassembly to be formed;
This bed hedgehopping with silicon material layer and this substrate, is carried out light dope cloth and plants;
In the side of this grid structure, establish sidewall spacers; And
This bed hedgehopping with silicon material layer and this substrate, is carried out heavy doping cloth and plants.
2. the assembly manufacture method of bed hedgehopping as claimed in claim 1 source/drain region is characterized in that: wherein this bed hedgehopping silicon material layer is constituted by polysilicon, and its thickness is determined by the golden layer material amount and the reaction condition that use in the follow-up gold layer silication manufacturing.
3. the assembly manufacture method of bed hedgehopping as claimed in claim 1 source/drain region is characterized in that: wherein establish this bed hedgehopping and more comprise the following steps: with the step of silicon material layer
If one sacrifices dielectric substance layer on this substrate;
Utilize light etching process, this sacrifice dielectric substance layer of etching is a gate mask, with the gate regions that covers semiconductor subassembly to be formed;
On this grid cover mask and this substrate, establish a silicon material layer;
Remove top and peripheral part that this silicon material layer places this grid, use silicon material layer in source/drain region in order to form this bed hedgehopping; And
Remove this gate mask.
4. the assembly manufacture method of bed hedgehopping as claimed in claim 3 source/drain region is characterized in that: wherein removing in the step of this silicon material layer partly, is to utilize the grid light shield to finish for the mode of mask.
5. the assembly manufacture method of bed hedgehopping as claimed in claim 3 source/drain region is characterized in that: wherein removing in the step of this silicon material layer partly, is to utilize the chemical-mechanical polishing mode to reach.
6. the assembly manufacture method of bed hedgehopping as claimed in claim 3 source/drain region is characterized in that: wherein this silicon material layer is constituted by polysilicon, and its thickness is determined by the golden layer material amount and the reaction condition that use in the follow-up gold layer silicification technics.
7. the assembly manufacture method of bed hedgehopping as claimed in claim 1 source/drain region is characterized in that: wherein establish this bed hedgehopping and more comprise the following steps: with the step of silicon material layer
If a silicon material layer is on this substrate;
If a dielectric substance layer is on this silicon material layer;
According to a grid light shield and use photoetch, this dielectric substance layer of etching is in the part of the gate regions of semiconductor subassembly to be formed, so as to exposing this silicon material layer;
Exposed portions in this silicon material layer of thermal oxidation forms a thermal oxide layer; And
Remove the nubbin of this thermal oxide layer and this dielectric substance layer.
8. the assembly manufacture method of bed hedgehopping as claimed in claim 7 source/drain region is characterized in that: wherein this bed hedgehopping silicon material layer is constituted by polysilicon, and its thickness is determined by the golden layer material amount and the reaction condition that use in the follow-up gold layer silicification technics.
9. the assembly manufacture method of bed hedgehopping as claimed in claim 1 source/drain region is characterized in that: wherein this gate dielectric layer with the part on the silicon material layer, is to remove in the lump in the step that forms this grid structure in this bed hedgehopping.
10. the assembly manufacture method of bed hedgehopping as claimed in claim 1 source/drain region is characterized in that: wherein this gate dielectric layer with the part on the silicon material layer, is to remove in the lump in the step that forms this sidewall spacers in this bed hedgehopping.
11. the assembly manufacture method of a bed hedgehopping source/drain region is characterized in that: drain electrode comprises the following steps:
If a bed hedgehopping uses silicon material layer on a substrate, and place the source/drain region of semiconductor subassembly to be formed;
On the gate regions of semiconductor subassembly to be formed, establish a grid structure of this semiconductor subassembly, this bed hedgehopping is an isolation with the electrode in silicon material layer and this grid structure; And
Cloth is planted this bed hedgehopping and is used silicon material layer and this substrate in the source/drain region of semiconductor subassembly to be formed, to form the source/drain electrode of this semiconductor subassembly;
Whereby, this bed hedgehopping in follow-up gold layer silication made, can form corresponding automatically gold layer silicide area with silicon material layer in order to react with a metal material layer in the source/drain electrode of this semiconductor subassembly.
12. the assembly manufacture method of bed hedgehopping as claimed in claim 11 source/drain region, it is characterized in that: wherein this bed hedgehopping silicon material layer is constituted by polysilicon, and its thickness is determined by the golden layer material amount and the reaction condition that use in the follow-up gold layer silicification technics.
13. the assembly manufacture method of bed hedgehopping as claimed in claim 11 source/drain region is characterized in that: wherein establish this bed hedgehopping and more comprise the following steps: with the step of silicon material layer
If one sacrifices dielectric substance layer on this substrate;
Utilize light etching process, this sacrifice dielectric substance layer of etching is a gate mask, with the gate regions that covers semiconductor subassembly to be formed;
If a silicon material layer is on this gate mask and this substrate;
Remove top and peripheral part that this silicon material layer places this gate mask, use silicon material layer in source/drain region in order to form this bed hedgehopping; And
Remove this gate mask.
14. the assembly manufacture method of bed hedgehopping as claimed in claim 13 source/drain region is characterized in that: wherein removing in the step of this silicon material layer partly, is to utilize the grid light shield to finish for the mode of mask.
15. the assembly manufacture method of bed hedgehopping as claimed in claim 13 source/drain region is characterized in that: wherein removing in the step of this silicon material layer partly, is to utilize the chemical-mechanical polishing mode to reach.
16. the assembly manufacture method of bed hedgehopping as claimed in claim 13 source/drain region is characterized in that: wherein this silicon material layer is constituted by polysilicon, and its thickness is determined by the golden layer material amount and the reaction condition that use in the follow-up gold layer silication manufacturing.
The assembly manufacture method of 17 bed hedgehopping as claimed in claim 11 source/drain regions is characterized in that: wherein establish this bed hedgehopping and also comprise the following steps: with the step of silicon material layer
If a silicon material layer is on this substrate;
If a dielectric substance layer is on this silicon material layer;
According to a grid light shield and use optical etching, this dielectric substance layer of etching is in the part of the gate regions of semiconductor subassembly to be formed, so as to exposing this silicon material layer;
Exposed portions in this silicon material layer of thermal oxidation forms a thermal oxide layer; And
Remove the nubbin of this thermal oxide layer and this dielectric substance layer.
18. the assembly manufacture method of bed hedgehopping as claimed in claim 17 source/drain region, it is characterized in that: wherein this bed hedgehopping silicon material layer is constituted by polysilicon, and its thickness is determined by the golden layer material amount and the reaction condition that use in the follow-up gold layer silication manufacturing.
19. an assembly manufacture method is characterized in that: comprise the following steps:
If a bed hedgehopping uses silicon material layer on a substrate, and place the source/drain region of semiconductor subassembly to be formed;
On the gate regions of semiconductor subassembly to be formed, establish a grid structure of this semiconductor subassembly, this bed hedgehopping is an isolation with the electrode in silicon material layer and this grid structure;
Cloth is planted this bed hedgehopping and is used silicon material layer and this substrate in the source/drain region of semiconductor subassembly to be formed, to form the source/drain electrode of this semiconductor subassembly;
In this grid structure and this source/drain electrode of this semiconductor subassembly, establish a metal level; And
This bed hedgehopping silicon material layer in the source/drain electrode of this metal level of thermal response and this semiconductor subassembly, so as in this source/drain electrode forms and to aim at metal silicide automatically.
20. assembly manufacture method as claimed in claim 19 is characterized in that: wherein this bed hedgehopping silicon material layer is constituted by polysilicon, and its thickness is determined by the golden layer material amount and the reaction condition that use in the follow-up gold layer silication manufacturing.
21. assembly manufacture method as claimed in claim 19 is characterized in that: wherein establish this bed hedgehopping and more comprise the following steps: with the step of silicon material layer
If one sacrifices dielectric substance layer on this substrate;
Utilize optical etching technology, this sacrifice dielectric substance layer of etching is a gate mask, with the gate regions that covers semiconductor subassembly to be formed;
If a silicon material layer is on this gate mask and this substrate;
Remove top and peripheral part that this silicon material layer places this gate mask, use silicon material layer in source/drain region in order to form this bed hedgehopping; And
Remove this gate mask.
22. assembly manufacture method as claimed in claim 21 is characterized in that: wherein removing in the step of this silicon material layer partly, is to utilize the grid light shield to reach for the mode of mask.
23. assembly manufacture method as claimed in claim 21 is characterized in that: wherein removing in the step of this silicon material layer partly, is to utilize the chemical-mechanical polishing mode to reach.
24. assembly manufacture method as claimed in claim 19 is characterized in that: wherein establish this bed hedgehopping and also comprise the following steps: with the step of silicon material layer
If a silicon material layer is on this substrate;
If a dielectric substance layer is on this silicon material layer;
According to a grid light shield and use optical etching, this dielectric substance layer of etching is in the part of the gate regions of semiconductor subassembly to be formed, so as to exposing this silicon material layer;
Exposed portions in this silicon material layer of thermal oxidation forms a thermal oxide layer; And the nubbin of removing this thermal oxide layer and this dielectric substance layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110417 CN1238888C (en) | 2001-04-03 | 2001-04-03 | Method for producing semiconductor module with raised source/drain area |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01110417 CN1238888C (en) | 2001-04-03 | 2001-04-03 | Method for producing semiconductor module with raised source/drain area |
Publications (2)
| Publication Number | Publication Date |
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| CN1378253A true CN1378253A (en) | 2002-11-06 |
| CN1238888C CN1238888C (en) | 2006-01-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01110417 Expired - Lifetime CN1238888C (en) | 2001-04-03 | 2001-04-03 | Method for producing semiconductor module with raised source/drain area |
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| CN (1) | CN1238888C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104779326A (en) * | 2015-04-20 | 2015-07-15 | 西安中为光电科技有限公司 | Method for recovering GaN epitaxial waste wafer |
| CN109585301A (en) * | 2014-10-22 | 2019-04-05 | 意法半导体公司 | For including the technique with the production of integrated circuits of liner silicide of low contact resistance |
-
2001
- 2001-04-03 CN CN 01110417 patent/CN1238888C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109585301A (en) * | 2014-10-22 | 2019-04-05 | 意法半导体公司 | For including the technique with the production of integrated circuits of liner silicide of low contact resistance |
| CN109585301B (en) * | 2014-10-22 | 2022-01-04 | 意法半导体公司 | Integrated circuit with low contact resistance liner silicide and manufacturing method thereof |
| CN104779326A (en) * | 2015-04-20 | 2015-07-15 | 西安中为光电科技有限公司 | Method for recovering GaN epitaxial waste wafer |
| CN104779326B (en) * | 2015-04-20 | 2018-05-01 | 西安中为光电科技有限公司 | A kind of method of GaN epitaxy waste paper recycling |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1238888C (en) | 2006-01-25 |
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