CN1377072A - Process for preparing capacitor on bipolar and CMOS compatible device and its device - Google Patents
Process for preparing capacitor on bipolar and CMOS compatible device and its device Download PDFInfo
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- CN1377072A CN1377072A CN 01110106 CN01110106A CN1377072A CN 1377072 A CN1377072 A CN 1377072A CN 01110106 CN01110106 CN 01110106 CN 01110106 A CN01110106 A CN 01110106A CN 1377072 A CN1377072 A CN 1377072A
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Abstract
The invention relates to a production method and device for forming capacitors at the same time of BiCMOS assembly parts formed by using a shared producing process. Thus, additional producting procedures can be eliminated so as to save the cost for producing capacitors. In addition, the region of ion-adulteration formed in the crystal extended layer is as a plate electrode of the capacitors in the invention so as to reduce the thickness of dielectric layer and increase value of capacitance on unit area.
Description
The invention relates to a kind of semiconductor integrated circuit, particularly about a kind of when forming the assembly of bi-CMOS (to call BiCMOS in the following text) manufacture process, form the manufacture method and the device thereof of capacitor simultaneously.
In recent years, in the design of semiconductor integrated circuit, being provided with of capacitor is increasingly important, and has become the circuit unit that can not be substituted.For example, present various capacitor arrangement has been widely applied at internal memory (memory) and Application Specific Integrated Circuit (applicationspecific integrated circuit, ASICs) aspect, as be used for the laminated type electric capacity of DRAM (Dynamic Random Access Memory) (DRAM), perhaps be used for polysilicon/polysilicon electrode plate capacitance structure of hybrid logic/analog circuit (mix-logic/analog circuit).
At this, please referring to Fig. 1, shown in be polysilicon/polysilicon electrode plate capacitance structure for general traditional hybrid logic/analog circuit (mix-logic/analog circuit); According to the 1st figure, it is an example with the BiCMOS assembly, is on the silicon substrate 10 of P type, utilizes most field oxide (field oxide) FOX to isolate the active area of assembly; And utilize traditional transistor fabrication process, be formed with the CMOS transistor area 11 of two traps, it comprises a nmos pass transistor 110 and PMOS transistor 111, be after forming two well region N-Well, P-Well, form earlier gate electrode structure G, more respectively heavy doping go into ion with in two well regions with formation source/drain electrode S/D; Side in BiCMOS assembly district 11 then is formed with a NPN two-carrier transistor 12, and its structure comprises a collection utmost point doped region 120, a base implant district 121, a base stage contact zone 123, an emitter-base bandgap grading doped region 122, reaches an emitter-base bandgap grading contact zone 124; And traditional polysilicon-polysilicon silicon capacitor structure 13, be to form a lower electrode plate in these silicon substrate 10 surfaces in regular turn, that is polysilicon layer 131, a multi-crystal silicification metal level 132, in order to reduce resistance and to increase ohmic contact, a dielectric layer, for example a silicon dioxide layer 133 and an electric pole plate, that is polysilicon layer 134; Wherein, for making aforesaid lower electrode plate, that is polysilicon layer 131 has conductivity, and it can use the phosphorous value source of mixing, as with liquid oxygen phosphorus chloride (POCl
3) spread (diffusion), ion implantation (ion implantation) injection arsenic or phosphonium ion, or use the conductive layer of in-situ doped (in-situ doped method) formation through the doped N-type ion.
The essential structure of aforesaid capacitor is made of two conductive layer surfaces (being battery lead plate) across a megohmite insulant, and the ability of capacitor stores electric charge is determined by three kinds of physical characteristics, that is the thickness of (1) megohmite insulant; (2) surface area of battery lead plate; And the electronics or the engineering properties of (3) megohmite insulant and battery lead plate.Yet, with the polysilicon-polysilicon silicon capacitor structure of aforementioned conventional, owing to, be that ion is gone in heavy doping in the polysilicon layer of its lower electrode plate for fear of the generation that exhausts phenomenon (depletion issue); This can thicken dielectric layer (that is oxide layer) thickness of follow-up growth, thus the capacitance of per unit area reduce (because C=ε/d), and reduce capacitance, further influence the characteristic (performance) of assembly.
In addition, for the two-layer polysilicon layer of growing up, must increase extra step to finish it on process steps, this not only spends makes the required time, has more increased the cost of making.
In view of this, the object of the present invention is to provide a kind of method and device thereof that forms capacitor when forming the bi-CMOS assembly, this method and device thereof are when forming the BiCMOS assembly, utilize its manufacture process to form the manufacture method of capacitor simultaneously, it has thin dielectric medium, and does not need additionally to increase process steps and just can finish.
Another object of the present invention is to provide a kind of method and device thereof that forms capacitor when forming the bi-CMOS assembly, this method and device thereof be the device of the doped region in the crystal enlargement layer as a battery lead plate of capacitor, and it can save the higher capacitor of capacitance that forms the better and unit are of a quality under the prerequisite of manufacturing time and cost.
Purpose of the present invention can reach by following measure:
A kind of method that forms capacitor when forming the bi-CMOS assembly is applicable on the semiconductor substrate, comprises the following steps:
In this semiconductor substrate, form one first buried regions and second buried regions;
Form one deck crystal enlargement layer on this semiconductor substrate;
In this crystal enlargement layer, form one first well region, a collection utmost point doped region, one second well region respectively, reach one the 3rd well region, and this second well region and this triple-well district are mixed with the first type ion and the second type ion respectively, and this first well region and this collection utmost point doped region are to contact with this first, second buried regions respectively;
Form an oxide layer and make and all be covered in this first well region, and part be covered in this second, with the 3rd well region on;
Form a base implant district in this crystal enlargement layer between this first well region and this collection utmost point doped region;
Form a conductive layer and make and all be covered in this first well region, and part be covered in this second, third well region oxide layer, with this base implant district on;
In this base implant district, form a base stage contact zone, and respectively at the heavily doped region that forms the second type ion and the first type ion in this second and the 3rd well region; And
In this base implant district, form an emitter-base bandgap grading doped region.
A kind of device that forms capacitor when forming the bi-CMOS assembly is to be applicable on the semiconductor substrate, it is characterized in that: comprising:
One buried regions is to be arranged in this semiconductor substrate;
One crystal enlargement layer is to be positioned on this semiconductor substrate;
One two-carrier junction transistor is to be arranged in this crystal enlargement layer, and it has a collection utmost point doped region;
One CMOS transistor, it has a grid conducting layer and a grid oxic horizon respectively;
One well region is to be arranged in this crystal enlargement layer, and this well region is to do with this buried regions to contact;
One oxide layer is to be positioned at this crystal enlargement layer surface that comprises this well region; And
One conductive layer, be to be positioned on this oxide layer, this well region is that the collection utmost point doped region with the two-carrier junction transistor together forms, and this oxide layer is together to form with the transistorized grid oxic horizon of CMOS, and this conductive layer is together to form with the transistorized grid conducting layer of CMOS.
In order to reach one object of the present invention, provide the manufacture method that a kind of and BiCMOS assembly together form capacitor, be applicable on the semiconductor substrate, comprise the following steps: at first in semiconductor substrate, to form one first buried regions and second buried regions, then on this semiconductor substrate, form one deck crystal enlargement layer.Then, in this crystal enlargement layer, form three well regions and a collection utmost point doped region respectively, wherein, it is in order to form the MOS assembly in the BiCMOS assembly that two well regions are arranged, another well region is then in order to the lower electrode plate as capacitor, and this collection utmost point doped region is to contact with aforesaid buried regions respectively with the lower electrode plate of capacitor.Afterwards, form oxide layer respectively with as the gate oxide of MOS assembly and the dielectric substance layer of capacitor, and form a base implant district in collection utmost point doped region side respectively at three above-mentioned well region surfaces.Then form gate electrode and the electric pole plate of capacitor and the base stage contact zone in base implant district of polysilicon respectively in above-mentioned three well regions and surface, base implant district, and the heavily doped region that forms ion in above-mentioned gate electrode and base stage contact zone down either side is with as the source/drain electrode of MOS assembly and the contact zone of base stage, again formation one emitter-base bandgap grading doped region in this base implant district.
It should be noted at this, the advantage that the present invention has compared to existing technology shows as owing to dielectric layer of the present invention is directly to carry out oxidation on this crystal enlargement layer surface to produce, utilize adjustment well region intermediate ion to ooze assorted concentration, therefore the thickness that can control this layer dielectric layer makes it thinner, and can increase the capacitance of capacitor.In addition, the present invention is the capacitor that forms simultaneously for when making the BiCMOS assembly, and it need not increase any process steps and just can reach identical even the capacitor of good merchantable brand matter more, saves time.
And as in the above-mentioned assembly, if will do electrical the contact with other assembly, then need the following step: form an insulating barrier in the crystal enlargement layer surface that comprises all component, as bpsg layer, then in this insulating barrier, form most openings to expose this polysilicon layer, source/drain electrode, ion heavily doped region, and surface, contact zone.In above-mentioned opening, form conductive plugs again, to do electrical the contact with other assembly.
In order to reach another object of the present invention, provide and a kind ofly utilize its manufacture process to form the device of capacitor simultaneously when forming the BiCMOS assembly, it is with the battery lead plate of the doped region in the crystal enlargement layer as capacitor, comprise: the semiconductor substrate, and wherein have a buried layer.And a crystal enlargement layer, be to be positioned on this semiconductor substrate.In this crystal enlargement layer, then be provided with a well region, and do electrical the contact, and this device is promptly in order to form the lower electrode plate of capacitor with buried layer.In addition, still comprising an oxide layer, is to be positioned on this well region, with the dielectric medium as capacitor, and then forms a polysilicon layer in order to the electric pole plate as capacitor above this oxide layer.And a BiCMOS assembly, be to be arranged in this crystal enlargement layer.
Please note at this, advantage of the present invention can also show as the present invention and be arranged at doped region in the crystal enlargement layer as the lower electrode plate of capacitor with one, it not only reduces the formation of one deck polysilicon, and, because of its carrying out along with the BiCMOS manufacture process does not increase any process steps, also can say so and reduce Production Time and dual cost.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and in conjunction with the accompanying drawings, be described in detail below:
Brief description of drawings
Fig. 1 is the polysilicon/polysilicon electrode plate electric capacity of existing conventional hybrid formula logic/analog circuit and the section of structure of BiCMOS assembly; And
Fig. 2 A～2K demonstration utilizes its manufacture process to form the manufacturing process profile of capacitor simultaneously according to of the present invention when forming the BiCMOS assembly.
The figure number explanation
10 silicon substrates, 11 BiCMOS assemblies
110 nmos pass transistors, 111 PMOS transistors
12 NPN two-carrier junction transistors
120 collection utmost point doped regions, 121 base implant districts
122 emitter-base bandgap grading doped regions, 123 base stage contact zones
124 emitter-base bandgap grading contact zones, 13 polysilicons/polysilicon capacitor
131 polysilicon layers, 132 multi-crystal silicification metal levels
133 silicon dioxide layers, 134 polysilicon layers
20 silicon substrates
201,202,203,204 buried regions
21 crystal enlargement layers
210,211,213,214 well regions
212 collection utmost point doped regions
215 emitter-base bandgap grading doped regions, 216 base stage contact zones
217,218 sources/drain electrode 219 emitter-base bandgap grading doped regions
22a, 22b, 22c silicon dioxide layer
23a, 23b, 23c, 23d polysilicon layer
24 MOS assemblies, 25 two-carrier junction transistor assemblies
26 capacitors, 27 BiCMOS assemblies
28 bpsg layers 28a～28k opening
29a～29k conductive plugs FOX field oxide
Embodiment
At this,,, utilize its manufacture process to form the manufacture method of capacitor and the preferred embodiment of device thereof simultaneously more specifically to understand according to of the present invention when forming the BiCMOS assembly please referring to the flow process profile shown in Fig. 2 A～2K.
Please refer to Fig. 2 A, provide the semiconductor substrate, for example is silicon substrate 20, and forms one first buried regions and second buried regions in this semiconductor substrate respectively, for example, adopts energy to be about 50KeV, the about 1E15 (atoms/cm of flux density
2) arsenic ion and boron ion implement that ion injects and form a N in silicon substrate 20
+With P
+The diffusion region, with as a N type buried regions 201, N type buried regions 202, N type buried regions 203, with P type buried regions 204.
Next, form one deck crystal enlargement layer on this semiconductor substrate; At this, please refer to Fig. 2 B, be in above-mentioned buried regions 201,202,203, with 204 and silicon substrate 20 go up to form a crystal enlargement layer, for example be that (its concentration is about 10 for a lightly doped N type crystal enlargement layer 21
14～10
15Atoms/cm
3Between).
Afterwards, the step of carrying out is for forming one first well region, a collection utmost point doped region, one second well region respectively in this crystal enlargement layer, reaching one the 3rd well region, and this second well region and this triple-well district are mixed with the first type ion and the second type ion respectively, and this first well region and this collection utmost point doped region are to contact with this first, second buried regions respectively; For example, shown in Fig. 2 C, earlier respectively at doping P type ion in the crystal enlargement layer 21 of buried regions 201,204 surfaces, as the boron ion, to form P type well region 210,214; Afterwards, doped N-type ion in the crystal enlargement layer 21 of buried regions 202,203 surfaces again is as arsenic ion, to form N type well region 212,213; Wherein, N type well region 212 is in order to the collection utmost point doped region 212 as this two-carrier junction transistor assembly 25.Then, N type ion is gone in heavy doping in this P type well region 210, makes the electric property inversion of original P type well region 210 become N type well region 211, and the concentration of its dopant ion is about 10
15～10
16Atoms/cm
3Between, to make it lower electrode plate, shown in 2C figure as capacitor 26.
Next, please referring to Fig. 2 D, be to form several field oxides (field oxide) FOX in these crystal enlargement layer 21 surfaces, with usefulness as each assembly isolation in selective oxidation mode (LOCOS).Afterwards, the step that carry out is to make and all be covered in this first well region for forming an oxide layer, and part be covered in this second, with the 3rd well region on; For example, according to Fig. 2 E, form a silicon dioxide layer (not being shown among the figure) with thermal oxidation method (thermal oxidation) in these crystal enlargement layer 21 surfaces, then, utilize photo-engraving process (photolithography) and etching technique (etching), define the pattern of this oxide layer, form the layer of silicon dioxide layer with these crystal enlargement layer 21 surfaces on well region 211 and make this well region of covering (that is lower electrode plate of capacitor) 211, and form gate oxide (gate oxide) 22b and the 22c of this MOS assembly 24 respectively at the surface of well region 213 and 214 with dielectric medium 22a as this capacitor 26.Wherein, above-mentioned silicon dioxide layer 22a, 22b, and the thickness of 22c between 100～150 .
And then, be carried out at the step that forms a base implant district in this crystal enlargement layer between this first well region and this collection utmost point doped region; For example, please refer to Fig. 2 F, is the P type ion that mixes, and for example is the boron ion, the crystal enlargement layer 21 between this field oxide FOX in form a scope collect utmost point doped region 212 will little base implant district 215.
Afterwards, form a conductive layer and make and all be covered in this first well region, and part be covered in this second, third well region oxide layer, with this base implant district on; For example, please refer to Fig. 2 G, be to form a conductive layer with chemical vapour deposition technique (CVD), make this crystal enlargement layer 21 of comprehensive covering as polysilicon layer (not being shown among the figure), afterwards and with photoetching process and etch process, define the pattern of this polysilicon layer, with respectively at this silicon dioxide layer 22a (that is dielectric layer of capacitor 26), this base implant district 215, with this silicon dioxide layer 22b, the surface of 22c forms a polysilicon layer 23a, it is in order to the electric pole plate as capacitor 26, polysilicon layer 23b, in order to contact electrode as the emitter-base bandgap grading doped region of the follow-up two-carrier junction transistor assembly 25 that will form, and polysilicon layer 23c and 23d, be gate electrode as MOS assembly 24.
Next, the work that mix, that is in this base implant district, form a base stage contact zone, and respectively at the heavily doped region that forms the second type ion and the first type ion in this second and the 3rd well region; At this, please scheme referring to 2H, inject P type ion respectively, for example be the boron ion to the base implant district of contact electrode 23b down either side, with the crystal enlargement layer 21 of gate electrode 23c down either side in to form P type ion heavily doped region with as the pair of source 217 in the base stage contact zone 216 of two-carrier junction transistor assembly 25 and the MOS assembly 24; And, inject N type ion, for example be arsenic ion to the crystal enlargement layer 21 of gate electrode 23d down either side, to form N type ion heavily doped region as the pair of source/drain electrode 218 in addition in the MOS assembly 24.Injecting ion then makes it have conductivity to the electric pole plate 23a of capacitor 26, the contact electrode 23b of two-carrier junction transistor assembly 25 and the gate electrode 23c and the 23d of MOS assembly 24.Yet 22a is damaged for fear of dielectric layer, can utilize synchronous doping (in-situ doped implantation), is mixed with the electric pole plate 23a of N type ion with formation.
Then, please refer to 2I figure, is to form an emitter-base bandgap grading doped region 219 in this base implant district, so far finishes the manufacturing of a BiCMOS assembly 27 and a capacitor 26.Note that because those assemblies may be done electrical the contact with other assembly at this, therefore, must finish the step of insulation and contact (contact); At this, please, for example, on crystal enlargement layer 21, form boron-phosphorosilicate glass (BPSG) layer 28 of a planarization with the high-temperature heat flux method referring to 2J figure, with photoetching process and etch process, define most opening 28a～28k again to expose each doped region and conductive layer.Afterwards, please scheme referring to 2K, deposition (deposit) and etch-back (etchingback) conductive layer for example are polysilicon layers (indicate) and form conductive plugs 29a～29k in these openings 28a～28k, are beneficial to assembly of the present invention and do electrical the contact with other assembly.
Shown in 2I figure, it is structure for BiCMOS assembly of the present invention and capacitor, be to be applicable to a silicon substrate 20, it comprises N type buried regions 201～203 and P type buried regions 204, above this silicon substrate 20, then form a crystal enlargement layer 21, and in it, has a N type well region 211, be to link to each other with this N type buried regions 201, it is in order to form the lower electrode plate of capacitor 26, then form a dielectric substance layer 22a on these crystal enlargement layer 21 surfaces, its material is to be silicon dioxide, and is to form a conductive layer in order to the electric pole plate 23a as this capacitor 26 on aforesaid dielectric substance layer 22a, and its material is to be polysilicon.
Side at this capacitor 26 is a BiCMOS transistor 27, and it comprises a two-carrier junction transistor 25 and a CMOS transistor 24; Wherein, this two-carrier junction transistor 27 is to form a collection utmost point doped region 212 in crystal enlargement layer 21, be to link to each other with buried layer 202, an and base implant district 215, and in base implant district 215, more comprise an emitter-base bandgap grading doped region 219 and a base stage contact zone 216, and in crystal enlargement layer 21 surface that comprises this emitter-base bandgap grading doped region 219 and form a conductive layer, its material be for polysilicon with contact electrode 23b as emitter-base bandgap grading doped region 219.
In addition, still comprise a CMOS transistor 24, it has N type well region 213 and P type well region 214, and links to each other with buried regions 203,204 respectively.In this N type well region 213 and P type well region 214, form a pair of source/drain region that is separated by each other 217 and 218 respectively, 217 crystal enlargement layer 21 surfaces are a grid oxic horizon 22b and a grid conducting layer 23c in regular turn in this source/drain region, and 218 crystal enlargement layer 21 surfaces are a grid oxic horizon 22c and a grid conducting layer 23d in regular turn in this source/drain region.
In addition,, then please refer to 2K figure, on aforementioned components, more comprise an insulating barrier, for example be bpsg layer 28, and have conductive plugs 29a～29k therebetween, so that do electrical the contact with other assembly if above-mentioned assembly is desired to do electrical the contact with other assembly.And, doing short circuit when contacting for fear of the lower electrode plate of capacitor 26 and electric pole plate, so the contact of lower electrode plate is on the direction of vertical paper, so be not shown among the figure.
Should be specifically noted that 3 points at this, that is: (1) has lacked a polysilicon electrode plate for the more existing polysilicon of capacitor constructions of the present invention/polysilicon double electrode plate structure, has therefore reduced and has made required cost; (2) because dielectric layer is the silicon dioxide that directly forms for by crystal enlargement layer 21 surfaces, and the doped region doping content of dielectric layer below is lower, therefore formed dielectric medium thickness can be thinner, with present embodiment, its formed silicon dioxide layer can be thinned to 100 , the dielectric layer of more existing 400 is little about 4 times, thereby increase the value of unit-area capacitance device; (3) making of capacitor of the present invention is to agree to the manufacturing process of general BiCMOS assembly and for it, additionally do not increase manufacturing step fully, cooperates the design of aforesaid single polysilicon films, is that it is that multiple cost descends.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly know those skilled in the art; without departing from the spirit and scope of the present invention; when can doing to change and retouching, so protection scope of the present invention is when looking claim and being as the criterion in conjunction with defining of specification and accompanying drawing.
Claims (16)
1. a method that forms capacitor when forming the bi-CMOS assembly is applicable on the semiconductor substrate, it is characterized in that: comprise the following steps:
In this semiconductor substrate, form one first buried regions and second buried regions;
Form one deck crystal enlargement layer on this semiconductor substrate;
In this crystal enlargement layer, form one first well region, a collection utmost point doped region, one second well region respectively, reach one the 3rd well region, and this second well region and this triple-well district are mixed with the first type ion and the second type ion respectively, and this first well region and this collection utmost point doped region are to contact with this first, second buried regions respectively;
Form an oxide layer and make and all be covered in this first well region, and part be covered in this second, with the 3rd well region on;
Form a base implant district in this crystal enlargement layer between this first well region and this collection utmost point doped region;
Form a conductive layer and make and all be covered in this first well region, and part be covered in this second, third well region oxide layer, with this base implant district on;
In this base implant district, form a base stage contact zone, and respectively at the heavily doped region that forms the second type ion and the first type ion in this second and the 3rd well region; And
In this base implant district, form an emitter-base bandgap grading doped region.
2. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 1, it is characterized in that: wherein, more comprise the following steps:
Forming an insulating barrier makes and is covered on this crystal enlargement layer;
In this insulating barrier, form most openings with expose this conductive layer, this ion heavily doped region, with this collection utmost point surface of adulteration area; And
In these openings, form conductive plugs.
3. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 1, it is characterized in that: wherein, this semiconductor substrate is to be silicon substrate.
4. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 1, it is characterized in that: wherein, this first well region is in order to forming the bottom crown of this capacitor, and the concentration of this first well region dopant ion is about 10
15～10
16Atoms/cm
3Between.
5. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 1, it is characterized in that: wherein, this second and the 3rd well region is in order to form a CMOS transistor.
6. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 1, it is characterized in that: wherein, the oxide layer that covers this first well region is the dielectric substance layer as this capacitor, and its material is to be silicon dioxide layer, and thickness is between 50～500 .
7. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 1, it is characterized in that: wherein, the oxide layer that part covers this second, third well region is as transistorized gate oxide.
8. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 1, it is characterized in that: wherein, cover conductive layer on the oxide layer of this first well region and be the top crown as capacitor, its material is to be polysilicon layer, and thickness is between 1000～5000 .
9. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 2, it is characterized in that: wherein, this insulating barrier is to be the boron-phosphorosilicate glass layer, and its thickness is between 5000～8000 .
10. form the method for capacitor during formation bi-CMOS assembly as claimed in claim 2, it is characterized in that: wherein, the material of this conductive plugs is to be polysilicon.
11. a device that forms capacitor when forming the bi-CMOS assembly is to be applicable on the semiconductor substrate, it is characterized in that: comprising:
One buried regions is to be arranged in this semiconductor substrate;
One crystal enlargement layer is to be positioned on this semiconductor substrate;
One two-carrier junction transistor is to be arranged in this crystal enlargement layer, and it has a collection utmost point doped region;
One CMOS transistor, it has a grid conducting layer and a grid oxic horizon respectively;
One well region is to be arranged in this crystal enlargement layer, and this well region is to do with this buried regions to contact;
One oxide layer is to be positioned at this crystal enlargement layer surface that comprises this well region; And
One conductive layer, be to be positioned on this oxide layer, this well region is that the collection utmost point doped region with the two-carrier junction transistor together forms, and this oxide layer is together to form with the transistorized grid oxic horizon of CMOS, and this conductive layer is together to form with the transistorized grid conducting layer of CMOS.
12. form the device of capacitor during formation bi-CMOS assembly as claimed in claim 11, it is characterized in that: wherein, surface at above-mentioned crystal enlargement layer more comprises an insulating barrier, and has most conductive plugs in this insulating barrier to do electrical the contact with other assembly.
13. form the device of capacitor during formation bi-CMOS assembly as claimed in claim 11, it is characterized in that: wherein, this semiconductor substrate is to be silicon substrate.
14. form the device of capacitor during formation bi-CMOS assembly as claimed in claim 11, it is characterized in that: wherein, this well region is in order to forming the lower electrode plate of this capacitor, and the concentration of its dopant ion is 10
15～10
19Atoms/cm
3Between.
15. form the device of capacitor during formation bi-CMOS assembly as claimed in claim 11, it is characterized in that: wherein, the oxide layer that covers this well region is the dielectric medium as this capacitor, and its material is to be silicon dioxide layer, and its thickness is between 50～500 .
16. form the device of capacitor during formation bi-CMOS assembly as claimed in claim 11, it is characterized in that: wherein, cover conductive layer on the oxide layer of this well region and be the top crown as capacitor, its material is to be polysilicon layer, and thickness is between 1000～5000 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011101067A CN1157776C (en) | 2001-03-23 | 2001-03-23 | Process for preparing capacitor on bipolar and CMOS compatible device and its device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011101067A CN1157776C (en) | 2001-03-23 | 2001-03-23 | Process for preparing capacitor on bipolar and CMOS compatible device and its device |
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| CN1377072A true CN1377072A (en) | 2002-10-30 |
| CN1157776C CN1157776C (en) | 2004-07-14 |
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|---|---|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956196B (en) * | 2005-10-28 | 2011-06-29 | 东部电子股份有限公司 | biCMOS device and method of manufacturing a biCMOS device |
| CN112331653A (en) * | 2020-10-29 | 2021-02-05 | 长江存储科技有限责任公司 | Semiconductor device, three-dimensional memory and semiconductor device manufacturing method |
-
2001
- 2001-03-23 CN CNB011101067A patent/CN1157776C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956196B (en) * | 2005-10-28 | 2011-06-29 | 东部电子股份有限公司 | biCMOS device and method of manufacturing a biCMOS device |
| CN112331653A (en) * | 2020-10-29 | 2021-02-05 | 长江存储科技有限责任公司 | Semiconductor device, three-dimensional memory and semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1157776C (en) | 2004-07-14 |
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