CN1377039A - Improved SRAM and its method - Google Patents

Abstract

The invention relates to a configuration of an array of the the new type static random access memory (SRAM) and a simple method for measuring a stand-by current. Based on the variation value of the measured stand-by current of SRAM, the actual resistance value of polysilicon load in SRAM array can be calculated from the said current. It is helpful for developer to understand the reason, which causes the high stand-by current, is from the polysilicon load or the electric leakage of the SRAM assembly part itself.

Description

A kind of improved static random access memory and method thereof

The present invention is relevant for a kind of static random access memory (Static Random AccessMemory; Be called for short SRAM), by special circuit setting and method of testing, can use and measure electric current and then draw the resistance that storage unit is carried.

Fig. 1 shows the circuit diagram of tradition by the SRAM storage unit (memorycell) that four NMOS transistors constituted.Transistor M1, M2 and polysilicon load (polyload) constitute bolt-lock unit (latch), and end points X and Y then can produce the different logical signal of logic level.Character line W is then as addressing usefulness, the on off state of oxide-semiconductor control transistors M3 and M4; Bit line B and bit line B then read or write the logical value of end points X and Y respectively.

For traditional SRAM storage unit, the resistance of its polysilicon load is chip (chip) standby current (I _Sbc) big or small main determining factor (dominant factor).Because technology is constantly dwindled (scale down), the length of SRAM memory cell size and polysilicon load is also more and more little.Therefore, the electric leakage of SRAM assembly (leakage) and polysilicon load resistance, both all seriously influence SRAM standby current (I _Sbc) size.Recently since integrated circuit all requirement can meet low-consumption of power (low power dissipation) requirement, so for standby current (I _Sbc) restriction also more is tending towards strict.But, in order to reduce standby current (I _Sbc), and the resistance of polysilicon load is improved, tend to cause the usefulness of storage unit to perform poor and derive stability problem.

In order to overcome the deficiencies in the prior art part, the present invention's purpose is to provide a kind of improved static state with the access memory on opportunity, makes improvements via special line design and at traditional SRAM array, to measure SRAM standby current (I _Sbc); Permeametry gained standby current (I _Sbc) changing value, the anti-resistance that pushes away polysilicon load in the storage unit in fact is to provide design, to produce and improve reference.

Be applicable to standby current (I of the present invention _Sbc) the novel SRAM of measuring method, comprise the following units at least.

One primary power device; 2m switchgear (S ₁～S _2m); And, 2m group supply path (P ₁～P _2m).Above-mentioned 2m switchgear (S ₁～S _2m) be coupled to above-mentioned 2m group supply path (P one to one ₁～P _2m) and above-mentioned primary power device between.

M memory block (B ₁～B _m), each memory block (B _j, 1≤j≤m) disposes two groups of this supply path (P respectively _2j-1, P _2j).Each memory region (B _j) comprise n storage unit (C _{J_1}～C _{J_n}); Each storage unit (C _{J_k}, 1≤k≤n) is by four transistors, and two groups of (L that carry on the back or on the head _{J_k_1}, L _{J_k_2}) constitute and these two groups of load (L _{J_k_1}, L _{J_k_2}) be coupled to corresponding two groups of these supply paths (P _2j-1, P _2j).

The chip enable switching device shifter in order to when memory chip enabling signal (CE) is in first current potential, makes all these switchgears (S ₁～S _2m) conducting, provide electric power to deposit block in order to do making this primary power device be seen through these supply paths to these, allow this static random access memory carry out normal running.

Device for selection controlling, when this memory chip enabling signal (CE) is in second current potential, that is this static random access memory is when being in holding state, and the needs that can test are from these switchgears (S ₁～S _2m) in, select pair of switches device (S at least _2j-1, S _2j) giving conducting, correlated current is measured and test to carry out.

Measure standby current so that the anti-resistance purpose that pushes away in order to reach, the present invention also proposes a kind ofly to utilize current measurement to draw static random access memory load resistance method, and this method comprises the steps.

At first, allow static random access memory enter standby mode (for example, making CE be in first potential state).At this moment, these switchgears (S ₁～S _2m) not conducting, this primary power device can't see through these supply paths (P ₁～P _2m) supply capability gives these memory regions (B ₁～B _m).

Then, measure this static random access memory standby current, and obtain the first electric current (I ₁).

Then, see through above-mentioned device for selection controlling, optionally allow these switchgears (S ₁～S _2m) in Q to the switchgear conducting, allow Q these memory blocks can be by this by this primary power unit feeding electric power.

Measure this static random access memory standby current again, use obtaining the second electric current (I ₂).

With this second electric current (I ₂) and the first electric current (I ₁) difference is again divided by m-Q, deposits the electric current that all storage unit circulated in the block and draw arbitrary Q $(\mathrm{\ΔI}=\frac{I_1-I_2}{m-Q}).$

Then, with electric current Δ I divided by the number of depositing storage unit in the block (n), in the hope of the 3rd electric current (Δ I/n) that each storage unit circulated.At last, provide current potential (V with this primary power device _Cc) divided by the 3rd electric current, and draw the resistance of each load in each storage unit $(\frac{V_{\mathrm{cc}}}{\mathrm{\ΔI}}\×n).$

From the above, the present invention proposes novel SRAM framework, it is characterized by can be by the running of newly establishing device for selection controlling under holding state, cooperate the present invention to propose the standby current measuring method, control above-mentioned switchgear conducting state, so that distinctly measure standby current changing value (i.e. second electric current and the first difference between currents value), and then reach polysilicon load resistance among the anti-SRAM of pushing away, reach the present invention's purpose by aforesaid way.

Brief Description Of Drawings:

For the present invention's above-mentioned purpose, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are described below in detail:

Fig. 1 shows that tradition is constituted SRAM memory circuit figure by four NMOS transistors;

Fig. 2 shows according to the novel SRAM array architecture of the present invention figure;

Fig. 3 shows that SRAM chips of the present invention starts the enforcement illustration of switching device shifter and device for selection controlling.The figure number explanation:

M1-M4～transistor; Latch, latch ₁-latch _n～bolt-lock unit; B, B～bit line; W～character line; X-Y～logical signal end; S ₁-S ₈～switchgear; P ₁-P ₈～supply path; B ₁-B ₄～memory block; C _{1_1}-C _{1_n}～storage unit; CE～memory chip enabling signal; I ₁～the first electric current; I ₂～the second electric current; Δ I/n～the 3rd electric current; WL ₁-WL _n～character line; BL-BL～bit line; 20～primary power device; 30～chip enable switching device shifter; 30a, 30c～reverser; 30b～dropping equipment 30b; 32～device for selection controlling; 32a～addition code translator; 32b～logic selecting arrangement; Z ₁-Z ₄～selection signal; M _Normal～normal mode signal; M _Test～standby mode signal; Address signal X ₁, X ₂～selecting address signal; Y ₁-Y ₄The output of～addition code translator; V _Cc～primary power device voltage.

Embodiment

Fig. 2 shows according to the novel SRAM array architecture of the present invention figure; For convenience of explanation; Only show to have 4 memory block SRAM array architecture (that is m=4) among the figure, only make detailed icons at first memory block in addition, the inner structure of other memory block all can get with reference to the structure of first memory block.

With reference to Fig. 2, be applicable to standby current (I of the present invention _Sbc) the novel SRAM of measuring method, comprise the following units at least: a primary power device 20, so that voltage V to be provided _Cc8 switchgear (S ₁～S ₈); 8 groups of supply path (P ₁～P ₈); First to fourth memory block (B ₁～B ₄); 2 code translators see through character line (WL ₁～WL _n) carry out addressing, will carrying out read-write memory cell by bit line (BL, BL); Chip enable switching device shifter (Fig. 3); And, device for selection controlling (Fig. 3).

Above-mentioned 8 switchgear (S ₁～S ₈); In this embodiment, each switchgear (S ₁～S ₈) be the PMOS transistor.In addition, above-mentioned 8 switchgear (S ₁～S ₈) be coupled to above-mentioned 8 groups of supply path (P one to one ₁～P ₈) and above-mentioned primary power device 20 between.

Above-mentioned supply path P ₁, P ₂The first memory block B is given in configuration ₁, above-mentioned supply path P ₃, P ₄The second memory block B is given in configuration ₂, above-mentioned supply path P ₅, P ₆The 3rd memory block B is given in configuration ₃, above-mentioned supply path P ₇, P ₈The 4th memory block B is given in configuration ₄

Each above-mentioned j memory block (B _jJ=1～4) include n storage unit (C _{J_1}～C _{J_n}).Storage unit (C in each storage unit block _{1_k}, C _{2_k}, C _{3_k}, C _{4_k}, 1≤k≤n) is by four NMOS transistors, and two groups of polysilicons (L that carries on the back or on the head _{J_k_1}, L _{J_k_2}) constitute, SRAM memory cell architecture as shown in Figure 1, wherein 2 nmos pass transistors and above-mentioned polysilicon load form bolt-lock unit (latch ₁～latch _n); In addition, two groups of load (L in each storage unit _{J_k_1}, L _{J_k_2}) be coupled to the corresponding two groups of supply path (P of place memory block _2j-1, P _2j).

Fig. 3 shows that SRAM chips of the present invention starts switching device shifter 30 and device for selection controlling 32

Implement illustration.

With reference to Fig. 3, said chip starts switching device shifter 30, comprises two reverser 30a, 30c and a dropping equipment 30b; Above-mentioned device for selection controlling 32 comprises: an addition code translator 32a and a logic selecting arrangement 32b.Above-mentioned logic selecting arrangement 32b is made up of 4 rejection gates (NORgate), and it exports Z ₁, Z ₂, Z ₃, Z ₄Then be coupled to above-mentioned switchgear S respectively ₁-S ₂, S ₃-S ₄, S ₅-S ₆, and S ₇-S ₈Grid.

As memory chip enabling signal (chip enable signal; When CE) being in logic low potential " L ", above-mentioned reverser 30a output noble potential " H " normal mode signal (M _Normal), impel the SRAM periphery, and interlock circuit can carry out normal running.Under this situation, reverser 30c output signal (M _Test) then be noble potential " H ", make logic selecting arrangement 32b export Z ₁, Z ₂, Z ₃, Z ₄Be electronegative potential " L "; Therefore, make all switchgear S ₁～S ₈Conducting is so above-mentioned primary power device 20 is seen through these supply paths (P ₁～P ₈) provide electric power to these memory block (B ₁～B ₄), this SRAM is carried out normal running.

When above-mentioned memory chip enabling signal CE is in logic low potential " H ", that is this SRAM is when being in holding state or test mode, after the high potential signal voltage process dropping equipment 30b step-down of chip start signal (CE), by the signal M of reverser 30c output _TestThen become electronegative potential " L ".Therefore, under holding state, can be according to actual required, by addition code translator 32a Input Address signal X ₁, X ₂Select, allow switch device (S ₁-S ₂, S ₃-S ₄, S ₅-S ₆, S ₇-S ₈) in, select at least pair of switches device (S _2j-1, S _2j) giving conducting, correlated current is measured and test to carry out.For example, X ₁, X ₂Be logic current potential 0,0 o'clock, Y ₁～Y ₄Signal is respectively 1000, only makes Z ₁The position standard becomes electronegative potential " L ", and with switchgear (S ₁-S ₂) conducting; X ₁, X ₂Be logic current potential 0,1 o'clock, Y ₁～Y ₄Signal is respectively 0100, only makes Z ₂The position standard becomes electronegative potential " L ", and with switchgear (S ₃-S ₄) conducting; X ₁, X ₂Be logic current potential 1,0 o'clock, Y ₁～Y ₄Signal is respectively 0010, only makes Z ₃The position standard becomes electronegative potential " L ", and with switchgear (S ₅-S ₆) conducting; X ₁, X ₂Be logic current potential 1,1 o'clock, Y ₁～Y ₄Signal is respectively 0001, only makes Z ₄The position standard become electronegative potential " L ", and with switchgear (S ₇-S ₈) conducting.

According to the device for selection controlling shown in the foregoing description 32, under holding state, though only can be with pair of switches device (S ₁-S ₂, S ₃-S ₄, S ₅-S ₆, or S ₇-S ₈) give conducting, but also changing its circuit design, and make the switchgear conducting more than two pairs.

Cooperate the above-mentioned novel SRAM framework that proposes, measure standby current so that the anti-resistance purpose that pushes away for reaching, proposition method of the present invention comprises the steps.

At first, allow static random access memory enter standby mode or be called test pattern (for example, make CE be in the state of noble potential " H ", its voltage is higher than V _Cc).In this case, reverser 30c output signal M _TestThen become noble potential " H "; So, signal Z ₁～Z ₄Output is high potential signal " H ", switchgear S ₁～S ₈Can conducting, above-mentioned primary power device 20 can't see through these supply paths P ₁～P ₈Supply capability is given these memory block (B ₁～B ₄).

Then, measure above-mentioned SRAM standby current, and obtain the first electric current (I ₁).

Then, see through addition code translator 32a in the above-mentioned device for selection controlling 32, optionally allow pair of switches device (S ₁-S ₂, S ₃-S ₄, S ₅-S ₆, or S ₇-S ₈) conducting.In this embodiment, suppose above-mentioned addition code translator 32a address signal X ₁, X ₂Be respectively 0,0, so Y ₁～Y ₄Signal be respectively 1000, make Z ₁The position standard becomes electronegative potential " L ", and with switchgear (S ₁-S ₂) conducting; The first memory block B by this ₁Can be by these primary power device 20 supply capabilities.That is, the first memory block B is only arranged ₁Middle polysilicon load can obtain above-mentioned primary power device 20 voltage V _Cc

Measure above-mentioned SRAM standby current again, use obtaining the second electric current (I ₂).

With this second electric current (I ₂) and this first electric current (I ₁) difference again divided by 3, and draw the above-mentioned first memory region B ₁In all storage cell institute circulating currents $(\mathrm{\ΔI}=\frac{I_2-I_1}{3}).$

Then, with electric current Δ I divided by the first memory block B ₁In Number of Storage Units (n), in the hope of each these storage unit the 3rd electric current (Δ I/n) that circulates.Above-mentioned the 3rd electric current that is be to supply with a polysilicon load current in each storage unit by above-mentioned primary power device 20; Because in bolt-lock unit in each storage unit (2 nmos pass transistors and 2 polysilicon loads), a nmos pass transistor meeting conducting is only arranged, so electric current also only circulates in the corresponding polysilicon load.

At last, provide current potential (V with this primary power device _Cc) divided by the 3rd electric current, and draw each polysilicon load resistance in each these storage unit $(\frac{V_{\mathrm{cc}}}{\mathrm{\ΔI}}\×n=\frac{V_{\mathrm{cc}}}{I_2-I_1}\×3n).$

Above embodiment is that all memory block numbers of hypothesis are 4, if in fact there be m, then polysilicon load resistance is $\frac{V_{\mathrm{cc}}}{I_2-{\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="A0110993700131.png"\; state="\{\{state\}\}">I</figure-callout>}}_1}\&times;(m-1)\&times;n.$

From the above, the invention provides a kind of novel SRAM array architecture, circuit design, and simple standby current measuring method, but permeametry SRAM standby current changing value by this, the anti-resistance that pushes away crystal silicon load in the SRAM array in fact, helping the research staff to understand and in fact cause high standby current reason, is from the polysilicon load or the electric leakage of SRAM assembly itself.

In addition, also can get polysilicon load resistance, so that topological design institute predetermined load value and actual measurement gained resistance difference are between the two compensated through actual measurement.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any skilled person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection domain of the present invention is when looking claim and being as the criterion in conjunction with instructions and the accompanying drawing person of defining.

Claims (3)

1. improved static random access memory is characterized in that comprising at least:

2m switchgear (S ₁～S _2m);

2m group supply path (P ₁～P _2m), be coupled to this switchgear (S respectively one to one ₁～S _2m);

M memory block (B ₁～B _m), each this memory block (B _j, 1≤j≤m) disposes two groups of this supply path (P respectively _2j-1, P _2j); Wherein, arbitrary this memory block (B _j) comprise n storage unit (C _{J_1}～C _{J_n}), each this storage unit (C _{J_k}, 1≤k≤n) is by four transistors, and two groups of (L that carry on the back or on the head _{J_k_1}, L _{J_k_2}) constitute and these two groups of load (L _{J_k_1}, L _{J_k_2}) be coupled to corresponding two groups of supply path (P _2j-1, P _2j);

The chip enable switching device shifter when memory chip enabling signal (CE) is in first current potential, makes all switchgear (S ₁～S _2m) conducting, supply path provides electric power to memory block, allows static random access memory carry out normal running; And

Device for selection controlling is when this memory chip enabling signal (CE) is in second current potential, when this static random access memory is in holding state, in order to from this switchgear (S ₁～S _2m) in, select pair of switches device (S at least _2j-1, S _2j) give conducting, to carry out dependence test.

2. static random access memory according to claim 1 is characterized in that each switchgear (S ₁～S _2m) be transistor.

3. one kind is utilized current measurement to draw static random access memory load resistance method, and the static random access memory that is suitable for this method comprises at least:

2m group supply path (P ₁～P _2m); And

M memory block (B ₁～B _m), each memory block (B _j, 1≤j≤m) disposes two groups of these supply paths (P respectively _2j-1, P _2j); Wherein, arbitrary memory block (B _j) comprise n storage unit (C _{J_1}～C _{J_n}), each storage unit (C _{J_k}, 1≤k≤n) is by four transistors, and two groups of (L that carry on the back or on the head _{J_k_1}, L _{J_k_2}) constitute and these two groups of load (L _{J_k_1}, L _{J_k_2}) be coupled to corresponding a pair of this supply path (P _2j-1, P _2j);

It is characterized in that this method comprises:

M is set to switchgear (S _2a-1, S _2aA=1～m), couple supply path (P respectively ₁～P _2m);

Allow this static random access memory enter first pattern, make switchgear (S ₁～S _2m) not conducting, use making this supply path (P ₁～P _2m) can't supply capability give this memory block (B ₁～B _m);

Measure this static random access memory standby current, obtain the first electric current (I ₁);

Optionally allow this switchgear (S ₁～S _2m) in Q to the switchgear conducting, by this can supply capability give Q this memory block can be by primary power unit feeding electric power;

Measure this static random access memory standby current, obtain the second electric current (I ₂);

With this second electric current (I ₂) and this first electric current (I ₁) difference is again divided by m-Q, and draw the electric current (Δ I) that all storage unit circulated in arbitrary Q memory block;

Draw the 3rd electric current (Δ I/n) that each storage unit circulates; And

With current potential (V _Cc) divided by the 3rd electric current, and draw each load resistance in each storage unit $(\frac{V_{\mathrm{cc}}}{\mathrm{\&Delta;I}}\&times;n).$

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