CN1373570A - Method for detecting and restoring underload and overload slip - Google Patents
Method for detecting and restoring underload and overload slip Download PDFInfo
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- CN1373570A CN1373570A CN 01142212 CN01142212A CN1373570A CN 1373570 A CN1373570 A CN 1373570A CN 01142212 CN01142212 CN 01142212 CN 01142212 A CN01142212 A CN 01142212A CN 1373570 A CN1373570 A CN 1373570A
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- pointer
- dbces
- buffer
- cell
- location
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5649—Cell delay or jitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
- H04L2012/5653—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL]
- H04L2012/5654—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly using the ATM adaptation layer [AAL] using the AAL1
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
Abstract
A method of managing buffers in a SAR (Segmentation and Reassembly) device in a cell-relay network in dynamic bandwidth circuit emulation mode involves reading out TDM data from a buffer at a location determined by a read pointer, and writing data from incoming cells commencing at a buffer location determined by a write pointer. The write pointer is incremented as data from incoming cells arc written into said buffers. On arrival of an incoming cell a determination is made as to the location of said write pointer. If the location of the write pointer lies between a first value equal to the location of the read pointer plus a predetermined maximum lead plus a predetermined DBCES buffer less the number of bytes per active channel and a second value equal to the location of the read pointer plus said predetermined DBCES buffering, an overrun condition is declared. If the location of said write pointer exceeds the location of the read pointer plus the predetermined maximum lead plus the predetermined DBCES buffer, an underrun condition is declared. This method takes into account additional buffering that is required to prevent underruns and overruns when operating in DBCES mode.
Description
Invention field
The present invention relates to digital communicating field, particularly be used for when dynamic bandwidth circuit artificial service writes cyclic buffer, detecting and recovering underload and method slipping on overload.
Background of invention
ATM (asynchronous transfer mode) be a kind of on the packet switching network in the grouping of little fixed dimension or cell the business of carrying data.This cell quilt statistically multiplexing on the fixed physical link between the network node, and on the network between the end points, set up virtual circuit.ATM comprises a plurality of standards, and wherein AAL1 (ATM adaptation layer 1) sets up a kind of standard be used for carrying voice for example or the such time-sensitive data of video image on the virtual circuit between the end points.This is called as circuit simulation (CES), because it provides a plurality of voice channels, this channel is similar to time division multiplex channel concerning the user.
DBCES is effective according to the time slot that detects which given time division multiplexing main line and result's a kind of pattern that dynamic bandwidth is used in atm network which time slot is invalid.When detecting disarmed state in specific time slot, this time slot is discharged from next atm fabric, and its used bandwidth can be reused for other business.DBCES describes in detail in atm forum specification: af-vtoa-0085.000 (in July, 1997).
The equipment that is called as SAR (segmentation and reconfigure) equipment is converted to cell to the input data, and vice versa.SAR comprises the buffer that is used to store the cell of wanting processed.The cell that arrives far-end is converted into data.ATM (asynchronous transfer mode) is a kind of digital communication system based on cell relay, and its permission is set up virtual circuit on a packet switching network.
A kind of AAL1 SAR equipment that is called MT90500 is sold by Mitel company, is used for the traffic of delivery time sensitivity between TDM (time division multiplexing) bus and ATM (asynchronous transfer mode) cell flow.The details of this equipment can find on the network address http://WWW.mitelsemi.com/index.html of Mitel.In MT90500, be written into cyclic buffer from the data of input ATM cell writing the determined position of pointer, and read from this cyclic buffer by a reading pointer at reasonable time by one, be used for being inserted into the TDM channel.The separation of reading and writing between the pointer has determined the buffer level that occurs at any time.If the data deficiencies in buffer underload phenomenon then occurs to fill corresponding TDM time slot.If the data in cyclic buffer are rewritten by new data before being read out the TDM channel, the overload phenomenon then appears.Both of these case obviously be do not wish to occur, and be commonly referred to the frame slippage.
In MT90500, to writing pointer value and reading pointer numerical value compares.According to distance between two pointers (and according to taking the lead (MinimumLead) and the maximum comparison that takes the lead (Maximum Lead) parameter) with user-defined minimum, show situation underload or overload, and be adjusted to a slippage pointer value writing pointer, to help to prevent further slippage (underload or overload).Approach minimum leading illegal position if write pointed, show that then appearance is underload; Approach maximum leading illegal position if write pointed, then show overload to occur." illegally " position is meant not in the leading and maximum position between leading of minimum.
In the common pending application application that we submit on the same day, we have proposed underload and improvement overload detection, make it more intelligent more than MT90500 when being used for SDT (structured data transfer) pattern.
This improvement comprises that use " change (turn) " numerical digit discerns overload and underload, particularly when data flow stops (for example, cut-out virtual circuit) better.Equally, adopt different standards to discern underload and overload.According to the instruction in our the common pending application application:
Pointer is positioned at reading pointer position pointed and reading pointer adds if write
It is leading greatly that (between the position of 2 * CDV) gained numeric representations, wherein CDV is a cell
Postpone to change, then think slippage not occur.Therefore, do not adjust and write pointer
If write numerical value that pointer is positioned at " reading pointer add maximum leading " and " read
Fetch pointer adds the maximum leading cell that adds " numerical value between, then think appearance
The overload phenomenon.
" reading pointer adds the maximum leading cell that adds " is quickly calculated to referring to
To an address, this address is than reading pointer maximum in advance leading (being programmed by the user)
Add when a cell arrives and to write the maximum word that reconfigures cyclic buffer
Joint number is (for example, if only there is a channel, then when receiving a cell in VC
The time, can write 47 channels the circular buffering of this VC (virtual circuit) at most
Device; If 23 channels are arranged in a VC, then when cell arrives,
Three channels can be written to the cyclic buffer of one of them VC at most).
Surpass " reading pointer adds the maximum leading cell that adds " if write pointer
Numerical value, then think underload state to occur.
This slippage detection routine is designed to SDT (structured data transfer) operation, and does not consider the buffering that prevents that when working in the DBCES pattern special use underload and that the overload appearance is required from adding.Need to adjust the standard that is used to discern normal, overload and underload state, to consider this buffering.
Distinguish normal, underload and overload when an object of the present invention is under working in the DBCES pattern, to write a cyclic buffer.
Summary of the invention
According to the present invention, provide the method for a kind of management buffer in the SAR of cell relay network (segmentation and reconfigure) equipment in the dynamic bandwidth circuit artificial pattern at this, comprising from buffer, reading TDM (time division multiplexing) data reading the determined position of hour hands by one; From beginning to write data from the input cell by writing the determined buffer positions of pointer; When the data from the input cell are written to described buffer, increase the said write pointer; And wherein, when the input cell arrives, determine the position of said write pointer, and:
(i) be in and equal reading pointer and add that predetermined maximum is leading and add that predetermined DBCES buffering deducts first numerical value of position of the byte number of each efficient channel if write the position of pointer, and equal then to show overload to occur between the second value of position that reading pointer adds the above predetermined DBCES buffering; And
If (ii) the position of said write pointer surpasses reading pointer and adds the above predetermined maximum leading position that adds predetermined DBCES buffering, then show underload state to occur.
Said method detects the CES operation (SDT) that combines and be used for standard with normal slippage usually.
Under state situation (ii), although should avoid writing the too leading reading pointer of pointer usually, but more possible is not to be in overload, writing pointer in fact is not far ahead of reading pointer, but for example writes the actual reading pointer that lags behind of pointer because the interruption of virtual circuit or the quick clock relevant with the reflector clock cause.
Therefore the present invention can distinguish underload when working in the DBCES pattern and overload.
The accompanying drawing summary
To only with reference to accompanying drawing the present invention be described in further detail by way of example below, wherein:
Fig. 1 is illustrated in normal, overload and the underload state that SDT in the SDT pattern reconfigures cyclic buffer;
Fig. 2 is illustrated in the DBCES pattern SDT is reconfigured the normal write operation of switching buffer;
Fig. 3 is illustrated in the DBCES pattern SDT is reconfigured the overload write operation of switching buffer;
And Fig. 4 is illustrated in the underload write operation that in the DBCES pattern SDT is reconfigured the switching buffer.
Preferred embodiment describes in detail
Referring now to Fig. 1,, in " normally " or basic SDT (structured data transfer) operation, cell arrives SDT with the speed that equates and receives SAR (RX_SAR), and because the change delay in the transmission circuit causes some cells to postpone to change (CDV).Because cell arrives with speed that " on average " equates, they usually by with reading pointer at a distance of an average distance (this average distance is～CDV) part is written to cyclic buffer.Because cell postpones to change, the arrival speed of cell may be slower or faster than average speed, if but in buffer, always there are a plurality of cells to equal CDV, slippage then should not can appear.Extreme case (for example, virtual circuit is cut off, and perhaps receiver and reflector clock depart from widely) only ought occur, then slippage will occur.
In Fig. 1, the operation of this buffer in the SDT pattern is shown, slack byte is represented the byte that has been read, perhaps the byte that is not written under situation about starting.Under normal condition, wherein write pointer and drop in the minimum leading and maximum window that takes the lead between the parameter, and then new data are write direct after legacy data.Minimum and maximum leading parameter has been determined a window in cyclic buffer, can receive cell data and underload or overload do not occur in this window.These positions always determine with respect to the reading pointer position, and the position of reading pointer can be read from buffer and increases along with tdm data certainly.
Under overload, write pointer and be positioned at after the maximum leading position, and be moved to average leading position.These valid data that cause also not reading are rewritten.Under underload state, write pointer and be positioned at before the minimum leading parameter, and moved to mean place once more, the byte that causes reading in the past is left in the basket.When these data were read the TDM bus, it can be replaced by blank signal or repeating signal.
But in the DBCES pattern, cell is accompanied by the delay that is greater than or less than CDV and arrives sometimes.When the efficient channel number in virtual circuit changed, this situation occurred termly.As a result, cell can not perhaps slippage will occur always being written to this buffer with reading pointer at a distance of the distance of CDV.Therefore, must consider to produce a slippage pointer value, it will avoid the slippage of repetition.As a result, must a kind of new method of design come in the DBCES pattern, to distinguish underload and overload.
In Fig. 2 to 4, supposing maximum leading is 8 bytes, average leading is 4 bytes, be 16 bytes for the required buffering of DBCES, and the number of efficient channel is 5, this means that each cell has 10 bytes can be written to each buffer at most.
As shown in Figure 2, be positioned at reading pointer position pointed if write pointer, and the efficient channel CDV that reading pointer+maximum take the lead+is used for VC cushions between the numerical value of limit, then thinks slippage not occur, and the next cell that arrives is written in the position that writes pointer.
The activity overview of given VC, the byte number that the efficient channel CDV buffering limit that is used for VC is calculated as the required DBCES buffering of user (reconfigures control structure at the DBCES that is used for VC, disposed by being provided with of DBCES control field), deduct and can be written into the maximum number of byte that each SDT that is used for VC reconfigures cyclic buffer.If two efficient channels are arranged in VC, then carry the pay(useful) load of 47 bytes owing to a cell, when a cell arrives, there are 24 byte datas can be written to each cyclic buffer at most.Round up to 47/2 and to draw maximum 24 bytes of each channel.
As shown in Figure 3, if when an input cell arrives, when writing pointer and being positioned between " it is maximum leading that reading pointer adds; add the efficient channel CDV buffering limit that is used for VC " and " reading pointer adds maximum leading; add the buffering limit of the required DBCES that is used for VC ", if because cell write in this position, some have been stored in the cyclic buffer but the data that also are not read might be rewritten, and therefore think overload (referring to Fig. 3) to occur.
As shown in Figure 4, if when an input cell arrives, write pointer and surpass " reading pointer adds maximum leading; add the required DBCES buffering limit that is used for VC ", then think underload state to occur, and be adjusted to and on average leadingly add that required DBCES buffering deducts the byte number of each efficient channel writing pointer value.Should avoid writing so " taking the lead " this reading pointer of pointer because " normally " and " overload " checked, therefore think that this state is underload state.More possible is writes pointer and has fallen behind reading pointer (for example, owing to cut off vc state or read clock faster than reflector clock), and in fact reading pointer points to also not to be received and think highly of the legacy data of writing.
Certainly, the professional in this area should know the size that can change reading pointer and write pointer value, for example comprises more revolution position, can judge better whether a slippage has transshipped or underload.
Therefore, the invention provides a kind of when work in the effective ways that DBCES pattern following time recovers from underload and slipping on overload.
Claims (6)
1. a management is in the method for the buffer in the SAR of cell relay network (segmentation and reconfigure) equipment under the dynamic bandwidth circuit artificial pattern, and it comprises:
From buffer, read TDM (time division multiplexing) data reading the determined position of hour hands by one;
From beginning to write data from the input cell by writing the determined buffer positions of pointer;
When the data from the input cell are written to described buffer, increase the said write pointer; And
It is characterized in that, when the input cell arrives, determine the position of said write pointer, and:
(i) be in and equal reading pointer and add that predetermined maximum is leading and add that predetermined DBCES buffering deducts first numerical value of position of the byte number of each efficient channel if write the position of pointer, and equal then to show overload to occur between the second value of position that reading pointer adds the above predetermined DBCES buffering; And
If (ii) the position of said write pointer surpasses reading pointer and adds the above predetermined maximum leading position that adds the above predetermined DBCES buffering, then show underload state to occur.
2. method according to claim 1 is characterized in that, this cell relay network is a kind of atm network, and the byte number of each efficient channel is determined divided by the efficient channel number by 48.
3. method according to claim 1 is characterized in that, when showing overload or underload state, the said write pointer is moved to a precalculated position of described relatively reading pointer.
4. method according to claim 1 is characterized in that, described precalculated position equals average taking the lead and adds that predetermined DBCES buffering deducts the byte number of each efficient channel.
5. method according to claim 4 is characterized in that, the average leading cell delay variation that equals to be used for the cell relay network.
6. method according to claim 5 is characterized in that, the maximum leading maximum that equals not occur transshipping in normal non-DBCES pattern takes the lead.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBNO.0022683.7 | 2000-09-15 | ||
| GB0022683A GB2366935B (en) | 2000-09-15 | 2000-09-15 | Method of checking for and recovering from underruns and overrun slips when writing to circular buffers in dynamic bandwidth circuit emulation services |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1373570A true CN1373570A (en) | 2002-10-09 |
Family
ID=9899541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01142212 Pending CN1373570A (en) | 2000-09-15 | 2001-09-14 | Method for detecting and restoring underload and overload slip |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN1373570A (en) |
| GB (1) | GB2366935B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442764C (en) * | 2005-06-06 | 2008-12-10 | 华为技术有限公司 | Controlling method for SAR treatment chip transmitting congestion |
| CN103970637A (en) * | 2013-04-22 | 2014-08-06 | 龚惠民 | Method for recovering from system data underload abnormality automatically |
| CN105183553A (en) * | 2015-10-31 | 2015-12-23 | 山东智洋电气股份有限公司 | Software bus program concurrence resource distribution method |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2399980A (en) * | 2003-03-26 | 2004-09-29 | Zarlink Semiconductor Ltd | Packet buffer management |
| GB0313986D0 (en) | 2003-06-17 | 2003-07-23 | Zarlink Semiconductor Inc | Data memory extension for use in double buffered TDM switches |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2703417B2 (en) * | 1991-04-05 | 1998-01-26 | 富士通株式会社 | Receive buffer |
-
2000
- 2000-09-15 GB GB0022683A patent/GB2366935B/en not_active Expired - Fee Related
-
2001
- 2001-09-14 CN CN 01142212 patent/CN1373570A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100442764C (en) * | 2005-06-06 | 2008-12-10 | 华为技术有限公司 | Controlling method for SAR treatment chip transmitting congestion |
| CN103970637A (en) * | 2013-04-22 | 2014-08-06 | 龚惠民 | Method for recovering from system data underload abnormality automatically |
| CN105183553A (en) * | 2015-10-31 | 2015-12-23 | 山东智洋电气股份有限公司 | Software bus program concurrence resource distribution method |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0022683D0 (en) | 2000-11-01 |
| GB2366935A (en) | 2002-03-20 |
| GB2366935B (en) | 2004-01-07 |
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