CN1373555A - Reglating method and circuit for poewr amplifying circuit using drain as output stage - Google Patents
Reglating method and circuit for poewr amplifying circuit using drain as output stage Download PDFInfo
- Publication number
- CN1373555A CN1373555A CN 01109307 CN01109307A CN1373555A CN 1373555 A CN1373555 A CN 1373555A CN 01109307 CN01109307 CN 01109307 CN 01109307 A CN01109307 A CN 01109307A CN 1373555 A CN1373555 A CN 1373555A
- Authority
- CN
- China
- Prior art keywords
- effect transistor
- transistor
- resistance
- amplification circuit
- power amplification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
A power amplifying circuit is composed of a differential amplifier, an adjustable constant current source connected to the emitters of said differential amplifier, an output stage with the first and the second FETs with drain as output, a current control unit containing the third and the fourth transistors, and a voltage control unit containing the first and the second resistors. Its advantages are low cost, high reliability and low linear distortion.
Description
The present invention relates to the method for a kind of power amplification circuit and adjusting thereof, specifically, relate to a kind of reglating method and circuit thereof of making the power amplification circuit of output stage with drain electrode.
Most widely used in the low frequency power amplification sector is that the single power supply OTL (out-put-transformer-less) has the output coupling capacitor circuit-mode of (being called for short OTL), or by the dual power supply OTL (out-put-transformer-less) OCL output capacitance-less circuit-mode of (being called for short OCL).Wherein Fig. 1 shows the typical OCL circuit structure of typically being made up of the transistor power amplifier, and it is driven by level Four forms: a differential amplifying stage, and the transistor Q1 and the Q2 that are connected by symmetry form, and are used to control the input and output of negative feedback NFB; One principal voltage amplifying stage is promptly finished voltage drive, is used to make output voltage amplification, and Q3 forms by transistor; One promotes amplifying stage, promptly finishes current drives, is made up of the transistor Q4 and the Q5 that are connected in series; And a power-amplifier stage, be the complementary push-pull emitter follower that adopts multistage darlington structure, wherein by the emitter of the transistor Q6 of serial connection and Q7 as output stage.When specifically using the amplifying circuit of this prior art, in order to realize the purpose of circuit adjustment, also need insert an adjustable constant-flow source respectively at differential amplifying stage and principal voltage amplifying stage, and the constant pressure source U0 that in the principal voltage amplifying stage, needs to insert the static bias current of a power-adjustable pipe.
Should be pointed out that when selecting large power triode for use the foregoing circuit pattern is reasonably preferred as output.But,,, correspondingly increased the loss of circuit and reduced its power output after all along with the increasing of electronic devices and components as having the circuit that level Four is amplified; In addition, owing to insert constant-source with adjustable and adjustable constant pressure source at differential amplifying stage and principal voltage amplifying stage simultaneously, correspondingly the adjusting of its output is comparatively complicated.
Prior art also has a kind of typical OCL circuit structure when making efferent duct by the MOSFET power tube, as shown in Figure 2.It comprises: a differential amplifying stage, and the transistor Q1 and the Q2 that are connected by symmetry form, and are used to control the input and output of negative feedback NFB; One principal voltage amplifying stage is promptly finished voltage drive, is used to make output voltage amplification, and Q3 forms by transistor; And a power-amplifier stage, by the source electrode of the mosfet transistor Q1a of serial connection and Q1b as output stage.Equally, still need insert constant-source with adjustable and adjustable constant pressure source, the output that comes regulating circuit at differential amplifying stage and voltage amplifier stage.Should the MOSFET pipe be the voltage-controlled device of a kind of desirable high speed.But, the power amplifier of doing output stage with the MOSFET pipe of above-mentioned prior art seldom is applied, be because the grid source cut-in voltage of MOSFET is too high, be generally 2～4V (and the cut-in voltage of normal transistor is 0.2V), and the defect that causes signal voltage loss, power output to diminish.
From the contrast of table 1, the difference of the power output of our above-mentioned as can be seen two kinds of prior art circuits.Fig. 1 and Fig. 2 when same direct-current working volts ± 30V maximum output voltage and the contrast table of power and power:
| The amplifier type | Maximum output voltage/8 ohm | Peak power output/8 ohm |
| The output of employing transistor | ????19V?RMS | ????45W?RMS |
| Adopt MOSFET output | ????17V?RMS | ????36W?RMS |
Therefore, just because of this significant deficiency of power loss, just caused it in linear power amplification, seldom to use.
Another fatal defective of above-mentioned prior art is, since the MOSFET pipe with source electrode as output stage, adjusting to its drain-to-gate voltage knot is not have to help in the adjusting to its source electrode output voltage, and in fact, it is very difficult and almost can't realize that desire is regulated the output voltage of sort circuit.
In addition, traditional circuit illustrated in figures 1 and 2 all exists in reliability design because of output and floats thereby adopt inconvenience so that short-circuit protection to realize complicated defective to the efferent duct electric current.
Yet MOSFET pipe but is ideal power amplifying device, if overcome the defective of MOSFET tube power loss, this desirable high speed, the voltage-controlled device change of high electric current meeting are popularized in linear power amplification short circuit.
One object of the present invention is to propose a kind of reglating method of power amplification circuit, and this method is made output stage with the drain electrode of MOSFET pipe, thereby has realized its output voltage synchronous adjustable by the Current Regulation and the interlock voltage-regulation of interlock;
Another object of the present invention is to propose a kind of power amplification circuit, and this circuit is made output stage with the drain electrode of MOSFET pipe, regulates by the interlock to its output stage, has improved the power output of MOSFET pipe.
The present invention is achieved through the following technical solutions:
According to an aspect of the present invention and since to drain electrode output the MOSFET pipe, the interlock regulation technology by electric current makes the negative portion that exports recommend the bias current synchronous adjustable of pipe, and is simple and easy to do.
According to a further aspect of the invention, adopt power amplifier of the present invention, its Dynamic Signal also is exaggerated in the transmission course of current regulating circuit, and directly coupling, thereby has simplified circuit, has reduced cost, is convenient to the raising of its power output.
In accordance with a further aspect of the present invention, power amplifier of the present invention is compared with traditional circuit, because its circuit is simple and practical, makes it have the highest efficient.If when lower operating voltage, as ± 15V, this advantage will be more obvious.
In accordance with a further aspect of the present invention; because the current sample of circuit of the present invention is convenient; by the rest-set flip-flop that in circuit of the present invention, is provided with; when the power tube overcurrent; it can turn-off whole operating current rapidly; rapider, more reliable than traditional any short-circuit protection circuit, and can remove the back in short circuit and recover automatically, so its protective value is tending towards perfect.Simultaneously, because the second breakdown effect of the no transistor of MOSFET pipe, and have negative temperature coefficient feature, make the reliability of entire circuit improve greatly.
By description, will make above-mentioned technology side peace of the present invention and other advantage apparent below in conjunction with accompanying drawing to preferred embodiment of the present invention.
In the accompanying drawing:
Fig. 1 is a kind of OCL circuit that adopts transistor to make power amplifier of prior art;
Fig. 2 is that the another kind of prior art adopts the MOSFET pipe to make the OCL circuit of power amplifier;
Fig. 3 is a preferred embodiment of two utmost point amplifying circuits of the present invention, and wherein input stage is the NPN pipe, and power output stage is the drain electrode of MOSFET pipe;
Fig. 4 is the flow chart that two utmost point amplifying circuit interlocks of the present invention are regulated;
Fig. 5 is another embodiment of two utmost point amplifying circuits of the present invention, and wherein input stage is the PNP pipe;
Fig. 6 is an embodiment again of two utmost point amplifying circuits of the present invention, and wherein two of output arms adopt a plurality of MOSFET pipes to be in parallel.
Hereinafter, will describe the present invention in detail.
At first, referring to as shown in Figure 3 secondary power amplifier of the present invention.It comprises: a differential amplifying stage, and the transistor Q11 and the transistor Q12 that are connected by symmetry form (this transistor is a NPN type pipe), are used for the control of negative feedback input and output; One adjustable constant-flow source Ip is connected with the emitter of this differential circuit; One output stage is made up of opposite polarity MOSFET pipe Q21 and Q22, and its source electrode is connected with positive-negative power ± Vcc by a resistance respectively, and it drains as output stage; One current control unit, be used to constitute the input control of described two field effect transistor gate voltages of described power-amplifier stage, connect to form by transistor Q13 and Q14 symmetry, the base stage of this transistor Q13 is connected with the collector electrode of described transistor Q11, emitter is connected with the grid of described MOSFET pipe Q21, the base stage of this transistor Q14 is connected with the collector electrode of described transistor Q12, and emitter is connected with the grid of described MOSFET pipe Q22; And, one voltage control unit, form by resistance R 11 and resistance R 12, this resistance R 11, be connected between the emitter of positive supply+Vcc and described transistor Q13, this resistance R 12 equates with the resistance of resistance 11, and is connected between negative supply one Vcc and the described transistor Q14 emitter.Certainly, obtain transistor Q13 and Q14 and will obtain the electric current that changes synchronously, between pipe Q14 and positive voltage+Vcc, also will insert one and the resistance R 13 of resistance R 11 equivalences.
Realize that for foregoing circuit of the present invention the method that interlock is regulated is such, see also flow chart shown in Figure 4.------positive-negative power ± Vcc, next step S102 are the differential amplifier circuits of selecting a symmetry to connect, are used for degenerative input and output control at first, at step S100 working power to be set.The more important thing is that reglating method of the present invention also needs a constant-source with adjustable Ip simultaneously, as step S104, like this by regulating this constant-source with adjustable Ip, just can obtain the pipe Q11 of variation synchronously and the collector current of Q12.
Secondly, at step S106, between positive-negative power ± Vcc, need to be provided with two opposite polarity MOSFET pipe Q21 and Q22, and its drain electrode is linked to each other as output stage.
Next, prior, at step S108 transistor Q13 and the Q14 that symmetry connects need be set, by in step S110, will inserting equivalent resistance R 11 and R13 between itself and the positive supply+Vcc, like this will be at step S112, obtain identical electric current I 13 and I14 on pipe Q13 and Q14, the circuit that will obtain the synchronizing current of this uniqueness here is called " multitude's formula current mirror "; And when regulating adjustable constant-flow source Ip, electric current I 11 and I12 in the differential circuit on pipe Q11 and the Q12 will change synchronously.Through identical resistance R 11 and R13, will have same pressure drop to put on pipe Q13 and Q14 from positive supply+Vcc, therefore managing Q13 will open and have identical electric current synchronously with Q14.
More particularly, purpose for the gate source voltage that reaches adjusted in concert pipe Q21 and Q22, the present invention is at step S114, emitter in pipe Q14 inserts resistance R 12, because this resistance R 12 is formed between the grid source knot of pipe Q22, therefore the Vds1 of the gate source voltage Vds2 of this Q22 and Q21 just with, like this " multitude's formula current mirror " just constant-current source Ip variation and convert " multitude's formula voltage mirror " to.
As seen, the MOSFET pipe as drain electrode output of the present invention, its high cut-in voltage in grid source can not have influence on output, and output voltage is and output pipe end saturation voltage drop that promptly MOSFET pipe end channel resistance is relevant.And the channel resistance of current MOSFET pipe is extremely low, and the IRF540 of producing with American I RF company is an example, and its channel resistance has only 0.05 ohm, and the pressure drop during operating current 10A is 0.5V, well below transistor commonly used in power amplification circuit.
The result who records from experiment as can be known, under same condition of work, promptly ± 30V, the power consumption of the second amplifying circuit of the present invention that records can see Table 2.
Table 2:
| The amplifier type | Maximum output voltage/8 ohm | Peak power output/8 ohm |
| Amplifying circuit of the present invention | ????20.5V?RMS | ????52.5W?RMS |
Data according to table 1 and table 2 contrast as can be known, and second amplifying circuit of the present invention has the highest efficient.When if operating voltage further reduces, the advantage of second amplifying circuit of the present invention is fallen more obvious.The power output of three kinds of circuit enumerating referring to table 3 when ± 15V.
Table 3:
| The amplifier type | Maximum output voltage/8 ohm | Peak power output/8 ohm |
| Traditional transistor power amplifier | ????9V?RMS | ????10W?RMS |
| Traditional MOSFET pipe power amplifier | ????7.8V?RMS | ????7.5W?RMS |
| Amplifying circuit of the present invention | ????10.3V?RMS | ????13.2W?RMS |
In addition, secondary circuit of the present invention is realized overcurrent protection easily, promptly after the arbitrary resistance R 21 or R22 sampling that are connected with described power amplification circuit, is sent to adjustable constant-flow source Ip.
Should be noted that in the preferred embodiment of the present invention as shown in Figure 3 the pipe Q11 of differential amplifier circuit and Q13 adopt NPN transistor, MOSFET pipe Q21 should be P channel-type pipe so, and is connected with forward power supply+Vcc; MOSFET pipe Q22 then should be N channel-type pipe, and power supply-Vcc is connected with negative sense.
Should imagine that equally if the pipe Q11 of differential amplifier circuit and Q13 adopt PNP transistor, as shown in Figure 5, MOSFET pipe Q21 should be N channel-type pipe so, and is connected with forward power supply+Vcc; MOSFET pipe Q22 then should be P channel-type pipe, and power supply-Vcc is connected with negative sense.
In the practice, this power amplification circuit of the present invention has widely to be used, and comprises being applied to those high-power circuits.Therefore, one according to a distortion of the present invention, as shown in Figure 6, can form MOSFET pipe Q21 group respectively and MOSFET pipe Q22 organizes with some effect transistors are parallel with one another.
It is also understood that and to make various deformation that for example: falling the adjustable constant-flow source can be realized by the multiple circuit of triode, MOSFET pipe according to technical scheme of the present invention; Import differential pipe and can adopt cascode utmost point gang mould formula; Symmetry connects moving Q13 and Q14 can adopt MOSFET pipe replacement etc., and they all should belong to the protection range of claims of the present invention.
Claims (16)
1, a kind of reglating method of the power amplification circuit of making output stage with draining is characterized in that,
A) two field-effect transistor symmetries are connected between two first and second opposite power supplys, it drains jointly as output stage;
B) differential amplifier circuit that a symmetry connects is set;
C) emitter at described differential amplifier circuit connects an adjustable constant-flow source, is used to obtain the collector current of symmetry;
D) two transistor symmetries are connected, utilize the collector current of described differential amplifier circuit to control its unlatching, be used to obtain the output current of symmetry;
E) utilize the output current of described symmetry, control the unlatching of described two field effect transistor;
F) utilize the output current of described symmetry to obtain identical voltage drop, regulate the voltage in grid source of two field effect transistor of described two field effect transistor.
2, method according to claim 1 is characterized in that, described step d) also comprises following processing:
G) between the emitter of described two transistors and described first power supply, insert the resistance of two equivalences respectively.
3, method according to claim 2 is characterized in that, also comprises the following steps:
H) emitter with a described transistor is connected with the base stage of a described field effect transistor;
I) collector electrode with described another transistor is connected with the base stage of described another field effect transistor.
4, method according to claim 3 is characterized in that, also comprises the following steps:
J) collector electrode at described another transistor inserts a resistance, form the loop with the grid source electrode of described another field effect transistor, and this resistance equates with the described resistance that is serially connected in its emitter.
5, method according to claim 4 is characterized in that, also comprises the following steps:
K) between described two field effect transistor and described first and second power supplys, insert substitutional resistance.
6, method according to claim 5 is characterized in that, comprises
L) take a sample from the arbitrary resistance that links to each other with field effect transistor, current foldback circuit is set, and be sent to described adjustable constant-flow source.
7, a kind of power amplification circuit comprises
One differential amplifying stage is made up of first triode and second triode that symmetry connects, is used for the control of negative feedback input and output, it is characterized in that described power amplification circuit also comprises
One adjustable constant-flow source is connected with the emitter of described differential circuit;
One output stage is provided with
First field-effect transistor, its source electrode is connected with first power supply via a resistance, and it drains as output stage;
Second field-effect transistor, its source electrode is connected with second source via a resistance, and this second source is opposite with described first electric power polarity, and its drain electrode is connected with the drain electrode of described first field-effect transistor and common output stage as described circuit; And
One current control unit is used to constitute the input control of described two field effect transistor gate voltages of described power amplification circuit, comprises
The 3rd transistor, base stage is connected with the collector electrode of described first triode, and emitter is connected with the grid of described first field-effect transistor; With
The 4th transistor pipe, base stage is connected with the collector electrode of described second triode, and emitter is connected with the grid of described second field-effect transistor; And
One voltage control unit comprises
First resistance is connected between the emitter of described first power supply and described the 3rd transistor; With
Second resistance equates with the resistance of described first resistance, and is connected between described second source and described the 4th transistor emitter.
8, power amplification circuit according to claim 7 is characterized in that, described the 4th transistor is connected with described first power supply via the 3rd resistance, and the 3rd resistance equates with described first resistance.
9, power amplification circuit according to claim 7 is characterized in that, described third and fourth transistor symmetry connects.
10, power amplification circuit according to claim 8 is characterized in that, described circuit also comprises an over-current protecting unit, after the arbitrary resistance sampling that is connected with described power amplification circuit, is sent to described adjustable constant-flow source.
11, power amplification circuit according to claim 7 is characterized in that, some the effect transistor described first field-effect transistor group and the second field-effect transistor groups formed respectively parallel with one another.
12, power amplification circuit according to claim 7 is characterized in that, described differential amplifier circuit adopts NPN transistor.
13, power amplification circuit according to claim 7 is characterized in that, described first field effect transistor is a P channel-type pipe, and is connected with the forward power supply; Described second field effect transistor is a N channel-type pipe, is connected with the negative sense power supply.
14, power amplification circuit according to claim 7 is characterized in that, described differential amplifier circuit is a PNP transistor.
15, power amplification circuit according to claim 14 is characterized in that, described first field effect transistor is a N channel-type pipe, and is connected with the negative sense power supply; Described second field effect transistor is a P channel-type pipe, is connected with the forward power supply.
16, power amplification circuit according to claim 7 is characterized in that, described the 3rd triode and described the 4th triode are field effect transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011093072A CN1150671C (en) | 2001-02-28 | 2001-02-28 | Reglating method and circuit for poewr amplifying circuit using drain as output stage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011093072A CN1150671C (en) | 2001-02-28 | 2001-02-28 | Reglating method and circuit for poewr amplifying circuit using drain as output stage |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1373555A true CN1373555A (en) | 2002-10-09 |
| CN1150671C CN1150671C (en) | 2004-05-19 |
Family
ID=4657852
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011093072A Expired - Fee Related CN1150671C (en) | 2001-02-28 | 2001-02-28 | Reglating method and circuit for poewr amplifying circuit using drain as output stage |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1150671C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101785178B (en) * | 2007-04-04 | 2012-11-28 | 艾利森电话股份有限公司 | Circuitry and method for reducing second and third-order nonlinearities |
| CN112636743A (en) * | 2020-12-25 | 2021-04-09 | 上海华力微电子有限公司 | Push-pull structure output circuit |
-
2001
- 2001-02-28 CN CNB011093072A patent/CN1150671C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101785178B (en) * | 2007-04-04 | 2012-11-28 | 艾利森电话股份有限公司 | Circuitry and method for reducing second and third-order nonlinearities |
| CN112636743A (en) * | 2020-12-25 | 2021-04-09 | 上海华力微电子有限公司 | Push-pull structure output circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1150671C (en) | 2004-05-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6888396B2 (en) | Multi-cascode transistors | |
| CN106230390B (en) | A kind of temperature-compensation circuit of power amplifier | |
| JP3631426B2 (en) | High power amplifier | |
| US7554364B2 (en) | High-voltage operational amplifier input stage and method | |
| US7368992B2 (en) | Load-invariant amplifier | |
| US7439805B1 (en) | Enhancement-depletion Darlington device | |
| CN1537358A (en) | Active bias circuit | |
| AU6452199A (en) | Amplifier arrangement with voltage gain and reduced power consumption | |
| CN112947656B (en) | Low quiescent current, off-chip capacitor LDO with dynamically optimized power supply rejection ratio | |
| US20090251215A1 (en) | Amplifier output stage with extended operating range and reduced quiescent current | |
| KR20060131321A (en) | High efficiency power amplifier with accurate duty cycle | |
| CN1150671C (en) | Reglating method and circuit for poewr amplifying circuit using drain as output stage | |
| US20200366250A1 (en) | Power amplifier system | |
| GB2219705A (en) | Fet amplifier | |
| US10903800B2 (en) | Power amplifier system | |
| US5070308A (en) | Working point adjusting circuit for a power amplifier | |
| CN1059767C (en) | Power amplifier circuit | |
| CN1416615A (en) | Circuit arrangement for adjusting operating point of high-frequency transistor and amplifier circuit | |
| CN219760969U (en) | High input impedance source follower based on bootstrap voltage | |
| US6747513B1 (en) | High fidelity floating bridge amplifier | |
| CN221709815U (en) | Overvoltage regulating circuit of radio frequency power amplifier and communication device | |
| CN1206957A (en) | Power-like amplifier output stage by adopting parallel voltage-stabilizing, quick thermal tracking biased compensation circuit | |
| KR100591062B1 (en) | Linear power amplifier for predistortion by using reverse diode | |
| US6016079A (en) | Power amplifier device | |
| CN112532193A (en) | Transistor amplifier, chip and electronic equipment based on diode feedback |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |