CN1372319A - Semiconductor component package module unit and programming method thereof - Google Patents
Semiconductor component package module unit and programming method thereof Download PDFInfo
- Publication number
- CN1372319A CN1372319A CN 02108448 CN02108448A CN1372319A CN 1372319 A CN1372319 A CN 1372319A CN 02108448 CN02108448 CN 02108448 CN 02108448 A CN02108448 A CN 02108448A CN 1372319 A CN1372319 A CN 1372319A
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- packaging
- base plate
- semiconductor element
- metal
- encapsulation module
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Abstract
A semiconductor elements packing module contains a pack substrate, a semiconductor element and a metal connecting layer with the following production method: to fix at least one of the semiconductor elements with several metal pads at the first surface of the substrate to be aligned with optical aligning machine the to drill holes from the second surface of the substrate of packaging to form a conducting hole on said substrate corresponding to each metal pad and to form a layer of metal on the second surface of the substrate to fill each hole with the metal to form several metal conducting holes, by using microphoto and etching to form a metal connection layer on the second surface containing several wires and contact pads to greatly lower the production cost to be competitive.
Description
Technical field
The present invention relates to encapsulation module of a kind of semiconductor element and preparation method thereof.
Background technology
Press, semi-conductive encapsulation procedure has multiple different kenel, and wherein chip package (flip chipPackage) is a kind of encapsulation technology of crystal grain face down.Please in the lump with reference to figure 1, it is the generalized section of the chip package of prior art, and it comprises a base plate for packaging (substrate) 1, semiconductor element 2, a plurality of projection (bumps) 3, a shim (underfill) 4 and a plurality of solder sphere (solder balls) 5.
Wherein said base plate for packaging 1 is multiple layer metal (4 layers or 6 layers) substrate normally, and it comprises first surface 1a and second surface 1b, more comprises plural conductive plug (via) 6 and a plurality of welded gaskets (solderpads) 7.Described semiconductor element 2 has a plurality of metal gaskets (die Pads), at first forms metal film (Under Bump Metallurgy under the projection at this metal gasket in encapsulation procedure; UBM) (figure is too complicated rather, is not presented on the figure) forms projection 3 again, more described semiconductor element 2 adhered on the first surface 1a of described base plate for packaging 1.Described shim 4 is in order to strengthen the mechanical adhesion strength of 1 of described semiconductor element 2 and base plate for packaging.Described solder sphere 5 is to be positioned on the welded gasket 7 of second surface 1b of described base plate for packaging 1.
Above-mentioned prior art has following shortcoming:
1, known encapsulation procedure must form metal film (UMB) under the projection at this metal gasket earlier, forms projection again, more described semiconductor element is adhered on the first surface of described base plate for packaging.Form wherein that metal film and projection all are the very high processing procedures of cost under the projection.
2, the employed base plate for packaging of prior art multiple layer metal (4 layers or 6 layers) substrate normally, its cost of manufacture is very high.
3,, be applicable to that the cost of detection card of semiconductor element of projection is higher for for the detection card (probe card) that electrically measures.Can learn that by above-mentioned 3 known chip package makes the cost of encapsulation procedure significantly improve because must make metal film and projection under the projection, relatively reduces competitiveness of product.
4, because prior art must be used the base plate for packaging of multilayer, it mostly is organic material (organicmaterial) greatly, and its thermal coefficient of expansion is usually up to 18ppm/ ℃, far above 4ppm/ ℃ of silicon semiconductor element.The difference of this thermal coefficient of expansion causes the threat of temperature cycles reliability (temperature-cyclereliability), and is particularly serious especially for large-area semiconductor element.
5, because described shim must be inserted between semiconductor element and the base plate for packaging in the mode that fluid flows, its viscosity (viscosity) can not be too high, and its material selectivity is restricted.
Therefore, encapsulation module how to develop a kind of brand-new semiconductor element with and manufacturing method thereof, significantly to reduce manufacturing cost and to promote yield, just become crucial problem of semiconductor packages industry.
Summary of the invention
Main purpose of the present invention is for providing a kind of encapsulation module of semiconductor element.
Secondary objective of the present invention is for providing a kind of encapsulation module with a plurality of semiconductor elements.
A further object of the present invention is to provide a kind of manufacture method of encapsulation module of semiconductor element.
The present invention adopts technical scheme as described below for achieving the above object: the encapsulation module of semiconductor element, and it comprises:
One base plate for packaging, it comprises first surface and second surface; Described base plate for packaging more comprises a plurality of metallic conduction plugs that run through and connect its first surface and second surface;
Semiconductor element, it is positioned at the first surface of described base plate for packaging; This semiconductor element more includes a plurality of metal gaskets, and wherein each metal gasket all is connected to a described metallic conduction plug;
One metal connecting layer, it is positioned at the second surface of this base plate for packaging; Described metal connecting layer comprises a plurality of plain conductors and a plurality of contact mat, and wherein each metallic conduction plug all is connected to a described plain conductor.
Wherein said base plate for packaging is made up of the thermal coefficient of expansion insulation material close with described semiconductor element.
Wherein more comprise a gelatinous layer, it is positioned at the first surface of described base plate for packaging, in order to described base plate for packaging and semiconductor element is bonding; Described gelatinous layer has adherence, and its thermal coefficient of expansion is less than 15ppm/ ℃.
Wherein more comprise a metal level, it is positioned on the first surface of this base plate for packaging, and covers described semiconductor element.
Wherein more comprise an insulating barrier, it is positioned at the second surface of this base plate for packaging and covers described plain conductor.
Wherein on each described contact mat, more comprise a solder sphere.
Form the method for the encapsulation module of above-mentioned semiconductor element, it comprises: a base plate for packaging is provided, and it comprises first surface and second surface; At least one semiconductor element is fixed on the first surface of described base plate for packaging, wherein this semiconductor element includes a plurality of metal gaskets; Utilize the optical alignment machine to carry out alignment procedure, utilize the Laser drill processing procedure this base plate for packaging to be holed again, all on this base plate for packaging, form a conductive plug through hole at each metal gasket by second surface; Form the layer of metal layer at the second surface of described base plate for packaging, simultaneously each conductive plug through hole is filled up and form a plurality of metallic conduction plugs, wherein each metallic conduction plug and be connected to a described metal gasket; And utilizing little shadow and etch process to form metal connecting layer at the second surface of described base plate for packaging, it comprises a plurality of plain conductors and a plurality of contact mat.
This method, the second surface that more is included in described base plate for packaging form insulating barrier covering the step of described plain conductor, and the step that forms solder sphere on described contact mat.
This method, the first surface at described base plate for packaging forms the metal level that one deck covers described semiconductor element more simultaneously.
When the translucent material of described base plate for packaging system's employing, then described alignment procedure is to utilize photographic camera to be taken by the second surface of this base plate for packaging, when the light tight material of described base plate for packaging system's employing, then described alignment procedure is to utilize x ray camera to be taken by the second surface of this base plate for packaging.
Adopt the present invention of technique scheme, have following advantage:
1, the present invention must not make metal film under the projection (UBM) and projection (bump), can significantly reduce the cost of encapsulation procedure.
2, base plate for packaging of the present invention must not use multiple layer metal (4 layers or 6 layers) substrate, can significantly reduce the cost of encapsulation procedure.
3, semiconductor element of the present invention not palpiform become projection, the detection card (probe card) of therefore must use cost not higher electrical measurement can reduce the cost of electrical measurement.
4, the material approaching can be selected for use because of base plate for packaging of the present invention, its temperature cycles reliability (temperature-cycle reliability) can be significantly promoted with the thermal coefficient of expansion of semiconductor element.
5, the present invention its be positioned on the first surface of this base plate for packaging and cover the metal level of described semiconductor element and gelatinous layer, can form an electromagnetic shielding to prevent the electrostatic breakdown semiconductor element, can strengthen heat sinking function, and can prevent the moisture invasion.
6, because gelatinous layer of the present invention does not need calking like the shim of prior art, therefore gelatinous layer of the present invention can be selected the higher material of the coefficient of viscosity for use, can strengthen the blocks moisture effect of encapsulation module.
7, the lower material of thermal coefficient of expansion can be selected for use because of base plate for packaging of the present invention, the stability of its size can be significantly promoted.
8, the revealer of institute of the present invention is LGA (land grid array) processing procedure, can convert PGA (pin grid array) processing procedure, CGA (column grid array) processing procedure BGA (ball gridarray) processing procedure easily in addition.
9, can utilize known hyperplasia technology (build-up process) under the structure of encapsulation module of the present invention, second surface 10b at base plate for packaging 10 forms hyperplasia layer (build-up layer), has the semiconductor packages module of multiple layer metal conductive layer (multi-layer interconnect) with formation.
Description of drawings
Fig. 1 is the generalized section of the chip package (flip chip package) of prior art.
Fig. 2 is the generalized section of the encapsulation module of the disclosed semiconductor element of first embodiment of the invention.
Fig. 3 is the generalized section of the encapsulation module of the disclosed semiconductor element of second embodiment of the invention.
Fig. 4 is the generalized section of the encapsulation module of the disclosed semiconductor element of third embodiment of the invention.
Fig. 5 is the disclosed generalized section with encapsulation module (multi-chip module) of a plurality of semiconductor elements of fourth embodiment of the invention.
Fig. 6 A-Fig. 6 F is the generalized section of the manufacture method of the encapsulation module of semiconductor element among the present invention.
The figure number explanation
1 base plate for packaging 1a first surface 1b second surface
2 semiconductor elements, 3 projections, 4 shims
5 solder sphere, 6 conductive plugs, 7 welded gaskets
10 base plate for packaging 10a first surface 10b second surfaces
11 conductive plug through holes, 12 metallic conduction plugs, 20 semiconductor elements
22 metal gaskets, 30 gelatinous layers, 40 metal connecting layer
40a plain conductor 40b contact mat 42 metal levels
50 insulating barriers, 70 solder sphere
Embodiment
At first please refer to Fig. 2, it is the generalized section of the encapsulation module of the disclosed semiconductor element of first embodiment of the invention.The encapsulation module of described semiconductor element comprises a base plate for packaging (substrate) 10, semiconductor element 20, a gelatinous layer (glue) 30, a metal connecting layer (interconnect layer) 40 and one insulating barrier (insulating layer) 50.
Described base plate for packaging 10 comprises first surface 10a and second surface 10b, and it is formed (for example the thermal coefficient of expansion of the semiconductor element 20 that is made of silicon (silicon) is about 4ppm/ ℃) by thermal coefficient of expansion (coefficient of thermal expansion) and described semiconductor element 20 close translucent or lighttight insulation materials.Described base plate for packaging 10 more comprises a plurality of metallic conduction plugs 12 that run through and connect its first surface 10a and second surface 10b, and the diameter of this metallic conduction plug 12 is between 10 microns (micro-meter) are to 100 microns.
Described semiconductor element 20 is positioned at the first surface 10a of described base plate for packaging 10, and it includes a plurality of metal gaskets 22, and wherein each metal gasket 22 all is connected to a described metallic conduction plug 12.
Described gelatinous layer 30 is in order to bonding with semiconductor element 20 with described base plate for packaging 10, it is made up of the material with characteristics such as strong adherence, strong hardness, low thermal coefficient of expansion (less than 15ppm/ ℃) and low humidity gas traps, for example epoxy compound (epoxy compounds), multiple sulphur imido compound (polyimide compounds) or the like.
Described metal connecting layer 40 is positioned at the second surface 10b of this base plate for packaging 10, it comprises a plurality of plain conductors 40a, a plurality of contact mat 40b and plural conductive choker block (via Pads) (is positioned at the conductive plug periphery, figure is too complicated rather, is not presented on the figure).Wherein each metallic conduction plug 12 all is connected to a described plain conductor 40a; Described contact mat 40b is as the usefulness that contacts of this encapsulation module with other circuit boards or probe.
Described insulating barrier 50 is called welding resisting layer (solder mask) again, and it is positioned at the second surface 10b of this base plate for packaging 10 and covers plain conductor 40a, in order to protect described plain conductor 40a.
Next see also Fig. 3, in the second embodiment of the present invention, the encapsulation module of described semiconductor element more comprises a metal level 42, its first surface 10a that is positioned at this base plate for packaging 10 goes up and covers described semiconductor element 20 and gelatinous layer 30, can form an electromagnetic shielding to prevent electrostatic breakdown semiconductor element 20, also the encapsulation module heat sinking function can be strengthened, and moisture invasion semiconductor element 20 can be prevented.Other elements of present embodiment and annexation thereof are all identical with first embodiment, and length is long rather repeats no more.
Next see also Fig. 4, in the third embodiment of the present invention, the encapsulation module of described semiconductor element more comprises a plurality of solder sphere (solder balls) 70, and it is positioned at the second surface 10b of this base plate for packaging 10, and attached on the described contact mat 40b.Described solder sphere 70 is made up of ashbury metal usually, can be as the usefulness of welding.Other elements of present embodiment and annexation thereof are all identical with first embodiment, and length is long rather repeats no more.
Next please refer to Fig. 5, it is the generalized section of the encapsulation module of the disclosed semiconductor element of fourth embodiment of the invention.The encapsulation module of described semiconductor element comprises a base plate for packaging 10, a plurality of semiconductor element 20, a gelatinous layer 30, a metal connecting layer 40 and an insulating barrier 50.
Described base plate for packaging 10 comprises first surface 10a and second surface 10b, and it is formed (for example the thermal coefficient of expansion by the semiconductor element 20 that silicon constituted is about 4ppm/ ℃) by thermal coefficient of expansion and described semiconductor element 20 close translucent or lighttight insulation materials.Described base plate for packaging 10 more comprises a plurality of metallic conduction plugs 12 that run through and connect its first surface 10a and second surface 10b.
Described a plurality of semiconductor element 20 is positioned at the first surface 10a of described base plate for packaging 10, and each semiconductor element 20 all includes a plurality of metal gaskets 22, and wherein each metal gasket 22 all is connected to a described metallic conduction plug 22.Described in addition gelatinous layer 30, metal connecting layer 40, all identical with first embodiment with insulating barrier 50, length is long rather repeats no more.In addition, present embodiment also can add that metal level 42 to prevent electrostatic breakdown semiconductor element 20, strengthens heat sinking function simultaneously as first embodiment, and prevents the moisture invasion; Present embodiment also can add solder sphere on each contact mat 40b as the 3rd embodiment, with the usefulness as welding.
Because of the encapsulation module of present embodiment comprises a plurality of semiconductor elements 20, therefore can form a polycrystalline grain module (multi-chip module; MCM).
Next please refer to Fig. 6 A-Fig. 6 F, it is the processing procedure generalized section of the encapsulation module of the disclosed semiconductor element of various embodiments of the present invention.Please refer to Fig. 6 A, one base plate for packaging 10 at first is provided, it comprises first surface 10a and second surface 10b, then on the first surface 10a of this base plate for packaging 10, form one deck gelatinous layer (glue) 30 in the predetermined semiconductor element part of pasting, carry out one precuring processing procedure (pre-cure process) again, Fig. 6 A is shown be the present invention first, second, and the processing procedure generalized section of the 3rd embodiment, as for the processing procedure of the 4th embodiment about MCM, its formed gelatinous layer 30 also must be positioned at predetermined each semiconductor element part of pasting.Because of the fabrication steps of the 4th embodiment with first, second, and the step of the 3rd embodiment identical, so Fig. 6 A-Fig. 6 F will be only at first, second, the processing procedure section that reaches the 3rd embodiment describes.
Described base plate for packaging 10 is made up of translucent or lighttight insulation material, and its thermal coefficient of expansion is close with the semiconductor element of desiring to carry out encapsulation procedure, and the heat budget (thermalbudget) of encapsulation module is significantly improved.The semiconductor element system of for example desiring to carry out encapsulation procedure is made of silicon, and then base plate for packaging 10 is chosen the nearly 4ppm/ of thermal coefficient of expansion ℃ material, for example ceramic wafer (ceramic platelet) or the like.Described gelatinous layer 30 is in order to described base plate for packaging 10 is bonding with semiconductor element, it is made up of the material with characteristics such as strong adherence, strong hardness, low thermal coefficient of expansion (less than 15ppm/ ℃) and low humidity gas traps, for example epoxy compound (epoxy compounds), multiple sulphur imido compound (polyimide compounds) or the like.Because gelatinous layer 30 of the present invention does not need calking like the shim of prior art, therefore gelatinous layer 30 of the present invention can be selected the higher material of the coefficient of viscosity for use, can strengthen the waterproof effect of encapsulation module.Described gelatinous layer 30 can be liquid kenel (liqud form) or patch kenel (tape form), if the liquid kenel then can utilize methods such as coating, wire mark, spray printing to be fixed on this base plate for packaging 10; If the patch kenel then can utilize methods such as stickup to be fixed on this base plate for packaging 10.Carry out one precuring processing procedure (pre-cure process) afterwards again.
Next please refer to Fig. 6 B, utilize photographic camera to aim at and locate, semiconductor element 20 is fixed on the gelatinous layer 30 of base plate for packaging 10 first surface 10a.This semiconductor element 20 must be pressed on the gelatinous layer 30 really, and accompanies by one curing process (cure process) with its curing.Described semiconductor element 20 includes a plurality of metal gaskets 22, sticks on the gelatinous layer 30 of base plate for packaging 10 first surface 10a.
Next please refer to Fig. 6 C, carrying out Laser drill processing procedure (laser drilling process) before, at first carry out alignment procedure (alignment), can aim at each metal gasket 22 of described semiconductor element 20 really to guarantee follow-up Laser drill processing procedure.If base plate for packaging 10 is to adopt translucent material, then alignment procedure can utilize the second surface 10b shooting of photographic camera (CCD camera) by base plate for packaging 10; If base plate for packaging 10 is to adopt light tight material, then alignment procedure can utilize the second surface 10b shooting of x ray camera by base plate for packaging 10.Behind the position of utilization alignment procedure with each metal gasket 22 of definite described semiconductor element 20, utilize the Laser drill processing procedure base plate for packaging 10 to be holed by second surface 10b, all on this base plate for packaging 10, form a conductive plug through hole (viahole) 11 at each metal gasket 22, and make each conductive plug through hole 11 all can aim at its pairing metal gasket 22.This Laser drill processing procedure not only must run through this base plate for packaging 10 fully, also the gelatinous layer on the conductive plug via path 30 and thin metal layer and metal oxide layer on the metal gasket 22 must be removed, in the hope of reducing the resistance value of the metallic conduction plug that forms in the future.The diameter of described conductive plug through hole 11 is between 10 microns (micro-meter) are to 100 microns.
This Laser drill processing procedure can be selected the short-pulsed laser of any kenel for use, and moderately adjusts its energy, makes repeatedly the laser irradiation just this base plate for packaging 10 be run through fully.The advantage of way like this is to reduce boring procedure micro-fractures (micro-cracking) and must produces, and makes that the inner surface contour of conductive plug through hole 11 is more smooth.
Next please refer to Fig. 6 D, carry out cleaning processing procedure (cleaning process) earlier one, then utilize physical deposition method (physical vapor deposition; PVD), chemical vapor deposition method (chemical vapor deposition; CVD) or galvanoplastic form layer of metal layer 42 at the second surface 10b of described base plate for packaging 10, simultaneously each conductive plug through hole 11 is filled up and form a plurality of metallic conduction plugs 12, wherein each metallic conduction plug 12 and be connected to the metal gasket 22 of a semiconductor element 20.
Described cleaning processing procedure can be gas ions cleaning processing procedure (plasma cleaning process), chemical evapn cleaning processing procedure or chemical liquids cleaning processing procedure, be in order to dispose the second surface 10b that falls within base plate for packaging 10 go up with conductive plug through hole 11 in chip (comprising organic substance that is derived from gelatinous layer 30 and the inorganic matter that is derived from base plate for packaging 10) and pollutant (contamination).Described metal level 42 can be single copper layer, also can be multiple layer (compositelayer) structure of thin adhesion coatings (glue layer) such as Ti, W, TiN, TiW, TaN and copper layer.
In forming the processing procedure of metal level 42 and metallic conduction plug 12, also can be chosen on the first surface 10a of base plate for packaging 10 and the semiconductor element 20 and also form metal level 42, so just form the second embodiment of the present invention.This metal level 42 that is positioned at the first surface 10a of base plate for packaging 10 covers semiconductor element 20, can form an electromagnetic shielding to prevent electrostatic breakdown (ESD damage) semiconductor element 20, can strengthen heat sinking function, and can prevent the moisture invasion.
Next please refer to Fig. 6 E, utilize micro-photographing process (photo lithographic process) and etch process (etching process), second surface 10b in described base plate for packaging 10 forms metal connecting layer (interconnect layer) 40, it comprises a plurality of plain conductors 40a, a plurality of contact mat (landpads) 40b and plural conductive choker block (via pads) (is positioned at the conductive plug periphery, figure is too complicated rather, is not presented on the figure).Wherein each metallic conduction plug 12 all is connected to a described plain conductor 40a, and this metallic conduction plug 12 is connected to the metal contact pad 22 of its pairing semiconductor element 20; Described contact mat 40b is as the usefulness that contacts of this encapsulation module with other circuit boards or probe.
Wherein said micro-photographing process is to be coated with one deck photoresistance (photo resist) at the second surface 10b of described base plate for packaging 10 earlier, utilizes light shield (photo mask) to expose again, then uses developing technique to form the photoresistance pattern.This photoresistance pattern in ensuing etch process as rigid guard shield (hardmask).Described etch process is gas ions etching (plasma etching) technology or wet etching (wet etching) technology utilized, and sees through described photoresistance pattern metal level 42 is carried out etching, to form described metal connecting layer 40.
Next please refer to Fig. 6 F; at first utilize sprinkling (spray coating) or wire mark (screenprinting) technology on the second surface 10b of described base plate for packaging 10, to form one deck insulation film; utilize micro-photographing process (photo lithographic Process) and erosion this processing procedure (etching Process); second surface 10b in described base plate for packaging 10 goes up formation one insulating barrier (insulating layer) 50; it is called welding resisting layer (solder mask) again, is in order to protect described plain conductor 40a.
Because of but described insulation film is the sensitization material, so this micro-photographing process need not be coated with photoresistance in advance, can directly utilize light shield to expose, and just can form described insulating barrier 50 at the utilization etch process.Can carry out one curing process (cure process) at last again to strengthen described insulating barrier 50, the processing procedure of the encapsulation module of the disclosed semiconductor element of the present invention is promptly accused and is finished.
In addition, also can form a solder sphere (solder ball) 70 (please referring to Fig. 4) on each contact mat 40b, it is made up of the alloy of tin usually, can so just finish the processing procedure of third embodiment of the invention as the usefulness of welding.In addition, also can on each contact mat 40b, form organic oxidation-resistant film (organic anti-oxidation film), can protect described contact mat 40b to avoid oxidation.
The encapsulation module of the disclosed semiconductor element of the present invention and manufacturing method thereof thereof have following advantage:
1, the present invention must not make metal film under the projection (UBM) and projection (bump), can significantly reduce the cost of encapsulation procedure.
2, base plate for packaging of the present invention must not use multiple layer metal (4 layers or 6 layers) substrate, can significantly reduce the cost of encapsulation procedure.
3, semiconductor element of the present invention not palpiform become projection, the detection card (probe card) of therefore must use cost not higher electrical measurement can reduce the cost of electrical measurement.
4, the material approaching can be selected for use because of base plate for packaging of the present invention, its temperature cycles reliability (temperature-cycle reliability) can be significantly promoted with the thermal coefficient of expansion of semiconductor element.
5, the disclosed metal level of second embodiment of the invention, it is positioned on the first surface of this base plate for packaging and covers described semiconductor element and gelatinous layer, can form an electromagnetic shielding to prevent the electrostatic breakdown semiconductor element, can strengthen heat sinking function, and can prevent the moisture invasion.
6, because gelatinous layer of the present invention does not need calking like the shim of prior art, therefore gelatinous layer of the present invention can be selected the higher material of the coefficient of viscosity for use, can strengthen the blocks moisture effect of encapsulation module.
7, the lower material of thermal coefficient of expansion can be selected for use because of base plate for packaging of the present invention, the stability of its size can be significantly promoted.
8, the revealer of first embodiment of the present invention institute is LGA (land grid array) processing procedure, can convert PGA (pin grid array) processing procedure, CGA (column grid array) processing procedure BGA (ball grid array) processing procedure easily in addition.
9, can utilize known hyperplasia technology (build-up process) under the structure of encapsulation module of the present invention, second surface 10b at base plate for packaging 10 forms hyperplasia layer (build-up layer), has the semiconductor packages module of multiple layer metal conductive layer (multi-layer interconnect) with formation.
The above is to utilize preferred embodiment to describe the present invention in detail, but not limit the scope of the invention, and the personage who knows this skill also can understand, suitably does some little change and adjustment, will not lose main idea of the present invention place, also not break away from the spirit and scope of the present invention.
Claims (10)
1, a kind of encapsulation module of semiconductor element, it comprises:
One base plate for packaging, it comprises first surface and second surface; Described base plate for packaging more comprises a plurality of metallic conduction plugs that run through and connect its first surface and second surface;
Semiconductor element, it is positioned at the first surface of described base plate for packaging; This semiconductor element more includes a plurality of metal gaskets, and wherein each metal gasket all is connected to a described metallic conduction plug;
One metal connecting layer, it is positioned at the second surface of this base plate for packaging; Described metal connecting layer comprises a plurality of plain conductors and a plurality of contact mat, and wherein each metallic conduction plug all is connected to a described plain conductor.
2, the encapsulation module of semiconductor element according to claim 1 is characterized in that: described base plate for packaging is made up of the thermal coefficient of expansion insulation material close with described semiconductor element.
3, the encapsulation module of semiconductor element according to claim 1 is characterized in that: more comprise a gelatinous layer, it is positioned at the first surface of described base plate for packaging, in order to described base plate for packaging and semiconductor element is bonding; Described gelatinous layer has adherence, and its thermal coefficient of expansion is less than 15ppm/ ℃.
4, the encapsulation module of semiconductor element according to claim 1 is characterized in that: more comprise a metal level, it is positioned on the first surface of this base plate for packaging, and covers described semiconductor element.
5, the encapsulation module of semiconductor element according to claim 1 is characterized in that: more comprise an insulating barrier, it is positioned at the second surface of this base plate for packaging and covers described plain conductor.
6, the encapsulation module of semiconductor element according to claim 1 is characterized in that: more comprise a solder sphere on each described contact mat.
7, a kind of method that forms the encapsulation module of semiconductor element as claimed in claim 1, it comprises:
One base plate for packaging is provided, and it comprises first surface and second surface;
At least one semiconductor element is fixed on the first surface of described base plate for packaging, wherein this semiconductor element includes a plurality of metal gaskets;
Utilize the optical alignment machine to carry out alignment procedure, utilize the Laser drill processing procedure this base plate for packaging to be holed again, all on this base plate for packaging, form a conductive plug through hole at each metal gasket by second surface;
Form the layer of metal layer at the second surface of described base plate for packaging, simultaneously each conductive plug through hole is filled up and form a plurality of metallic conduction plugs, wherein each metallic conduction plug and be connected to a described metal gasket; And
Utilize little shadow and etch process to form metal connecting layer at the second surface of described base plate for packaging, it comprises a plurality of plain conductors and a plurality of contact mat.
8, the method for the encapsulation module of formation semiconductor element according to claim 7, it is characterized in that: the second surface that more is included in described base plate for packaging forms insulating barrier covering the step of described plain conductor, and the step that forms solder sphere on described contact mat.
9, the method for the encapsulation module of formation semiconductor element according to claim 7 is characterized in that: the first surface at described base plate for packaging forms the metal level that one deck covers described semiconductor element more simultaneously.
10, the method for the encapsulation module of formation semiconductor element according to claim 7, it is characterized in that: when the translucent material of described base plate for packaging system's employing, then described alignment procedure is to utilize photographic camera to be taken by the second surface of this base plate for packaging, when the light tight material of described base plate for packaging system's employing, then described alignment procedure is to utilize x ray camera to be taken by the second surface of this base plate for packaging.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02108448 CN1202573C (en) | 2002-03-29 | 2002-03-29 | Semiconductor component package module unit and programming method thereof |
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| CN 02108448 CN1202573C (en) | 2002-03-29 | 2002-03-29 | Semiconductor component package module unit and programming method thereof |
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| CN1202573C CN1202573C (en) | 2005-05-18 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097330B (en) * | 2009-12-11 | 2013-01-02 | 日月光半导体（上海）股份有限公司 | Conduction structure of encapsulation substrate and manufacturing method thereof |
| CN103200776A (en) * | 2013-04-19 | 2013-07-10 | 苏州光韵达光电科技有限公司 | Laser drilling method of ball grid array structure PCB (printed circuit board) |
| CN103688350A (en) * | 2011-02-23 | 2014-03-26 | 德克萨斯仪器股份有限公司 | Chip module embedded in PCB substrate |
| CN105428373A (en) * | 2015-12-31 | 2016-03-23 | 京东方科技集团股份有限公司 | Film-coated substrate for organic light emitting diode (OLED), method for preparing OLED display device by means of the OLED film-coated substrate, and OLED display device thereof |
| CN112505102A (en) * | 2019-09-16 | 2021-03-16 | 力成科技股份有限公司 | Method for measuring resistance of package substrate and package substrate thereof |
-
2002
- 2002-03-29 CN CN 02108448 patent/CN1202573C/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097330B (en) * | 2009-12-11 | 2013-01-02 | 日月光半导体（上海）股份有限公司 | Conduction structure of encapsulation substrate and manufacturing method thereof |
| CN103688350A (en) * | 2011-02-23 | 2014-03-26 | 德克萨斯仪器股份有限公司 | Chip module embedded in PCB substrate |
| CN103200776A (en) * | 2013-04-19 | 2013-07-10 | 苏州光韵达光电科技有限公司 | Laser drilling method of ball grid array structure PCB (printed circuit board) |
| CN105428373A (en) * | 2015-12-31 | 2016-03-23 | 京东方科技集团股份有限公司 | Film-coated substrate for organic light emitting diode (OLED), method for preparing OLED display device by means of the OLED film-coated substrate, and OLED display device thereof |
| WO2017114000A1 (en) * | 2015-12-31 | 2017-07-06 | 京东方科技集团股份有限公司 | Film-coated substrate for oled, method for preparing oled display device by using same, and oled display device |
| CN105428373B (en) * | 2015-12-31 | 2018-12-28 | 京东方科技集团股份有限公司 | OLED overlay film substrate, the method and OLED display device that OLED display device is prepared with it |
| CN112505102A (en) * | 2019-09-16 | 2021-03-16 | 力成科技股份有限公司 | Method for measuring resistance of package substrate and package substrate thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1202573C (en) | 2005-05-18 |
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