CN1368824A - Method and device for detecting full screen size using data enable signal - Google Patents

Abstract

The device for detecting the full screen size by the data enable signal can comprise a time sequence control device and a multi-channel conversion device, wherein the time sequence control device can comprise a plurality of input ends and a control signal end, each input end is coupled with a display bit, and the control signal end outputs a control signal. When correcting the image signal, the time sequence control device can feed the control signal into the multi-channel conversion device, so that the data enable signal is fed into the time sequence control device and the full screen size of the full frame is presented. After the picture is corrected, the time sequence control device changes the logic state of the control signal, so that the signal received by the time sequence control device is correct display bit data and presents a real picture image.

Description

Method and device for detecting full screen size using data enable signal

The invention relates to a method and device for detecting the full screen size of a display, in particular to a method and device for detecting the full screen size by using a data enabling signal.

In this era of information explosion and the vigorous development of the electronic industry, the source of people's knowledge is no longer limited to newspapers, magazines, TV broadcasts and other media. As long as they take the train of the Internet, they can get first-hand information from all over the world at any time. Information; just because of this, personal computers are also popularized in most families at an astonishing speed, and penetrate into everyone's daily life, making the development of the computer industry present a thriving scene. On the other hand, the vigorous development of the computer industry has also led to the improvement and innovation of imaging technology. Taking displays as an example, traditional cathode ray tube (CRT) displays have gradually faded out in recent years due to their large size and serious radiation. The market for high-end displays is replaced by liquid crystal displays (LCDs) that are low in radiation, low in power consumption, and thin and light. Therefore, LCDs have already become mainstream models in the high-end market and synonymous with high-end displays.

The screen of a monitor is composed of many pixels arranged, which means that each pixel is the most basic display unit. During image development, the display color and brightness of each pixel can be determined by the ratio of the three primary color signals corresponding to each pixel in the display signal, so as to present a complete image. Therefore, compared with a screen of the same size, if the number of pixels on the screen is more, it means that the area occupied by each pixel is smaller, and the picture that can be presented is more detailed. When judging the fineness of the picture, the resolution of the picture is often used as the basis for judgment. Generally speaking, the resolution refers to the number of pixels in each column (row) in the picture multiplied by each row (column). ), such as 800×600 or 1024×768, etc., the higher the resolution, the more detailed the picture presented. Since the current monitors all support display modes with multiple resolutions, although the number of pixels of the monitor is fixed, in different display modes, images with different resolutions can still be presented according to different display signals; In addition, the color level that each pixel can present is determined by the number of bits of each primary color signal among the three primary color signals. For example, each primary color signal can be composed of 8 bits or 6 bits, and the primary color signal composed of 8 bits has 256 (ie 2 ⁸ ) levels; while the primary color signal composed of 6 bits has only 64 levels. (that is, 2 ⁶ ) levels. Of course, the more bits used to represent the primary color signal, the richer the color, which means the higher the resolution of the color. It should be noted that the so-called three primary color signals here refer to the three primary color signals required for imaging. Taking the current display as an example, the combination of red signal, blue signal and green signal can be used for imaging. The colors required by the screen, and these three are collectively called the three primary color signals; of course, the three primary colors are not limited to the three colors of red, green, and blue, and any three color signals that can achieve the above functions can be used as the three primary color signals. In the following, the functions of each signal in the display signal will be described.

The image signal input to the digital display is generally a low-voltage differential coded signal, and the content of the coded signal includes digital signals of three primary colors, a horizontal synchronization signal Hs, a vertical synchronization signal Vs, a data enable signal DE, and a pixel clock CK. In Figure 1, since the display can only present digital images, the low-voltage differential encoding signal 102 includes signals such as Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+, RxC- and RxC+, and these signals must be transparent The digital display signal 104 can only be processed after the differential signal is received and decoded by the decoder 110 . Therefore, after receiving the low-voltage differential coded signal 102, the differential signal receiving decoder 110 can deconvert the low-voltage differential coded signal 102 and restore it to its original three-primary digital display signal 104 (RD, GD, and BD), horizontal synchronization signal Digital signals such as Hs, vertical synchronous signal Vs, data enable signal DE, and pixel clock CK. After the digital display signal 104 is fed into the proportional processor 130, the optimized output image can be obtained through processing procedures such as phase adjustment or interpolation calculation; since these adjustment methods are not the focus of the present invention, they will not be described in detail here The operation principle is described, and the horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, and the pixel clock CK in the display will be described below.

The unit of the horizontal synchronization signal Hs, the vertical synchronization signal Vs and the pixel clock CK is frequency. The pixel clock CK is the number of pixels that can display colors per second, which determines the length of time between a pixel displaying a color and the next pixel displaying a color. When the screen data is input to the display, the display starts to display colors from the pixels in the first column and the first row on the upper left, followed by the pixels in the first column and the second row, the pixels in the first column and the third row, ... .., until the pixels in the last row of the first column are displayed, then go back to the pixels in the first row of the second column to display the color, and then the pixels in the second row of the second column, ......, so that And so on, until the pixels in the last column and last row display a color. In this way, the colors displayed by each pixel can be pieced together to form the picture to be displayed. And when another screen data is input to the display, start again from the pixels in the first column and first row on the upper left, and determine the color to be displayed by each pixel in the same order, thus piecing together another screen. It should be noted that when the pixels in the last row of each column are displayed, the pixels in the first row of the next column are controlled by the horizontal synchronization signal Hs to display colors, so the horizontal synchronization signal Hs can determine the pixels that display colors per second The number of columns; and when the pixels of the last column and the last row of the screen are displayed, the vertical synchronization signal Vs controls the first pixel of the first column of the screen to display the color, so the vertical synchronization signal Vs can determine the picture displayed per second number. Due to the phenomenon of persistence of vision in the human eye, if the update speed of the display screen is high enough to a certain extent, the rapidly updated screen is not a fast flashing screen, but a continuous dynamic screen. Combination, that is, film. The speed at which different pictures are changed on the display screen is called the refresh rate (refresh rate), which is the frequency of the vertical synchronization signal Vs. At present, the picture update frequency of a general computer mainframe is above 60 Hz, that is, the display screen can display at least 60 picture data in one second. Hereinafter, the timing relationship among the horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, and the pixel clock CK will be described with reference to the figures.

Referring to FIG. 2A , it shows a schematic diagram of the timing relationship among the horizontal synchronous signal Hs, the vertical synchronous signal Vs, and the data enable signal DE. Taking the resolution of 1024×768 as an example, the horizontal synchronization signal Hs at this resolution may be 48.36 KHz, the vertical synchronization signal Vs may be 60 Hz, and the pixel clock CK may be 65 MHz. During image display, since each picture has 768 columns, the vertical synchronizing signal Vs is exchanged only once after the horizontal synchronizing signal Hs is exchanged 768 times, and 60 pictures can be exchanged in one second. On the other hand, the data enable signal DE can be used to indicate the actual length of the frame, that is, although the pixel clock CK is a signal with a fixed frequency, the result of sampling the display signal by the pixel clock CK can only be obtained by the data enable signal DE. In other words, the period of the data enabling signal DE is the actual length of each column of pictures, and since each picture has 1024 lines, the data enabling signal DE needs to display 1024 lines in one cycle. pixels, as shown in Figure 2B. Hereinafter, the relationship between the occurrence timing of the horizontal synchronous signal Hs, the vertical synchronous signal Vs, and the data enable signal DE and the display frame will be discussed.

Referring to FIG. 3 , it shows the corresponding relationship between the picture area and each signal. Assuming that the resolution of the screen 300 is 1024×768, it means that the length and width of the screen 300 have 1024 and 768 pixels respectively, since the color to be displayed by each pixel is sampled by the pixel clock CK to the display signal, so in In the picture 300, the pixels in each column correspond to 1024 pulses in the pixel clock CK; moreover, since the period of the data enable signal DE is the actual length of each column of picture, the period of the data enable signal DE is exactly the same as The periods of 1024 pixel clocks CK are the same, as shown in the figure. It should be noted that since the length of each column in the picture 300 is determined by the data enable signal DE, which is different from the period of the horizontal synchronization signal Hs, there will be a period of no picture at the beginning and end of the horizontal synchronization signal Hs. Areas are referred to as back porch and front porch; taking this figure as an example, the dotted line area on the left side of the picture 300 is the rear edge BPH of the horizontal synchronization signal Hs, and the dotted line area on the right side of the picture 300 is the horizontal The leading edge FPH of the sync signal Hs. Similarly, the vertical sync signal Vs also has front and rear edge regions. The dotted line area above the frame 300 is the rear edge BPV of the vertical sync signal Vs, and the dotted line area below the frame 300 is the front edge FPV of the vertical sync signal Vs. Incidentally, the names of the so-called front and rear edges here are the result of convention, which is not very important; what is important is what they represent, which is the area outside the screen that does not display signals. Such a concept is established rather than a name. Much more important.

Generally speaking, traditional monitors use the frequency and polarity of the horizontal and vertical synchronous signals in the input video signal to compare with the preset values of several video signals built in the monitor. When the frequency and polarity of the synchronous signal of the input video signal If it is the same as any preset value, the display will output the image adjustment data of the preset value to the screen, so as to adjust the image signal to the correct position of the screen. However, since there are so many types of display cards on the market today, even if the above comparison results are the same, it is possible that the timing of the front edge and rear edge of the video signal is different; if you still use the preset image adjustment data to correct the image at this time, it will be Incorrect adjustment occurs, so that the picture cannot be sent to the correct position on the screen, and there are situations such as picture offset or wrong number of pixels, which seriously affect the viewing quality.

Therefore, in order to correctly judge the timing of the front and rear edges of the image material, many control chips for detecting the front and rear edges have been developed, but the detection methods of these control chips are calculated based on the first colored pixel and the last colored pixel in the image signal; but When encountering a full-frame image signal or a black image that is not a full screen (the so-called black means no red, green, and blue colors, and the black image is pure DOS mode, etc.), it will be very difficult to detect the front and rear edge timings with this calculation method. Big question.

In view of this, the object of the present invention is to provide a method and device for detecting the full screen size by using the data enable signal, so that the full screen size can be accurately obtained no matter whether the input image data is full screen or has color.

According to the object of the present invention, a method and device for detecting the full screen size using a data enable signal are proposed.

The device for detecting the full screen size with the data enable signal may include a timing control device and a multiplexing device. The timing control device may include several input terminals and a control signal terminal, and each input terminal may be connected to a display of a color signal. The bits are coupled to present the color of each pixel; and the control signal terminal can output a control signal to determine whether to perform image correction. After the multiplexing device is coupled to the timing control device, according to the control signal fed from the control signal terminal, the data enabling signal can be selected to be fed into the timing control device to perform image correction work, or the display bit can be selected to be fed into the timing control device device to present real images.

To achieve the stated purpose, the present invention provides a method for detecting the full screen size using a data enable signal, which is used to detect the full screen size of a digital display signal, the digital display signal includes a primary color signal, and the primary color signal With m display bits, the method for detecting the full screen size by using the data enabling signal includes the following steps: providing the data enabling signal; and using the data enabling signal as the data of the nth display bit in the primary color signal, The full screen size is detected accordingly, wherein m and n are both integers greater than 0, and n is not greater than m.

The present invention also provides a device for detecting the full screen size by using the data enabling signal, which is used for detecting the full screen size of a digital display signal, the digital display signal includes a primary color signal, and the primary color signal has m display bits , the device for detecting the full screen size with the data enabling signal includes: a timing control device, the timing control device includes m input terminals and a control signal terminal, and the m input terminals are used to communicate with the m display positions coupled, and the control signal terminal is used to output a control signal; a multiplexing device, the multiplexing device is coupled to the timing control device, and the multiplexing device is connected to the data enabling signal and the primary color signal The nth display bit is coupled to feed the nth input terminal of the timing control device alternatively from the data enabling signal and the nth display bit of the primary color signal according to the control signal, wherein , both m and n are integers greater than 0, and n is not greater than m.

When correcting the image signal, the timing control device can feed the control signal into the multiplexing device, so that the data enabling signal can be fed into an input terminal, so that a full-frame full-screen size can be presented accordingly, and the calculated Front and rear edge timing and other related parameters to obtain the correct display screen size and position. After the image correction is completed, the timing control device can change the logic state of the control signal, so that the signal received by each input terminal is correct display bit data, so as to present a real image image.

In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

FIG. 1 shows a block diagram of a display.

FIG. 2A is a schematic diagram of the timing relationship among the horizontal synchronization signal, the vertical synchronization signal and the data enable signal.

FIG. 2B is a schematic diagram of the timing relationship between the data enable signal and the pixel clock in FIG. 2A .

FIG. 3 shows the corresponding relationship between the picture area and each signal.

FIG. 4A is a block diagram of a device for detecting full screen size using a data enable signal according to a preferred embodiment of the present invention.

FIG. 4B is a schematic diagram of the detailed structure of FIG. 4A .

The detection method and device of the full screen size provided by the present invention, when detecting the full screen size, use the data enable signal to replace one or more display bits in the digital display signal, and feed it into the timing control device for identification, to display full screen size. Since the data enable signal is a signal that appears only when the display signal actually appears in the horizontal and vertical synchronous signal timings, no matter whether the image signal is full frame or completely black, as long as the data enable signal replaces the digital display signal By displaying the bit and imaging according to it, you can accurately know the relevant parameters such as the size, position and resolution of the screen. It should be noted that although these methods of detecting the full screen size can be implemented at any time, because the image presented after replacing the display bit data with the data enable signal is not real, so after performing the relevant detection and image correction After waiting for work, the display of the original picture must be restored so as not to affect the viewing quality; therefore, in practice, a multiplexing device can be used to switch signals before and after correction, and its specific implementation will be described in detail in the preferred embodiment .

Referring to FIG. 4A , it shows a block diagram of a device for detecting full screen size using a data enable signal according to a preferred embodiment of the present invention. The timing control device 430 includes an input port Ri, an input port Gi, an input port Bi and a control signal terminal CT. The input port Ri is used to receive the red signal RD, the input port Gi is used to receive the green signal GD, and the input port Bi is used to receive the blue signal. Signal BD; when the three primary color signals are fed into the timing control device 430, the timing control device 430 can calculate relevant parameters such as screen size, position, front and rear edge timing, etc., for displaying images. The timing control device 430 here may be a timing control chip, such as a timing control chip with a model number of PW164-20R. It should be noted that if each of the three primary color signals is represented by m display bits, then each input port also has m input terminals corresponding to it; taking the 24-bit digital display signal as an example, the red signal RD, The green signal GD and the blue signal BD each have 8 display bits, so the input port Ri, the input port Gi, and the input port Bi also need 8 input ports, and each display bit corresponds to an input port one-to-one. The corresponding relationship between the display bit and each input terminal will be described in detail below with the accompanying drawings. It should be noted that in order to enable the data enable signal to replace the display bit to detect the full screen size, and switch back to the original display screen after the screen correction is completed, the multiplexing device 410 can be used to couple to the timing control The device 430 performs switching between the two signals according to the control signal Ctrl. This embodiment takes the switching between the display bits of the data enable signal DE and the red signal RD as an example, and its specific implementation will be described in detail below.

Referring to FIG. 4B , it shows a schematic diagram of the detailed structure of FIG. 4A . The red signal RD is composed of 8 display bits such as display bit RD0, display bit RD1, ..., display bit RD7, etc. Similarly, the green signal GD is composed of display bit GD0, display bit GD1, ..., display bit GD7, etc. 8 Composed of display bits, the blue signal BD is composed of 8 display bits such as display bit BD0, display bit BD1,..., display bit BD7, etc., and it can be clearly seen from the attached drawings that each display bit is related to the timing control An input end of each input port in the device 430 is coupled, for example, the display bit RD6 is coupled to the input end Ri6 of the input port Ri, the display bit GD7 is coupled to the input end Gi7 of the input port Gi, and so on. Please note that the signal connection method in Figure 4B is to use the data signal DE to replace the highest display bit RD7 of the red signal RD for full-screen size detection; of course, in terms of practice, the data signal DE can also be used to replace the red signal RD. The display bit can replace several display bits of the red signal RD at the same time, or replace one or more display bits of other primary color signals to achieve the same purpose as in this embodiment, and will not be described in detail here. Taking this figure as an example, when the digital display signal is fed into the timing control device 430, the control signal terminal CT of the timing control device 430 can feed the control signal Ctrl into the multiplexer 415 of the multiplexer 410, and the multiplexer 415 can be based on the logic state of the control signal Ctrl, for example, logic 1, and at the same time switch SW1 off (ie on) and switch SW2 on (ie off). display bits - display bit RD7 and fed to input Ri7. What is important is that even if the original video signal is not full-frame or completely black, after the data enable signal DE is fed into the input terminal Ri7, a full-frame full-screen size can be displayed accordingly. Then, by activating the calculation function of the timing control device 430 , related parameters such as front and rear edge timing can be calculated to obtain the correct size and position of the display screen, and the display module can display correct images accordingly.

After the picture correction is completed, the timing control device 430 can change the logic state of the control signal Ctrl, for example, make it logic 0, so that the multiplexer 415 can accordingly turn on (i.e. off) the switch SW1 and close the switch SW2 (that is, on), so that the 8th display bit of the red signal RD-display bit RD7 is fed into the input terminal Ri7 to present a real picture image; since the digital display signal has been corrected to the best correct geometric display state at this time, Therefore, the optimized imaging effect can be achieved.

Furthermore, when the input signal such as the horizontal synchronization signal, the vertical synchronization signal, or the polarity of the image signal changes, the timing control device 430 can also perform the above image correction procedure again to maintain the optimal image quality.

It should be noted that when the full screen size is detected in this way, the display bit replaced by the data enable signal DE is preferably the highest display bit of each primary color signal, such as display bit RD7 or display bit GD7 or display bit BD7, etc. , the reason is that the number of display bits used by different color resolutions is not the same, such as 24 bits or 18 bits, etc.; but no matter how many display bits are used, usually the highest display bit will be used, while the lower bit will be used. It may be discarded. If the display bit replaced by the data enable signal DE is not the highest display bit, the display bit may not be used in the image signal with lower color resolution, so the above-mentioned image correction cannot be achieved. the goal of. Therefore, in the case that the display can support multiple color resolutions, it is a more appropriate choice to suggest that the data enable signal DE be coupled to the highest display bit. Of course, the above-mentioned preferred embodiment is described by taking a color display as an example, but a monochrome display can also use the detection method and device provided by the present invention without departing from the spirit of the present invention.

The method and device for detecting the full screen size by using the data enable signal disclosed in the above-mentioned embodiments of the present invention can accurately detect the full size of the image signal even if the input image signal is not a full-frame full-screen image or a completely black image. Screen size, and get the best picture quality.

In summary, although the present invention has been disclosed above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make various modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the claims.

Claims (18)

1. A method for detecting the full screen size with a data enable signal, for detecting the full screen size of a digital display signal, the digital display signal includes a primary color signal, and the primary color signal has m display bits, the The method for using the data enable signal to detect the full screen size includes the following steps: providing the data enable signal; and The data enabling signal is used as the data of the nth display bit in the primary color signal to detect the full screen size, wherein m and n are both integers greater than 0, and n is not greater than m. 2. The method for detecting a full screen size using a data enable signal as claimed in claim 1, wherein the primary color signal is a red signal. 3. The method for detecting a full screen size using a data enable signal as claimed in claim 1, wherein the primary color signal is a green signal. 4. The method for detecting a full screen size using a data enable signal as claimed in claim 1, wherein the primary color signal is a blue signal. 5. The method for detecting a full screen size using a data enable signal as claimed in claim 1, wherein m is 8. 6. The method for detecting a full screen size using a data enable signal as claimed in claim 1, wherein n is 8. 7. The method for detecting a full screen size using a data enable signal as claimed in claim 1, wherein m is 6. 8. The method for detecting a full screen size using a data enable signal as claimed in claim 1, wherein n is 6. 9. A device for detecting the full screen size with a data enable signal, used for detecting the full screen size of a digital display signal, the digital display signal includes a primary color signal, and the primary color signal has m display bits, the Devices that use the data enable signal to detect full screen size include: A timing control device, the timing control device includes m input terminals and a control signal terminal, the m input terminals are used to couple with the m display bits, and the control signal terminal is used to output a control signal; A multiplexing device, the multiplexing device is coupled to the timing control device, and the multiplexing device is coupled to the data enabling signal and the nth display bit of the primary color signal, for automatically The data enable signal and the nth display bit of the primary color signal are alternatively fed to the nth input terminal of the timing control device, wherein m and n are both integers greater than 0, and n is not greater than m . 10. The device for detecting a full screen size using a data enable signal as claimed in claim 9, wherein the timing control device is a timing control chip. 11. The device for detecting a full screen size using a data enable signal as claimed in claim 10, wherein the timing control chip is a model of PW164-20R. 12. The device for detecting a full screen size using a data enable signal as claimed in claim 9, wherein the primary color signal is a red signal. 13. The device for detecting a full screen size using a data enable signal as claimed in claim 9, wherein the primary color signal is a green signal. 14. The device for detecting a full screen size using a data enable signal as claimed in claim 9, wherein the primary color signal is a blue signal. 15. The device for detecting a full screen size using a data enable signal as claimed in claim 9, wherein m is 8. 16. The device for detecting full screen size using a data enable signal as claimed in claim 15, wherein n is 8. 17. The device for detecting a full screen size using a data enable signal as claimed in claim 9, wherein m is 6. 18. The device for detecting a full screen size using a data enable signal as claimed in claim 17, wherein n is 6.

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