CN1365036A - Mainboard and computer system using elastic memory and double rate memory - Google Patents
Mainboard and computer system using elastic memory and double rate memory Download PDFInfo
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- CN1365036A CN1365036A CN 01120302 CN01120302A CN1365036A CN 1365036 A CN1365036 A CN 1365036A CN 01120302 CN01120302 CN 01120302 CN 01120302 A CN01120302 A CN 01120302A CN 1365036 A CN1365036 A CN 1365036A
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Abstract
The present invention relates to mainboard and computer system with elastic synchronous DRAM and double data rate DRAM. By means of setting voltage regulator and several terminal resistors in terminal circuit module, the present invention has decreased printed circuit board area and production cost of computer mainboard. When the double rate DRAM module is used, the terminal circuit module is inserted into memory module slot so as to provide terminal voltage and terminal resistor essential for double rate DRAM to access. When the double rate DRAM is used, the mainboard is needed to have differential clock signal. When the reference voltage output by the double rate DRAM is detected, the differential clock generator for the present invention is made to produce differential clock signal for the double rate DRAM module to use.
Description
Technical field
The present invention relates to a kind of personal computer system, but and be particularly related to motherboard and the computer system that a kind of personal computer system's elasticity is used the dynamic RAM of synchronous DRAM and Double Data Rate.
Background technology
Among the now general personal computer system, mainly be made up of motherboard, interface card and peripherals, wherein motherboard can be described as the heart of computer system.On motherboard, except central processing unit (Central Processing Unit is arranged, be called for short CPU), control chip group (chipset) and can be for outside the slot of mounting interface card, several memory banks that memory modules can be installed (memory module slot) are still arranged, they can be according to usefulness person's needs, the memory modules (memory module) of varying number is installed, and a memory modules is made up of several memory subassemblies.
Generally at the employed internal memory of personal computer, as synchronous dynamic RAM (synchronous dynamic random access memory, SDRAM), its operation rising edge of being in response to clock signal of system carries out the accessing operation control of data.And with storage operation in Double Data Rate (double data rate, following time of pattern DDR), the control of accessing operation that internal memory just can carry out data at the rising edge and the falling edge of clock signal of system, speed that so just can rapid memory.
The running difference of synchronous DRAM SDRAM and Double Data Rate dynamic RAM DDRAM is as follows: (1) SDRAM uses the normal clock signal, and DDRAM uses differential (differential) clock signal; (2) V of SDRAM
DD=3.3V, the V of DDRAM
DD=3.3V, V
DDQ=2.5V; (3) SDRAM does not need reference voltage, and DDRAM needs reference voltage, and its value is 1/2V
DDQ(4) data bus that SDRAM connect is general CMOS logic, and the data bus that DDRAM connect be the serial terminal logic (series stubterminated logic 2, STTL_2); (5) data bus that SDRAM connect does not need to use terminal voltage (terminated voltage, V
TT), and the data bus that DDRAM connect need use a V
TTTerminal voltage is to absorb reflection wave; (6) data bus that SDRAM connect does not need to use lifting resistance (pull-up resistor), and the data bus that DDRAM connect need use lifting resistance.DDRAM what be better than SDRAM then is its Double Data Rate.
Use at present the computing machine of DDRAM to be all the computing machine of higher price, for example webserver (server) or higher personal computer, the memory module slot major part that its motherboard provided is all only supported DDRAM.Or the employed control chip group of some motherboard (chip set) is supported two kinds of memory modules of SDRAM/DDRAM on the market, but motherboard can only select to support a kind of memory modules, for example sdram memory module or DDRAM memory modules.But because the data bus that the DDRAM memory modules is connect is serial terminal logic (STTL_2), therefore need provide the voltage regulator (voltage regulator) of VTT terminal voltage and a plurality of lifting resistance (pull up resistor) to absorb reflection wave, these parts all must be positioned on the motherboard.Even therefore control chip group is supported the SDRAM/DDRAM memory modules, also can only when producing, select a kind of production.Promptly support the motherboard of SDRAM, or support the motherboard of DDRAM, both can't share, and the function of control chip group can't be given full play to.When producing the motherboard of supporting DDRAM, need these parts such as voltage regulator and a plurality of lifting resistance are positioned on the motherboard.The area of the printed circuit board (PCB) of motherboard (PCB) will thereby increase, and causes the motherboard cost to increase.
Summary of the invention
In view of this, but the invention provides the motherboard that a kind of elasticity is used synchronous DRAM and Double Data Rate dynamic RAM, but allow user's elasticity use synchronous DRAM module and Double Data Rate dynamic RAM module.
But first purpose of the present invention is to propose the motherboard that a kind of elasticity is used synchronous DRAM Double Data Rate dynamic RAM, allows the user optionally select to use sdram memory module or DDRAM memory modules on a slice motherboard.
Second purpose of the present invention is to propose a kind of terminating circuit module, motherboard production firm can be positioned on the terminating circuit module by required voltage regulator and a plurality of lifting resistance of data bus when using the DDRAM memory modules, with the area of the printed circuit board (PCB) of saving motherboard.
The 3rd purpose of the present invention is to propose a kind of memory modules, and the pin of this memory modules for example is 184 lines, but is not limited to 184 lines.Allow memory modules production firm sdram memory can be positioned over the memory modules of former use DDRAM internal memory, make sdram memory also can be used in the motherboard of supporting 184 line memory module slots.
But a kind of elasticity disclosed in this invention is used the motherboard and the computer system of synchronous DRAM and Double Data Rate dynamic RAM, and it is summarized as follows; But a kind of elasticity is used the system of synchronous DRAM and Double Data Rate dynamic RAM, is that required voltage regulator and a plurality of lifting resistance is positioned on the terminating circuit module when using the DDRAM memory modules.When select using the DDRAM memory modules, at first the DDRAM memory modules is placed a plurality of memory module slots, in a back memory module slot of DDRAM memory modules, plug this terminating circuit module again.This moment, the reference voltage pin of DDRAM memory modules will produce a reference voltage level, this reference voltage level will be delivered to voltage detecting circuit, through producing a comparative result after relatively with reference voltage level, this comparative result will be sent to clock generator (clock generator) with required differential clock (differential clock) signal of generation DDRAM memory modules, and deliver to control chip group with the required coherent signal of notice control chip group generation DDRAM memory modules.The printed circuit board area of the motherboard of system will be dwindled, and make motherboard selectable use sdram memory module or DDRAM memory modules.
But a kind of elasticity of the present invention is used the motherboard of synchronous DRAM and Double Data Rate dynamic RAM, is provided with the control chip group of supporting two kinds of memory modules of SDRAM/DDRAM.And required voltage regulator and a plurality of lifting resistance of data bus is positioned on the terminating circuit module will use the DDRAM memory modules time, to save the printed circuit board area of motherboard.When using the sdram memory module, then need in all memory module slots, to plug the sdram memory module; When selecting to use the DDRAM memory modules, at first the DDRAM memory modules is placed among a plurality of memory module slots, in a back memory module slot of DDRAM memory modules, plug this terminating circuit module again.So can on a slice motherboard, select to use sdram memory module or DDRAM memory modules.
A kind of terminating circuit module of the present invention can be applicable to motherboard, and its motherboard has a plurality of memory module slots, and each memory module slot has a plurality of signal wires.This terminating circuit module comprises: printed circuit board (PCB) can be inserted in any one in a plurality of memory module slots, so that being electrically connected of terminating circuit module and a plurality of memory module slots to be provided; Voltage regulator is placed on the printed circuit board (PCB), in order to terminal voltage to be provided; And a plurality of terminal resistances, be placed on the printed circuit board (PCB), be coupled to voltage regulator, an end of terminal resistance is connected to signal wire, and the other end is connected to terminal voltage.Wherein a plurality of memory module slots are the memory module slots that meet JEDEC standard 184 wire gauge lattice or 224 wire gauge lattice.These memory module slots also comprise the reference voltage pin.When the terminating circuit module inserts in a plurality of memory module slots any one, voltage regulator will provide the reference voltage of the reference voltage level scope that meets SSTL_2 bus specification in the JEDEC standard to the reference voltage pin.
A kind of memory modules of the present invention can be applicable to motherboard.This motherboard has memory module slot, and this memory modules comprises: printed circuit board (PCB) can be inserted in the memory module slot; And a plurality of synchronous DRAMs, place on the printed circuit board (PCB).Wherein memory module slot is the memory module slot that meets JEDEC standard 184 wire gauge lattice or 224 wire gauge lattice.
Description of drawings
Fig. 1 is the arrangement of parts synoptic diagram of the computer main frame panel of known support DDRAM memory modules;
Fig. 2 is the arrangement of parts synoptic diagram of the present invention's computer main frame panel of supporting the SDRAM/DDRAM memory modules;
Fig. 3 is the arrangement of parts synoptic diagram that the present invention is positioned over voltage regulator and a plurality of terminal resistance the outer terminating circuit module of motherboard;
Fig. 4 is the arrangement of parts synoptic diagram that the present invention is positioned over SDRAM 184 line memory modules;
Fig. 5 is the block scheme of differential clock generating means of the present invention;
Fig. 6 A is that process of the present invention couples the block scheme that resistance activates the differential clock generating means;
Fig. 6 B is the block scheme that activates the differential clock generating means through jumper wire device of the present invention;
Fig. 7 A is process input/output end port of the present invention and couples the block scheme that resistance activates the differential clock generating means;
Fig. 7 B is the block scheme through input/output end port and jumper wire device activation differential clock generating means of the present invention.
Number in the figure is respectively:
100: known motherboard
The 101:CPU slot
102: control chip group
103: the differential clock generating means
104～107: memory module slot
108: voltage regulator
109: terminal resistance
110～111:ISA slot
112～114:PCI slot
200: motherboard of the present invention
The 201:CPU slot
202: control chip group
2021: input/output end port
203: the differential clock generating means
2031: voltage comparator
2032: clock generator
204～207: memory module slot
210～211:ISA slot
212～214:PCI slot
300: the terminating circuit module
301: printed circuit board (PCB)
400:184 line memory modules
401: printed circuit board (PCB)
402：SDRAM
701: CPU (central processing unit)
702: input/output end port
R1, R2, R3, R4: resistance
J1, J2: jumper wire device
Embodiment
Please refer to Fig. 1, is the arrangement of parts synoptic diagram of the computer main frame panel of known support DDRAM memory modules.Include on the computer main frame panel 100 of known support DDRAM memory modules: a CPU slot 101, a control chip group 102, a differential clock generating means 103, a plurality of memory module slot 104～107, a voltage regulator 108, a plurality of terminal resistance 109, a plurality of PCI slot 112～114 and a plurality of ISA slot 110～111.Wherein CPU slot 101 is for the slot that inserts CPU; Control chip group 102 is to support the control chip group of DDRAM memory modules; Differential clock generating means 103 is in order to produce the required differential clock signal of DDRAM memory modules; A plurality of memory module slots 104～107 are for placing a plurality of DDRAM memory modules; Voltage regulator 108 is used to supply the DDRAM data bus that memory modules is connect required terminal voltage; A plurality of terminal resistances 109 are in order to the electric wave of the data bus transmission line that absorbs the DDRAM memory modules and connect.A plurality of PCI slots 112～114 are for placing a plurality of pci interface cards; A plurality of ISA slots 110～111 are for placing a plurality of ISA interface cards.
Referring again to Fig. 1, this motherboard 100 is supported the DDRAM memory modules.Therefore a plurality of terminal resistances 109 and voltage regulator 108 are positioned on the printed circuit board (PCB) of motherboard 100, cause the area of printed circuit board (PCB) to increase.As shown in Figure 1, the length of its printed circuit board (PCB) is 20cm.And known motherboard 100 can only be supported the DDRAM memory modules, does not support the sdram memory module simultaneously.And present DDRAM memory modules price is than sdram memory module height.Cause the DDRAM memory modules only to be applicable to higher computer system, the webserver for example, and can't popularize.
Please refer to Fig. 2, is the arrangement of parts synoptic diagram of the present invention's motherboard of supporting the SDRAM/DDRAM memory modules.Motherboard 200 of the present invention comprises: a CPU slot 201, a control chip group 202, a differential clock generating means 203, a plurality of memory module slot 204～207, a plurality of PCI slot 212～214 and a plurality of ISA slot 210～211.Wherein the function of CPU slot 201, a plurality of memory module slot 204～207, a plurality of PCI slot 212～214 and a plurality of ISA slots 210～211 is described with above-mentioned Fig. 1.Control chip group 202 provides support and uses the ability of SDRAM and two kinds of memory modules of DDRAM.The user can be optionally and memory modules that decision will be used.The memory modules that differential clock generating means 203 will be looked use produces the required differential clock signal of use DDRAM memory modules or uses the required normal clock signal of SDRAM.The present invention is positioned over a plurality of terminal resistances 109 and voltage regulator 108 on the motherboard 200 terminating circuit module 300 outward.When selecting to use the DDRAM memory modules, again this terminating circuit module 300 is inserted in any one of a plurality of memory module slots 204～207.So can save the area of printed circuit board (PCB).As shown in Figure 2, the printed circuit board (PCB) contraction in length of motherboard 200 of the present invention is 19cm.
Please refer to Fig. 3, is the arrangement of parts synoptic diagram that the present invention is positioned over voltage regulator and a plurality of terminal resistance the outer terminating circuit module of motherboard.Terminating circuit module 300 of the present invention can be applicable in the motherboard 200.Its motherboard 200 has a plurality of memory module slots 204～207, and each memory module slot has a plurality of signal wires.This terminating circuit module 300 comprises: printed circuit board (PCB) 301 can insert in any one in a plurality of memory module slots 204～207, so that being electrically connected of terminating circuit module 300 and a plurality of memory module slots 204～207 to be provided; Voltage regulator 108 is placed on the printed circuit board (PCB) 301, in order to terminal voltage to be provided; And a plurality of terminal resistances 109, be placed on the printed circuit board (PCB) 301, be coupled to voltage regulator 108, an end of terminal resistance 109 is connected to signal wire, and the other end is connected to terminal voltage.Wherein a plurality of memory module slots 204～207th meet the 184 wire gauge lattice of JEDEC standard or the memory module slot of 224 wire gauge lattice.These memory module slots 204～207 also comprise the reference voltage pin.When terminating circuit module 300 inserts in a plurality of memory module slots 204～207 any one, voltage regulator 108 will provide the reference voltage of the reference voltage level scope that meets SSTL_2 bus specification in the JEDEC standard to the reference voltage pin.The value of this reference voltage for example is 1.25V.Right this reference voltage level is not limited to 1.25V.Those skilled in the art without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.
Please refer to Fig. 4, is the arrangement of parts synoptic diagram that the present invention is positioned over SDRAM 184 line memory modules.Memory modules 400 of the present invention can be applicable in the motherboard 200, and motherboard 200 has the memory module slot 204～207 of 184 lines, and this memory modules 400 comprises: printed circuit board (PCB) 401 can insert in the memory module slot 204～207; And a plurality of synchronous DRAMs 402, place on this printed circuit board (PCB) 401.Wherein memory module slot 400 meets the memory module slot of JEDEC standard 184 wire gauge lattice.Known 184 line memory modules only are applicable to DDRAM, so motherboard 200 is when supporting the DDRAM memory modules, and its memory bank 204～207 will only be supported the memory modules of 184 lines.And SDRAM 402 can only be placed on the memory modules of 168 lines.Therefore be to can't see the practice of on 184 line memory modules, placing SDRAM 402 on the market.The objective of the invention is SDRAM 402 is placed on the 184 line memory modules, make 184 line memory modules also can use SDRAM 402.Table one is depicted as the pin bitmap of 184 line DDRAM memory modules.The present invention is positioned over the practice of 184 line memory modules with SDRAM, is not that restriction the present invention only is applicable to 184 line memory modules, other for example the memory modules of 168 lines or 224 lines all be the scope that the present invention protected.
Table one: the pin bitmap of 184 line DDRAM memory modules
| ????Pin# | Name | ????Pin# | Name | ????Pin# | Name | ??Pin# | Name |
| ????1 | Vref | ????48 | A0 | ????94 | DQ4 | ??141 | A10 |
| ????2 | DQ0 | ????49 | CB2 | ????95 | DQ5 | ??142 | CB6 |
| ????3 | Vss | ????50 | Vss | ????96 | Vddq | ??143 | Vddq |
| ????4 | DQ1 | ????51 | CB3 | ????97 | DM0 | ??144 | CB7 |
| ????5 | DQS0 | ????52 | BA1 | ????98 | DQ6 | ??KEY | KEY |
| ????6 | DQ2 | ????KEY | KEY | ????99 | DQ7 | ??145 | Vss |
| ????7 | Vdd | ????53 | DQ32 | ????100 | Vss | ??146 | DQ36 |
| ????8 | DQ3 | ????54 | Vddq | ????101 | NC | ??147 | DQ37 |
| ????9 | NC | ????55 | DQ33 | ????102 | NC | ??148 | Vdd |
| ????10 | NC | ????56 | DQS4 | ????103 | A13 | ??149 | DM4 |
| ????11 | Vss | ????57 | DQ34 | ????104 | Vddq | ??150 | DQ38 |
| ????12 | DQ8 | ????58 | Vss | ????105 | DQ12 | ??151 | DQ39 |
| ????13 | DQ9 | ????59 | BA0 | ????106 | DQ13 | ??152 | Vss |
| ????14 | DQS1 | ????60 | DQ35 | ????107 | DM1 | ??153 | DQ44 |
| ????15 | Vddq | ????61 | DQ40 | ????108 | Vdd | ??154 | /RAS |
| ????16 | CK0 | ????62 | Vsdq | ????109 | DQ14 | ??155 | DQ45 |
| ????17 | /CK0 | ????63 | /WE | ????110 | DQ15 | ??156 | Vddq |
| ????18 | Vss | ????64 | DQ41 | ????111 | CKE1 | ??157 | /CS0 |
| ????19 | DQ10 | ????65 | /CAS | ????112 | Vddq | ??158 | /CS1 |
| ????20 | DQ11 | ????66 | Vss | ?113 | BA2 | ??159 | DM5 |
| ????21 | CKE0 | ????67 | DQS5 | ?114 | DQ20 | ??160 | Vss |
| ????22 | Vddq | ????68 | DQ42 | ?115 | A12 | ??161 | DQ46 |
| ????23 | DQ16 | ????69 | DQ43 | ?116 | Vss | ??162 | DQ47 |
| ????24 | DQ17 | ????70 | Vdd | ?117 | DQ21 | ??163 | Nc/cs3 |
| ????25 | DQS2 | ????71 | Nc/cs2 | ?118 | A11 | ??164 | Vddq |
| ????26 | Vss | ????72 | DQ48 | ?119 | DM2 | ??165 | DQ52 |
| ????27 | A9 | ????73 | DQ49 | ?120 | Vdd | ??166 | DQ53 |
| ????28 | DQ18 | ????74 | Vss | ?121 | DQ22 | ??167 | Nc，Feten |
| ????29 | A7 | ????75 | /CK2 | ?122 | A8 | ??168 | Vdd |
| ????30 | Vddq | ????76 | CK2 | ?123 | DQ23 | ??169 | DM6 |
| ????31 | DQ19 | ????77 | Vddq | ?124 | Vss | ??170 | DQ54 |
| ????32 | A5 | ????78 | DQS6 | ?125 | A6 | ??171 | DQ55 |
| ????33 | DQ24 | ????79 | DQ50 | ?126 | DQ28 | ??172 | Vddq |
| ????34 | Vss | ????80 | DQ51 | ?127 | DQ29 | ??173 | NC |
| ????35 | DQ25 | ????81 | Vss | ?128 | Vddq | ??174 | DQ60 |
| ????36 | DQS3 | ????82 | Vddid | ?129 | DM3 | ??175 | DQ61 |
| ????37 | A4 | ????83 | DQ56 | ?130 | A3 | ??176 | Vss |
| ????38 | Vdd | ????84 | DQ57 | ?131 | DQ30 | ??177 | DM3 |
| ????39 | DQ26 | ????85 | VDD | ?132 | Vss | ??178 | DQ62 |
| ????40 | DQ27 | ????86 | DQS7 | ?133 | DQ31 | ??179 | DQ63 |
| ????41 | A2 | ????87 | DQ58 | ?134 | CB4 | ??180 | Vddq |
| ????42 | Vss | ????88 | DQ59 | ?135 | CB5 | ??181 | SA0 |
| ????43 | A1 | ????89 | Vss | ?136 | Vddq | ??182 | SA1 |
| ????44 | CB0 | ????90 | WE | ?137 | CK1 | ??183 | SA2 |
| ????45 | CB1 | ????91 | SDA | ?138 | /CK1 | ??184 | Vss |
| ????46 | Vdd | ????92 | SCL | ?139 | Vss | ||
| ????47 | DQS8 | ????93 | Vss | ?140 | DM8 |
Please refer to Fig. 5, is the block scheme of a differential clock generating means of the present invention.Differential clock generating means 203 of the present invention is to be applied in the computer system, this computer system comprises: motherboard 200, it comprises: a plurality of memory module slots 204～207, each memory module slot comprise a reference voltage pin and a plurality of signal wire; Voltage comparator 2031 is coupled to the reference voltage pin position of a plurality of memory module slots 204～207, whether meets a reference voltage level in order to the voltage that detects on the reference voltage pin position; Clock generator 2032 is coupled to the output of this voltage comparator 2031; And control chip group 202, be coupled to the output terminal of voltage comparator 2031; And memory modules 400, insert in any one in those memory module slots 204～207.Memory modules 400 comprises: printed circuit board (PCB) 401; And a plurality of synchronous DRAMs 402, place on the printed circuit board (PCB) 401; When wherein the voltage on the voltage comparator 2031 detection reference voltage pin does not meet reference voltage level, make clock generator 2032 produce the normal clock signal, provide to memory modules 400, voltage comparator 2031 makes control chip group 202 operate in a normal data rate mode, so as to the data of access module 400.Through producing a comparative result with reference voltage level after relatively, this comparative result will be sent to clock generator 2032 to produce required differential clock signal bell CK+ and the CK-of DDRAM memory modules.And deliver to control chip group 202 with the required coherent signal of notice control chip group 202 generation DDRAM memory modules.This voltage comparator 2031 for example is an operational amplifier (OperationAmplifier, OP AMP).The implementation method of right this voltage comparator 2031 is not limited to operational amplifier.Those skilled in the art without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.So can produce required normal clock signal of sdram memory module or the required differential clock signal of DDRAM memory modules.Wherein a plurality of memory module slots 204～207 have for example 184 lines, but are not limited to 184 lines, and for example: the memory module slot that is 224 wire gauge lattice is also applicable to the present invention.
Please refer to Fig. 6 A, is that process of the present invention couples the block scheme that resistance activates the differential clock generating means.As shown in Figure 6A, but a kind of elasticity provided by the present invention is used the motherboard of synchronous DRAM and Double Data Rate dynamic RAM, comprise: a plurality of memory module slots (aforesaid 104～107), comprise a reference voltage pin on each memory module slot, those reference voltage pin are connected in parallel; One control chip group 202, this control chip group 202 has a memorymodel pin (not drawing among the figure), when this memorymodel pin is set, control chip group 202 operates in the Double Data Rate pattern, when the memorymodel pin was not set, control chip group 202 operated in the normal data rate mode; And clock generator 2032, be coupled to control chip group 202, when control chip group 202 operates in the Double Data Rate pattern, clock generator 2032 promptly produces differential clock signal CK+ and CK-, when control chip group 202 operated in the normal data rate mode, clock generator 2032 produced normal clock signal CK.Wherein the memorymodel pin can be connected to voltage source and is set by coupling a resistance R 1.But this memorymodel pin also can be connected to earth potential to set by resistance R 1.Those skilled in the art without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.Those memory module slots wherein for example are the memory module slot of the 184 wire gauge lattice that meet the JEDEC standard, and wherein this reference voltage level meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard; Or those memory module slots for example are the memory module slot of 224 wire gauge lattice.
Please refer to Fig. 6 B, is that process of the present invention couples the block scheme that resistance activates the differential clock generating means.But a kind of elasticity provided by the present invention uses the motherboard of synchronous DRAM and Double Data Rate dynamic RAM to comprise: a plurality of memory module slots (aforesaid 104～107), comprise a reference voltage pin on each memory module slot, those reference voltage pin are connected in parallel; One control chip group 202, this control chip group 202 has a memorymodel pin position (not drawing among the figure), when this memorymodel pin is set, control chip group 202 operates under the Double Data Rate pattern, when the memorymodel pin was not set, control chip group 202 operated under the normal data rate mode; And clock generator 2032, be coupled to control chip group 202, when control chip group 202 operates in the Double Data Rate pattern, clock generator 2032 promptly produces differential clock signal CK+ and CK-, when control chip group 202 operated in the normal data rate mode, clock generator 2032 promptly produced normal clock signal CK.Wherein the memorymodel pin can be by coupling jumper wire device J1 (jumper), and jumper wire device during by short circuit resistance in series R2 connect and be connected to voltage source and be set.As jumper wire device J1 during by short circuit, the memorymodel pin is connected to voltage source through resistance R 2, and the memorymodel pin is set.When jumper wire device J1 opened a way, the memorymodel pin was not set.But this memorymodel pin also can be connected to earth potential to set by jumper wire device J1 and resistance R 2.Those skilled in the art are not in breaking away from god of the present invention and scope, when being used for a variety of modifications and variations.
Please refer to Fig. 7 A, is process input/output end port of the present invention and the block scheme that couples resistance activation differential clock generating means.But the invention provides the motherboard that a kind of elasticity is used synchronous DRAM and Double Data Rate dynamic RAM, comprise: a plurality of memory module slots (aforesaid 104～107), comprise a reference voltage pin on each memory module slot, those reference voltage pin are connected in parallel; Central processing unit 701 (CPU); Control chip group 202 is coupled to central processing unit 701; Input/output end port 702 (I/O port) is coupled to control chip group 202, and input/output end port 702 has a memorymodel position (not drawing among the figure); And clock generator 2032, be coupled to control chip group 202, in order to produce differential clock signal and normal clock signal, either-or; When the memorymodel position is set, after process central processing unit 701 reads, even control chip group 202 operates in the Double Data Rate pattern, control chip group 202 is that clock generator 2032 produces differential clock signal CK+ and CK-then, when the memorymodel position is not set, even central processing unit 701 control chip group 202 operate in a normal data rate mode, control chip group is that clock generator 2032 produces normal clock signal CK then.Wherein the memorymodel position can be connected to voltage source and is set by coupling a resistance R 3.Right this memorymodel position also can be connected to earth potential to set by resistance R 3.Those skilled in the art, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Those memory module slots wherein for example are the memory module slot of the 184 wire gauge lattice that meet the JEDEC standard, and wherein this reference voltage level meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard.Or those memory module slots for example are the memory module slot of 224 wire gauge lattice.
Please refer to Fig. 7 B, is process input/output end port of the present invention and the block scheme that couples resistance activation differential clock generating means.But the invention provides the motherboard that a kind of elasticity is used synchronous DRAM and Double Data Rate dynamic RAM, comprise: a plurality of memory module slots (aforesaid 104～107), comprise a reference voltage pin on each memory module slot, those reference voltage pin are connected in parallel; Central processing unit 701 (CPU); Control chip group 202 is coupled to central processing unit 701; Input/output end port 702 (I/O port) is coupled to control chip group 202, and input/output end port 702 has a memorymodel position (not drawing among the figure); And clock generator 2032, be coupled to control chip group 202, in order to produce differential clock signal and normal clock signal, either-or; When the memorymodel position is set, after process central processing unit 701 reads, even control chip group 202 operates in the Double Data Rate pattern, control chip group 202 is that clock generator 2032 produces differential clock signal CK+ and CK-then, when the memorymodel position is not set, even central processing unit 701 control chip group 202 operate in a normal data rate mode, control chip group makes clock generator 2032 produce normal clock signal CK then.Wherein the memorymodel position can be by coupling jumper wire device J2, and jumper wire device resistance in series R2 and be connected to voltage source and be set during by short circuit.As jumper wire device J2 during by short circuit, the memorymodel position is connected to voltage source through resistance R 4, and the memorymodel position is set.When jumper wire device J2 opened a way, the memorymodel position was not set.Right this memorymodel position also can be connected to earth potential to set by jumper wire device J2 and resistance R 4.Those skilled in the art without departing from the spirit and scope of the present invention, can be used for a variety of modifications and variations.Those memory module slots wherein for example are the memory module slot of the 84 wire gauge lattice that meet the JEDEC standard, and wherein this reference voltage level meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard.Or those memory module slots for example are the memory module slot of 224 wire gauge lattice.
In sum, but a kind of elasticity of the present invention uses the motherboard and the computer system of synchronous DRAM and Double Data Rate dynamic RAM to compare with known technology, has following advantage and effect at least:
But use the motherboard and the computer system of synchronous DRAM and Double Data Rate dynamic RAM according to elasticity of the present invention, but allow user's elasticity use synchronous DRAM module and Double Data Rate dynamic RAM module.
According to terminating circuit module of the present invention, allow motherboard production firm can use required voltage regulator and a plurality of lifting resistance of DDRAM memory modules to be positioned on the terminating circuit module, with the area of the printed circuit board (PCB) of saving motherboard.
According to a kind of 184 line memory modules of the present invention, allow memory modules production firm sdram memory can be positioned over 184 line memory modules of former use DDRAM internal memory, make sdram memory also can be used in the motherboard of supporting 184 line memory module slots.
In sum; though the present invention with preferred embodiment openly as above; but it is not in order to limit the present invention; any personnel that are familiar with this technology; various changes and the retouching done without departing from the spirit and scope of the present invention; all do not break away from protection scope of the present invention, and protection scope of the present invention should be with being as the criterion that claims were limited.
Claims (18)
1. but an elasticity is used the motherboard of synchronous DRAM and Double Data Rate dynamic RAM, it is characterized in that: comprising:
A plurality of memory module slots comprise a reference voltage pin on each memory module slot, those reference voltage pin are connected in parallel;
One voltage comparator is coupled to those reference voltage pin of those memory module slots, whether meets a reference voltage level in order to the voltage that detects on those reference voltage pin;
One clock generator is coupled to the output terminal of this voltage comparator, when meeting this reference voltage level, produces a differential clock signal, when not meeting this reference voltage level, produces a normal clock signal;
One control chip group is coupled to the output terminal of this voltage comparator, and when meeting this reference voltage level, this control chip group operates in a pair of haplotype data rate mode, and when not meeting this reference voltage level, this control chip group operates in a normal data rate mode.
2. motherboard according to claim 1, it is characterized in that: those memory module slots are the memory module slots that meet 184 wire gauge lattice of JEDEC standard, and wherein this reference voltage level meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard.
3. motherboard according to claim 1 is characterized in that: those memory module slots are memory module slots of 224 wire gauge lattice.
4. but an elasticity is used the motherboard of synchronous DRAM and Double Data Rate dynamic RAM, it is characterized in that: comprising:
A plurality of memory module slots comprise a reference voltage pin on each memory module slot, those reference voltage pin are connected in parallel;
One control chip group, this control chip group has a memorymodel pin, and when this memorymodel pin was set, this control chip group operated in a pair of haplotype data rate mode, when this memorymodel pin was not set, this control chip group operated in a normal data rate mode;
One clock generator, be coupled to this control chip group, when this control chip group operated in this Double Data Rate pattern, this clock generator promptly produced a differential clock signal, when this control chip group operated in this normal data rate mode, this clock generator promptly produced a normal clock signal.
5. motherboard according to claim 4, it is characterized in that: those memory module slots are the memory module slots that meet 184 wire gauge lattice of JEDEC standard, and wherein this reference voltage level meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard.
6. motherboard according to claim 4 is characterized in that: those memory module slots are memory module slots of 224 wire gauge lattice.
7. but an elasticity is used the motherboard of synchronous DRAM and Double Data Rate dynamic RAM, it is characterized in that: comprising:
A plurality of memory module slots comprise a reference voltage pin on each memory module slot, those reference voltage pin are connected in parallel;
One central processing unit;
One control chip group is coupled to this central processing unit;
One input/output end port is coupled to this control chip group, and this input/output end port has a memorymodel position;
One clock generator is coupled to this control chip group, in order to produce a differential clock signal and a normal clock signal, either-or;
8. motherboard according to claim 7 is characterized in that: this memorymodel position is set through coupling a resistance.
9. motherboard according to claim 7, it is characterized in that: those memory module slots are the memory module slots that meet 84 wire gauge lattice of JEDEC standard, and wherein this reference voltage level meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard.
10. motherboard according to claim 7 is characterized in that: those memory module slots are memory module slots of 224 wire gauge lattice.
11. a terminating circuit module can be applicable to a motherboard, this motherboard has a plurality of memory module slots, and each memory module slot has a plurality of signal wires, it is characterized in that: this terminating circuit module comprises:
One printed circuit board (PCB) can insert in any one in those memory module slots, so that being electrically connected of this terminating circuit module and those memory module slots to be provided;
One voltage regulator is placed on this printed circuit board (PCB), in order to a terminal voltage to be provided;
A plurality of terminal resistances are placed on this printed circuit board (PCB), are coupled to this voltage regulator, and those terminal resistance one ends are connected to those signal wires, and the other end is connected to this terminal voltage.
12. terminating circuit module according to claim 11, it is characterized in that: those memory module slots are the memory module slots that meet 184 wire gauge lattice of JEDEC standard, those memory module slots also comprise a reference voltage pin, when this terminating circuit module inserts in those memory module slots any one, this voltage regulator provides a reference voltage to this reference voltage pin, and wherein this reference voltage meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard.
13. terminating circuit module according to claim 11, it is characterized in that: those memory module slots are memory module slots of 224 wire gauge lattice, those memory module slots also comprise a reference voltage pin, when this terminating circuit module inserted in those memory module slots any one, this voltage regulator provided a reference voltage to this reference voltage pin.
14. a computer system is characterized in that: comprising:
One motherboard, it comprises: a plurality of memory module slots comprise a reference voltage pin and a plurality of signal wire on each memory module slot; One voltage comparator is coupled to this reference voltage pin of those memory module slots, whether meets a reference voltage level in order to the voltage that detects on this reference voltage pin position; One clock generator is coupled to the output terminal of this voltage comparator; One control chip group is coupled to the output terminal of this voltage comparator;
One terminating circuit module inserts in any one in those memory module slots, and this terminating circuit module comprises: a printed circuit board (PCB), in order to being electrically connected of this terminating circuit module and those memory module slots to be provided; One voltage regulator is placed on this printed circuit board (PCB), in order to provide a reference voltage to this a reference voltage pin and a terminal voltage; A plurality of terminal resistances are placed on this printed circuit board (PCB), are coupled to this voltage regulator, and those terminal resistance one ends are connected to those signal wires, and the other end is connected to this terminal voltage;
One memory modules inserts in any one in those memory module slots, and this memory modules comprises a plurality of Double Data Rate dynamic RAMs;
15. computer system according to claim 14, it is characterized in that: those memory module slots are the memory module slots that meet 184 wire gauge lattice of JEDEC standard, and wherein this reference voltage level meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard.
16. computer system according to claim 14 is characterized in that: those memory module slots are memory module slots of 224 wire gauge lattice.
17. a computer system is characterized in that: comprising:
One motherboard, it comprises: a plurality of memory module slots, each memory module slot have 184 pin positions, and comprise a reference voltage pin and a plurality of signal wire; One voltage comparator is coupled to this reference voltage pin of those memory module slots, whether meets a reference voltage level in order to the voltage that detects on this reference voltage pin; One clock generator is coupled to the output of this voltage comparator; One control chip group is coupled to the output terminal of this voltage comparator;
One memory modules inserts in any one in those memory module slots, and this memory modules comprises: a printed circuit board (PCB); A plurality of synchronous DRAMs place on this printed circuit board (PCB);
18. computer system according to claim 17, it is characterized in that: those memory module slots are the memory module slots that meet 184 wire gauge lattice of JEDEC standard, and wherein this reference voltage level meets the reference voltage level scope of SSTL_2 bus specification in the JEDEC standard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011203021A CN1192296C (en) | 2001-07-10 | 2001-07-10 | Mainboard and computer system using elastic memory and double rate memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011203021A CN1192296C (en) | 2001-07-10 | 2001-07-10 | Mainboard and computer system using elastic memory and double rate memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1365036A true CN1365036A (en) | 2002-08-21 |
| CN1192296C CN1192296C (en) | 2005-03-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011203021A Expired - Lifetime CN1192296C (en) | 2001-07-10 | 2001-07-10 | Mainboard and computer system using elastic memory and double rate memory |
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| CN (1) | CN1192296C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101489124B (en) * | 2008-12-31 | 2011-04-27 | 深圳裕达富电子有限公司 | Synchronous dynamic memory using method |
| CN102135931A (en) * | 2010-01-25 | 2011-07-27 | 英业达股份有限公司 | Passive back plane testing module and passive back plane testing method thereof |
| CN101459389B (en) * | 2007-12-14 | 2012-09-19 | 鸿富锦精密工业（深圳）有限公司 | Host board voltage regulating circuit |
-
2001
- 2001-07-10 CN CNB011203021A patent/CN1192296C/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101459389B (en) * | 2007-12-14 | 2012-09-19 | 鸿富锦精密工业（深圳）有限公司 | Host board voltage regulating circuit |
| CN101489124B (en) * | 2008-12-31 | 2011-04-27 | 深圳裕达富电子有限公司 | Synchronous dynamic memory using method |
| CN102135931A (en) * | 2010-01-25 | 2011-07-27 | 英业达股份有限公司 | Passive back plane testing module and passive back plane testing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1192296C (en) | 2005-03-09 |
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