CN1362822A - High speed routing search system based on content addressable memory - Google Patents
High speed routing search system based on content addressable memory Download PDFInfo
- Publication number
- CN1362822A CN1362822A CN 02100458 CN02100458A CN1362822A CN 1362822 A CN1362822 A CN 1362822A CN 02100458 CN02100458 CN 02100458 CN 02100458 A CN02100458 A CN 02100458A CN 1362822 A CN1362822 A CN 1362822A
- Authority
- CN
- China
- Prior art keywords
- route
- coprocessor
- address
- addressable memory
- route querying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 43
- 230000003068 static effect Effects 0.000 claims abstract description 12
- 230000001360 synchronised effect Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 description 20
- 238000012545 processing Methods 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
Images
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
The seek system comprises route seeking coprocessor, drive circuit, content-addressable memory and synchronous static memory. The route seeking coprocessor is a programmable chip, the content-addressable memory is connected with seeking coprocessor by means of drive circuit, and controlled by it. Said synchronous static memory is connected with route seeking coprocessor, and the reading and writing of the synchronous static memory is controlled by seeking coprocessor. Its maximum seeking rate can be up to 50 MPPS. Its maximum capacity can support 25K rate table entries, and can be expanded to 1 M route table entries, it can make real time refresh, and can be applicable to IPv6 by utiting simple equipment.
Description
Technical field
The present invention relates to the high speed route lookup system of a content-based addressable register (hereinafter to be referred as CAM), belong to networking technology area.
Background technology
Router is a network interconnection device, generally has two or more port, and each port all links to each other with other router or a network.The effect of router is the Internet Protocol (InternetProtocol that comes in from certain port wherein, hereinafter to be referred as IP) packet forwards from other port, the foundation of this forwarding is the purpose IP address of IP bag, and can obtain the forwarding information of purpose IP address from the result of Routing Protocol operation, these information are formed routing table with the format management and the storage of a rule route.
Route querying be in router according to the destination address of IP bag, search routing table, obtain the process of the forwarding information of this IP bag, wherein forwarding information is that the dynamic refresh as a result of Routing Protocol operation is in routing table.Therefore a route querying system comprises high speed route lookup and real-time route refresh function in high speed router.
In realization in the past, the route querying system in the high speed router generally realizes by following method:
A, directly control static memory (hereinafter to be referred as SRAM) by hardware and realize.
B, directly control dynamic memory (hereinafter to be referred as DRAM) by hardware and realize.(referring to Pankaj Gupta, Linand N.McKeown " Routing Lookups in Hardware at Memory Access Speeds ", Proc, IEEE INFOCOM ' 98 Apr.1998.)
Directly control SRAM realization route querying by hardware and generally can not support big routing table, and will deposit routing table by compression algorithm, refreshing of route is complicated more, will rebuild whole routing table sometimes.
The method of directly controlling DRAM with hardware mostly is direct high 24 storage addresss as DRAM according to the IP address, because most route prefix length is all smaller or equal to 24, so the route querying for the overwhelming majority only needs the primary memory visit just can obtain the result, but also there is following shortcoming in it:
1, because the memory access time of DRAM limits, the maximum of the method is searched speed can only reach 20,000,000 bag/seconds (MPPS).
2, owing to length will be become 24 less than 24 Prefix Expansion, so route refresh process more complicated can not refresh routing table in real time.
3, under the situation of using a DRAM, refreshing to influence route querying, and route querying speed is descended, and postpones to become big.
4, can not be applied directly in the Internet Protocol next generation IPv6 route querying.
Summary of the invention
In order to solve shortcomings such as route querying speed is low in the prior art, process is complicated, range of application is little, the present invention proposes a kind of high speed route lookup system of content-based addressable memory, search speed with raising, enlarge routing list capacity, and can realize refreshing in real time, reduce to search delay, enlarge the scope of application.
The route querying system of the content-based addressable memory that the present invention proposes comprises the route querying coprocessor, drive circuit, Content Addressable Memory and synchronous static memory.Route querying coprocessor wherein is a programmable chip, Content Addressable Memory links to each other with the route querying coprocessor by drive circuit, and the control of reception route querying coprocessor, synchronous static memory links to each other with the route querying coprocessor, reading and writing by route querying coprocessor control synchronous static memory.
The route querying system of the content-based addressable memory that the present invention proposes has the following advantages:
Two-forty: maximum is searched speed can reach 50,000,000 bag/seconds (MPPS), guarantees that it is Smin that minimum is searched speed.
Big capacity: can support the 256K route table items, and can expand to the 1M route table items.
Refresh in real time: guarantee that per second has the order of U bar route refresh to be performed.
Little delay: what guarantee maximum searches time-delay less than Dmax.
Support IPv6: go for IPv6 by simple setting.
Wherein Smin, Dmax are relevant and adjustable with U.
Native system can carry out two-forty in a word, and the low route querying that postpones is carried out real-time routing table and refreshed, and supports big capacity routing table, and supports the route querying of IPv6.
Description of drawings:
Fig. 1 is the structured flowchart of system of the present invention;
Fig. 2 is the cut-away view of route querying coprocessor in the system of the present invention;
Fig. 3 is the sequential chart of purpose IP address receiving interface in the route querying coprocessor;
Fig. 4 is the sequential chart of routing forwarding information transmission interface in the route querying coprocessor;
Fig. 5 is the sequential chart of central processing unit (CPU) interface in the route querying coprocessor.
Embodiment
Fig. 1 is the structured flowchart of high speed route lookup of the present invention system, and it is made up of following four parts:
The route querying coprocessor, it is a field programmable gate array (FPGA) chip, it is a core part of the present invention, it is the control centre of whole system, it provides three interfaces to the outside: wherein A is central processing unit (CPU) interface, B is a purpose IP address receiving interface, and C is the forwarding information transmission interface.It receives the destination address of IP bag by purpose IP address receiving interface, receive the route refresh order that Routing Protocol is sent by central processing unit (CPU) interface, control content addressable memory (CAM) and synchronous static memory (SSRAM) carry out route refresh and search, and send forwarding information by the forwarding information transmission interface then.
Content Addressable Memory (CAM), the Content Addressable Memory bar (CAMmodule) of use Lara Technology company is the inserting slot construction that 45 degree or 90 degree tilt.Can use two Content Addressable Memory bars (CAMModule) at most, deposit route prefix in the Content Addressable Memory (CAM), comprise IP address and mask.
Synchronous static memory (SSRAM) cooperates Content Addressable Memory (CAM) to use, and is used to deposit the port of routing forwarding information such as the transmission of IP bag, next-hop ip address etc.;
The 74xx16245 device of drive circuit use+3.3v power supply.Because the route querying coprocessor will drive all chips in the Content Addressable Memory bar (CAM module), when using two Content Addressable Memory bars (CAMmodule), drive 16 chips, by the driving force of this drive circuit increase signal, the route querying coprocessor is wanted the direction of control Driver Circuit when read-write Content Addressable Memory (CAM).
Introduce the content of the present invention and the course of work in detail below in conjunction with accompanying drawing.
Relate to three processing procedures among the present invention: initialization procedure, the routing table refresh process, the route querying process is introduced these three processes below respectively in conjunction with the accompanying drawings.
Initialization procedure:
Need an initialization procedure before route querying of the present invention system operate as normal, external system will be finished this initialization procedure by central processing unit (CPU) interface when using native system, and at first, external system will provide reset signal; Then, be 3 the unit parameter of writing dynamic dispatching algorithm (meaning of the address location that the central processing unit interface is involved, and the meaning of the used parameter of dynamic dispatching algorithm is in the aft section introduction of this specification) to the address; At last, external system is by being that 2 unit is write Config instruction (meaning of the address location that the central processing unit interface is involved and used command format are in the aft section introduction of this specification) and disposed CAM to the address.Whole like this initialization procedure finishes.When the central processing unit interface writes data, must follow sequential shown in Figure 5.
The route refresh process:
External system sends route refresh order by central processing unit (CPU) interface to the route querying coprocessor according to route.It is Unit 1 that external system is read the address earlier, if the value of reading is 0, write address is that the route refresh instruction is write in 2 unit, and these instructions comprise Fill, Delete, Mov; If the value of reading is non-0, then can not write these orders (meaning of the address location that the central processing unit interface is involved and used command format are introduced in the back of this specification).Fig. 2 is the cut-away view of route querying coprocessor in the system, therefrom as can be seen the route querying coprocessor in the process of receiving the laggard line operate of above-mentioned instruction: after the central processing unit interface module is receiving the route refresh order, by command processing module these orders are handled, the route refresh order is divided into the microcommand that directly to carry out, be put in the buffering area, if scheduler module has been selected the refresh command execution, then these microcommands are launched into CAM interface module and SSRAM interface module by transmitter module, the CAM interface module is by the read-write of drive circuit control CAM, refreshing routing table finished in the read-write of SSRAM interface module control SSRAM.
The route querying process:
External system sends purpose IP address by purpose IP address receiving interface module to the route querying coprocessor, the course of work of this module as shown in Figure 3, external system provides the clock CLK that transmits purpose IP address for the route querying coprocessor, at the FULL signal when low, external system can send purpose IP address to the route querying coprocessor, external system is sent into a purpose IP address by the TEN signal being put high expression, this IP address is exactly 32 bit data that the DATA bus transmits, the route querying coprocessor can be gathered this data according to clock CLK, by sequential chart as can be known, a plurality of purpose IP address can be transmitted continuously.
As shown in Figure 2, after purpose IP address receiving interface module receives purpose IP address, this purpose IP address can be put in the buffering area, having a plurality of purpose IP address buffer is buffered, if scheduler module selects search operation to carry out, then these purposes IP address is sent to transmitter module, transmitter module transfers them to the CAM interface module, the CAM interface module is carried out the streamline search operation by drive circuit control CAM, CAM can return an address and give the route querying coprocessor, the CAM interface module receives this address, and it is sent to the SSRAM interface module, SSRAM interface module control SSRAM carries out read operation, and the data of returning (forwarding information) are delivered to forwarding information transmission interface module.
Forwarding information transmission interface module sends forwarding information according to sequential shown in Figure 4 after receiving the forwarding information that the SSRAM interface module is sent.Forwarding information transmission interface module is sent a clock CLK to external system, when the transmission forwarding information, the TEN signal is put height, simultaneously forwarding information is put on the DATA bus, finishes the forwarding information process of transmitting, same routing forwarding information also can continuous being sent out away.
Below introduce the meaning and the used command format of the involved address location of central processing unit (CPU) interface:
Finish whole configuration of searching system by central processing unit (CPU) interface, the initialization of routing table and real-time route refresh are new.Some status registers, command register and other interface are arranged in coprocessor inside, and their address is as shown in the table.
| The address | Purposes | Read-write |
| 0 | Keep. | Can read and write |
| 1 | Status register when writing refresh command, is read this address earlier at every turn, if be 0, expression can be write, otherwise, can not send refresh command. | Read-only |
| 2 | The refresh command Input Address. | Only write |
| 3 | Command register, the parameter of dynamic dispatching algorithm. | Can read and write |
Native system provides with instruction type for upper layer software (applications) provides the route refresh interface, comprises Fill, Delete, and Mov, the Config four instructions, external system is that 2 unit sends refresh command to native system by write address, provides used command format below.Order 1 Fill to add a route
Fill adds a route in routing table, the length of this instruction is 128, and external system is that 2 unit sends this route refresh instruction by twice write address.
| ??OPCODE(0000) | ADDR (20) | NextHopIP (32) | PortNo (8) |
| IPAddress (32) | Mask (32) | ||
OPCODE is the command code of instruction, is 0000.
ADDR is the address of route in routing table that will add.
NextHopIP is next bar IP address of the route that will add.
PortNo is the forwarding port numbers of the route that will add.
IPAddress is the prefix of the route that will add.
Mask is the mask of the route that will add.
Order 2 Delete: delete a route.
A route table items of assigned address in this instruction deletion routing table.
OPC
| OPCODE(0001) | ADDR (20) | Keep |
ODE is the command code of instruction, is 0001.
ADDR is the address of route in routing table that will delete.
Other position keeps, and is nonsensical.
Order 3 Mov: mobile routing command
The list item that address bit S_ADDR in the routing table is begun moves to the list item that D_ADDR begins, and mobile route bar number is LENGTH.
| OPCODE(0011) | S_ADDR (20) | D_ADDR (20) | LENGTH (20) |
The command code of OP CODE instruction is 0011.
The source address of the piece that S_ADDR will move, 20 of data widths.
The destination address of the piece that D_ADDR will move, 20 of data widths.
The length of the piece that LENGTH will move, the number of the list item that is comprised in the piece just, 20 of data widths.
Order 4 Config deploy content addressable memories (CAM)
This order designs at Content Addressable Memory (CAM), different with common memory, at the register that Content Addressable Memory (CAM) inside has some to be configured, this order is used for the initialization procedure of Content Addressable Memory (CAM).The form of order is as follows:
| OPCODE(0100) | ADDR (20) | ????CONFIG_DATA | |
| CONFIG_DATA (68) | |||
The command code of OPCODE instruction is 0100.
The Content Addressable Memory that ADDR will dispose (CAM) register address, 20 of data widths.
CONFIG_DATA writes the content of register, 68 of data widths, wherein second 64 of instruction be the high 64 of CONFIG_DATA, first 64 be hang down 4 of CONFIG_DATA.
The explanation of the dispatching algorithm parameter that when using system of the present invention, relates to:
Among the present invention at route querying with the conflict relationship between refreshing, used a kind of dynamic dispatching strategy, the mutual exclusion that guarantees route querying and route refresh is carried out, lowest performance and maximum delay that assurance is simultaneously searched, the dynamic dispatching strategy has a parameter A, can be that 3 register disposes realization by central processing unit (CPU) interface write address.One embodiment of the present of invention are arranged to 100K to this value, this moment is for the port of 2.5 gigabit/sec (Gb/s), minimum is searched the maximum Bao Su of speed Smin greater than port, and maximum to search time-delay Dmax be 1.1 microseconds, and it is 100K that the route refresh order bar that per second is carried out is counted U.For the port of 10 gigabit/sec (Gb/s), Smin is greater than the maximum Bao Su of port, and Dmax is 1.4us, and U is 100K.
Claims (1)
1, a kind of route querying system of content-based addressable memory is characterized in that this system of searching comprises route querying coprocessor, drive circuit, Content Addressable Memory and synchronous static memory; Described route querying coprocessor is a programmable chip, described Content Addressable Memory links to each other with the route querying coprocessor by drive circuit, and the control of reception route querying coprocessor, described synchronous static memory links to each other with the route querying coprocessor, reading and writing by route querying coprocessor control synchronous static memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021004587A CN1150731C (en) | 2002-02-01 | 2002-02-01 | High speed routing search system based on content addressable memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021004587A CN1150731C (en) | 2002-02-01 | 2002-02-01 | High speed routing search system based on content addressable memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1362822A true CN1362822A (en) | 2002-08-07 |
| CN1150731C CN1150731C (en) | 2004-05-19 |
Family
ID=4739375
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021004587A Expired - Fee Related CN1150731C (en) | 2002-02-01 | 2002-02-01 | High speed routing search system based on content addressable memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1150731C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100407693C (en) * | 2004-12-30 | 2008-07-30 | 中兴通讯股份有限公司 | Dispatching method and equipment for searching and updating routes based on FPGA |
| CN101221538B (en) * | 2008-01-24 | 2010-10-13 | 杭州华三通信技术有限公司 | System and method for implementing fast data search in caching |
| CN101895479A (en) * | 2010-08-17 | 2010-11-24 | 上海交通大学 | System for increasing speed of route lookup |
| CN1610338B (en) * | 2003-10-24 | 2011-04-27 | 阿尔卡特公司 | Method for accelerated packet processing |
| US8601262B2 (en) | 2002-10-31 | 2013-12-03 | Ntt Docomo Inc. | Location privacy through IP address space scrambling |
-
2002
- 2002-02-01 CN CNB021004587A patent/CN1150731C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8601262B2 (en) | 2002-10-31 | 2013-12-03 | Ntt Docomo Inc. | Location privacy through IP address space scrambling |
| CN1610338B (en) * | 2003-10-24 | 2011-04-27 | 阿尔卡特公司 | Method for accelerated packet processing |
| CN100407693C (en) * | 2004-12-30 | 2008-07-30 | 中兴通讯股份有限公司 | Dispatching method and equipment for searching and updating routes based on FPGA |
| CN101221538B (en) * | 2008-01-24 | 2010-10-13 | 杭州华三通信技术有限公司 | System and method for implementing fast data search in caching |
| CN101895479A (en) * | 2010-08-17 | 2010-11-24 | 上海交通大学 | System for increasing speed of route lookup |
| CN101895479B (en) * | 2010-08-17 | 2013-03-27 | 上海交通大学 | System for increasing speed of route lookup |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1150731C (en) | 2004-05-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4556761B2 (en) | Packet transfer device | |
| US9264357B2 (en) | Apparatus and method for table search with centralized memory pool in a network switch | |
| US5398245A (en) | Packet processing method and apparatus | |
| US6732227B1 (en) | Network translation circuit and method using a segmentable content addressable memory | |
| US6965969B2 (en) | Non-uniform cache apparatus, systems, and methods | |
| US8625604B2 (en) | Hash-based prefix-compressed trie for IP route lookup | |
| Bando et al. | FlashTrie: beyond 100-Gb/s IP route lookup using hash-based prefix-compressed trie | |
| CN109388590B (en) | Dynamic cache block management method and device for improving multichannel DMA (direct memory access) access performance | |
| US8341187B2 (en) | Method and device for storage | |
| CN1216473C (en) | TCAM high-speed search method and system supporting multiple nexthop | |
| US20040015598A1 (en) | Method for increasing the transmit and receive efficiency of an embedded ethernet controller | |
| US6697923B2 (en) | Buffer management method and a controller thereof | |
| CN1150731C (en) | High speed routing search system based on content addressable memory | |
| WO2023123902A1 (en) | Data transmission processing method in chip system, and related device | |
| CN103023782B (en) | A kind of method and device of accessing three-state content addressing memory | |
| US8730961B1 (en) | System and method for optimizing router lookup | |
| WO2016090848A1 (en) | Method and device for managing table space of ternary content addressable memory | |
| US20230144038A1 (en) | Memory pooling bandwidth multiplier using final level cache system | |
| JP7010922B2 (en) | Forwarding entry access | |
| TW569219B (en) | Architecture and method for updating cache data | |
| CN1301607C (en) | Method for implementing supporting virtual local network fire wall | |
| CN107948075A (en) | Effectively solve the method and system of public network and VPN route forwarding | |
| US20230028997A1 (en) | Sgl processing acceleration method and storage device | |
| CN1798088A (en) | Dispatching method and equipment for searching and updating routes based on FPGA | |
| JP2005333220A (en) | Network node device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040519 Termination date: 20160201 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |