CN1357921A - Coating soldered pad configuration for reducing chip impedance - Google Patents
Coating soldered pad configuration for reducing chip impedance Download PDFInfo
- Publication number
- CN1357921A CN1357921A CN 01144461 CN01144461A CN1357921A CN 1357921 A CN1357921 A CN 1357921A CN 01144461 CN01144461 CN 01144461 CN 01144461 A CN01144461 A CN 01144461A CN 1357921 A CN1357921 A CN 1357921A
- Authority
- CN
- China
- Prior art keywords
- circle
- wafer
- conductive projection
- conductive
- reduce
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
Abstract
The coating soldered pad configuration includes central chip conducting lug array; and four rings of conducting lugs including the first or the inner ring with conducting lugs connected to the power ring, the second ring with conducting lugs connected to the ground ring and the third and the fourth ring with conducting lugs connected to the signal input end. The conducting lugs connected to the third and the fourth rings are cross arranged to reduce wire bending and thus inductive reactance. The re-distributed conductor layer of the coating chip is formed between the protecting layer and the upper conductor layer and is defined based on the upper conductor layer to reduce the length of the conducting lugs.
Description
Technical field
The present invention relates to the integrated circuit encapsulation technology, particularly a kind ofly reduce impedance and improvement and cover the wafer-covered solder pad configuration that reduces impedance on the wafer of brilliant high-frequency signal transmission quality.
Background technology
Along with very big type integrated circuit (ULSI) process technique ground replacement of generation, the single wafer increased functionality, impel the encapsulation technology level also have in response to and significantly promote.End or contact mat (bonding pad) are gone in the output that utilizes the lead frame connecting wafer of tradition large-scale integrated circuit (LSI) or medium-sized integrated circuit (MSI), or title lead contact mat (wire bond pad), again with the method for packing of pottery or resin forming, ultra-large type integrated circuit (VLSI) has been seemed deposited not required, still more ULSI.
Generally utilize lead frame to connect the method for packing of contact mat, produced the gold thread shift phenomenon by preventing that gold thread is long or inject the packaging plastic material, contact mat can only design in the periphery of the element region of wafer.Element therefore need be with longer electric lead (conductive trace) to connect between contact mat and the element.In addition, under the trend along with single wafer increased functionality and high speed performance requirement, the I/O number of pins is also more and more.The tradition bonding wire connects the mode of contact mat, follows high inductance, and the working at high speed of unfavorable wafer can not satisfy the demand of following high performance integrated circuit.
Therefore, a kind of IC encapsulation technique that covers crystalline substance (flip-chip) that is called is promptly given birth in response to the demand.This technology please refer to Fig. 1, a plurality of conductive projections 24 are designed in the superiors of wafer 20, each conductive projection 24, be not limited to be formed at beyond the chip element district around, be evenly distributed in wafer 20 everywhere but be close to array way.Final wafer 20 turns (flipped) again makes the conductive projection 24 of wafer upper strata array distribution be connected in corresponding substrate 26 down.There is corresponding conductive projection pad (or title chip-covered boss pad) 28 corresponding with it on the base plate for packaging 26, to accept conductive projection 24 with array way.
Because overlay crystal chip and lead contact mat (wire bonding pad) wafer are in wafer core inside (core) otherness and little.When chip design was lead contact mat wafer, contact mat was disposed in the wafer and (does not generally allow the element existence below the contact mat) all around, then covers with sheath around all the other of wafer.When chip design is overlay crystal chip, then forms a metal level again on the sheath of former lead contact mat type wafer, and form electric lead through little shadow and etching step.Be connected to the wafer core by all around lead contact mat position in the wafer, form projection again and connect the tin ball thereon.Therefore, with regard to integrated circuit (IC) design company, how still to utilize existing design tool design overlay crystal chip in response to lead contact mat wafer.
The cross sectional representation of one traditional overlay crystal chip please refer to shown in Figure 2.Its basic framework from bottom to top comprises polysilicon layer (element gate or conductor layer) 40, the first intraconnections dielectric layer 50A, the first intraconnections conductor layer 60A, the second intraconnections dielectric layer 50B, the second intraconnections conductor layer 60B, the 3rd intraconnections dielectric layer 50C, the 3rd intraconnections conductor layer 60C, reaches sheath 70.Connect the polysilicon layer 40 and the first intraconnections conductor layer 60A respectively with contact 55A, interlayer 55B, 55C between the intraconnections conductor layer.On the sheath 70 and one the 4th metal level 80 is arranged, be defined as redistribution lead wire layer (redistribution layer through little shadow and etching; Be called for short RDL), in order to connect contact mat 75 each precalculated position, form sheath (passivation layer) 92 again, and after little shadow and etched patternization, electroplate to the wafer core, or with the mode of screen printing, formation conductive projection 95.
All conductive projections of above-mentioned tradition are the array kenel and distribute.In addition, no matter conductive projection is signal or ground connection or connects supply voltage that polyhybird is present between the conductive projection of each ranks.Therefore with regard to signal connected, part lead-in wire (or claiming electric lead (conductive trace)) was longer, and the part lead-in wire is shorter.Conductive projection distance on contact mat around the former design wafer and wafer core is decided.Its vertical view then as shown in Figure 3, the peripheral contact mat that connects power supply P utilizes RDL layer 97 to be connected to the wafer core contact mat 98 of wafer, the contact mat of other ground connection G, the contact mat that connects signal S also with.
Summary of the invention
Because traditional overlay crystal chip design, signal conductive projection, ground connection conductive projection, power supply conductivity projection are mixed between the array conductive projection, and therefore, the electric lead impedance of the redistribution lead wire layer RDL that the signal conductive projection of part is utilized will be bigger.The present invention will address the above problem, and the wafer-covered solder pad that proposes on a kind of wafer to reduce impedance is configured to reduce the impedance of holding wire weld pad.
The purpose of this invention is to provide inductance and the anti-solution of inductance that the bent angle because of electric lead under the high-frequency operation produces.
Another object of the present invention is in order to reduce and signal is exported wafer-covered solder pad collocation method into the relevant impedance of end.
The present invention discloses the wafer-covered solder pad that reduces impedance on a kind of wafer and puts, and comprises at least: wafer core array of conductive bumps; Four circle conductive projection circles are arranged from inside to outside, and wherein each conductive projection of first lap is connected to power ring (power ring).Conductive projection in the second circle conductive projection circle is connected to ground loop (ground ring); Signal is exported into end, then mainly is connected to the 3rd circle conductive projection circle and the 4th circle conductive projection circle.In addition for reducing each conductive projection of anti-and the 3rd circle conductive projection of inductance, be staggered to reduce the bending of IC base plate for packaging electric lead about being with conductive projection in the 4th circle conductive projection circle.In addition, the conductor layer of distribution again of overlay crystal chip is formed under the sheath, the superiors conductor layers top, and export according to the superiors' conductor layer of wafer and to define the conductor layer that distributes again into buffering area and ground connection, power bus to reduce conductive projection electric lead (conductiv trace) length of signal output part and peripheral two circle conductive projection circles.
Description of drawings
Brilliant IC encapsulation technology is covered in Fig. 1 demonstration, with the schematic diagram of the chip-covered boss pad on the conductive projection counterpart substrate that covers wafer;
Fig. 2 shows each metal level of traditional overlay crystal chip, the cross sectional representation of contact mat and conductive projection relevant position;
Fig. 3 shows traditional overlay crystal chip redistribution lead wire layer RDL, with the schematic diagram that is connected of VSS, VCC and signal;
Fig. 4 shows the overlay crystal chip conductive projection configuration schematic diagram according to the inventive method design;
Fig. 5 shows the overlay crystal chip conductive projection configuration wafer core according to the inventive method design, and four circle conductive projection configuration schematic diagram please note that outer two circles connect signals and export about the conductive projection of end or be staggered up and down.
Embodiment
Conductive projection configuration of the present invention please refer to Fig. 4.Overlay crystal chip core 100 comprises various core voltages (core voltage) projection and core ground connection (core ground) projection is the distribution of array kenel.Show four circle conductive projections around the core 100, be the power supply projection 110a that is connected to power ring (power ring) VCC, VSS projection 110b, signal projection 110c and the 110d that is connected to ground loop (ground ring) from inside to outside in regular turn.Please note outermost two ring signal projection 110c, 110d and be left and right sides interlace mode.Signal projection 110c, 110d are outmost turns space maximums in the advantage of outermost two circles, therefore, can arrange maximum signal projections.And outermost two ring signal projection 110c, 110d are the advantage of left and right sides interlace mode is that the electric lead 115 that is connected with the signal projection linearly needn't be bent.So can make the inductance antiatherosclerotic effect minimum, particularly the signal projection is when going into to fill up as the output of high frequency.
For reducing the impedance of the long generation of electric lead that connects the signal projection, the present invention changes the position of redistributing layer (RDL).Be example for example, then form sheath after conventional method M3 conductor layer forms, reach the sheath window, form M4 again and be defined as the RDL layer, in order on each position of wafer core, to form conductive projection to expose contact mat with three layer conductor layer M1, M2, M3.Please also refer to Fig. 5, after method of the present invention changes M1 (figure do not show), M2 (figure does not show), M3 conductor layer into and forms, then form conductor layer M4, conductor layer M4 is in order to be defined as the RDL layer.Then remove in the former contact mat zone that is designed to of former M3 conductor layer part, and utilize semiconductor substrate configuration electric capacity, protecting component for electrostatic discharge and inductance element one of them and the combination thereof of below, this zone.
The definition of conductor layer M4 is to go into signal damping district (I/O bus-bar) according to output on the M3 conductor layer to the M4 definition, to please refer to Fig. 5 with voltage/power bus (voltage/ground bus) (being positioned at the 3rd layer conductor floor M3).Therefore, the present invention can reduce the electric lead of signal output part and two ring signal projections.Particularly for conventional wires contact mat chip design, lead M3 is connected to contact mat with signal, and the present invention to be conductive projection with representation signal be disposed near the lead contact mat, therefore more can manifest conductive projection that the present invention connects representation signal and be disposed near the lead contact mat advantage.Please note Fig. 5 except showing I/O bus bar voltage/power bus (M3), only show the four circle conductive projections and the corresponding arrangement of conductors layer M4 thereof that are positioned at wafer core periphery.Above-mentioned four circle conductive projections are respectively in regular turn from inside to outside and are connected to power ring (power ring) VCC power supply projection 110a, are connected to the VSS projection of ground loop (ground ring) and are connected to signal and export two ring signal projection S into end.In addition, it is first preferential to be disposed at the 4th circle conductive projection circle 110d that the signal of above-mentioned overlay crystal chip is exported into end, and the 3rd circle conductive projection circle 110c be time preferential, complies with near wafer core array of conductive bumps the preferential configuration sequence that successively decreases.In other words, also the ground loop of minority or the connection that connects power ring of minority can be disposed at the 4th circle conductive projection circle 110d and the 3rd circle conductive projection circle 110c in case of necessity.Certainly, signal is exported also can connect into end and is disposed at the first lap conductive projection circle 11a and the second circle conductive projection circle 110b.But priority is then far below the 4th circle conductive projection circle 110d or the 3rd circle conductive projection circle 110c.
In addition, as long as the below intersection of core voltage projection just directly connects with interlayer in the electric lead that connects core voltage.The below intersection of core ground connection projection also directly connects with interlayer in the electric lead that connects core ground connection.So can further reduce the electric lead length that is connected to core voltage.
Certainly, when chip-covered boss as above changes, cooperate the bump pads on the substrate of chip-covered boss, also with correspondence and change disposes one as described above.
The above embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when not limiting claim of the present invention with it, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim scope of the present invention.
Claims (10)
1. reduce the wafer-covered solder pad configuration of impedance on the wafer, it is characterized in that: comprise at least:
Wafer core array of conductive bumps;
First lap conductive projection circle surrounds this wafer core array of conductive bumps, and the conductive projection of majority in this first lap conductive projection circle is respectively in order to be connected to power ring (power ring) or ground loop (ground ring);
The second circle conductive projection circle surrounds this first lap conductive projection circle, and the interior most conductive projection of this second circle conductive projection circle is connected to signal and exports into end.
2. reduce the wafer-covered solder pad configuration of impedance on the wafer as claimed in claim 1, it is characterized in that: more comprise a circle or the above conductive projection circle of a circle, surround this first lap conductive projection circle, be connected to signal and export, and each conductive projection of this second circle conductive projection circle and peripheral conductive projection circle thereof is staggered about being each other into end.
3. reduce the wafer-covered solder pad configuration of impedance on the wafer as claimed in claim 2, it is characterized in that: it is anti-in order to the inductance that reduces high-frequency signal to be staggered about above-mentioned conductive projection is.
4. reduce the wafer-covered solder pad configuration of impedance on the wafer as claimed in claim 1, it is characterized in that: more comprise a circle or the above conductive projection cast of a circle and be formed between above-mentioned first lap conductive projection circle and the above-mentioned second circle conductive projection circle, in order to be connected to power ring or ground loop.
5. reduce the wafer-covered solder pad configuration of impedance on the wafer as claimed in claim 1, it is characterized in that: above-mentioned wafer core array of conductive bumps is in order to connect various core voltages.
6. reduce the wafer-covered solder pad configuration of impedance on the wafer as claimed in claim 1, it is characterized in that: above-mentioned first lap conductive projection circle, the second circle conductive projection circle are connected to power ring or ground loop or signal end by the conductor layer that distributes again and again of sheath below respectively with above-mentioned conductive projection.
7. reduce the wafer-covered solder pad configuration of impedance on the wafer as claimed in claim 1, it is characterized in that: wherein a kind of of the group that the semiconductor of above-mentioned first lap conductive projection circle, the second circle conductive projection circle below is formed in order to configuration electric capacity, protecting component for electrostatic discharge, inductance element and combination thereof.
8. reduce the wafer-covered solder pad configuration of impedance on the wafer as claimed in claim 1, it is characterized in that: it is first preferential to be disposed at this second circle conductive projection circle that the signal of above-mentioned overlay crystal chip is exported into end, and this first lap conductive projection circle be time preferentially.
9. reduce the wafer-covered solder pad configuration of impedance on the wafer as claimed in claim 1, it is characterized in that: the conductor layer of distribution again of above-mentioned overlay crystal chip is formed at the sheath below, the superiors conductor layers top, and export into buffering area and ground connection, power bus according to the superiors' conductor layer of this wafer and to define this conductor layer that distributes again to reduce signal output part and this second conductive projection electric lead (conductive trace) length of enclosing the conductive projection circle.
10. reduce the wafer-covered solder pad configuration of impedance on the wafer, it is characterized in that: comprise at least:
Wafer core array of conductive bumps;
First lap conductive projection circle surrounds this wafer core array of conductive bumps, and conductive projections most in this first lap conductive projection circle are connected to power ring (power ring);
The second circle conductive projection circle surrounds this first lap conductive projection circle, and most conductive projections is connected to ground loop (ground ring) in this second circle conductive projection circle; And
The 3rd circle conductive projection circle surrounds this second circle conductive projection circle, and the interior most conductive projection of the 3rd circle conductive projection circle is connected to signal and exports into end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01144461 CN1187819C (en) | 2001-12-18 | 2001-12-18 | Coating soldered pad configuration for reducing chip impedance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01144461 CN1187819C (en) | 2001-12-18 | 2001-12-18 | Coating soldered pad configuration for reducing chip impedance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1357921A true CN1357921A (en) | 2002-07-10 |
| CN1187819C CN1187819C (en) | 2005-02-02 |
Family
ID=4677599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01144461 Expired - Lifetime CN1187819C (en) | 2001-12-18 | 2001-12-18 | Coating soldered pad configuration for reducing chip impedance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1187819C (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201383A (en) * | 2010-03-26 | 2011-09-28 | 精材科技股份有限公司 | Electronic device package and fabricating method thereof |
| CN102915996A (en) * | 2011-08-03 | 2013-02-06 | 矽品精密工业股份有限公司 | Electrical interconnection mechanism for 3D integrated circuit |
| CN105374694A (en) * | 2015-12-04 | 2016-03-02 | 上海兆芯集成电路有限公司 | Chip apparatus and projection configuration method thereof |
-
2001
- 2001-12-18 CN CN 01144461 patent/CN1187819C/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102201383A (en) * | 2010-03-26 | 2011-09-28 | 精材科技股份有限公司 | Electronic device package and fabricating method thereof |
| CN102915996A (en) * | 2011-08-03 | 2013-02-06 | 矽品精密工业股份有限公司 | Electrical interconnection mechanism for 3D integrated circuit |
| CN102915996B (en) * | 2011-08-03 | 2015-04-15 | 矽品精密工业股份有限公司 | Electrical interconnection mechanism for 3D integrated circuit |
| CN105374694A (en) * | 2015-12-04 | 2016-03-02 | 上海兆芯集成电路有限公司 | Chip apparatus and projection configuration method thereof |
| CN105374694B (en) * | 2015-12-04 | 2020-09-01 | 上海兆芯集成电路有限公司 | Chip device and bump configuration method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1187819C (en) | 2005-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6680544B2 (en) | Flip-chip bump arrangement for decreasing impedance | |
| US7489035B2 (en) | Integrated circuit chip package having a ring-shaped silicon decoupling capacitor | |
| US8350380B2 (en) | Method for manufacturing leadframe, packaging method for using the leadframe and semiconductor package product | |
| KR100592786B1 (en) | Stack package made of area array type packages, and manufacturing method thereof | |
| CN101315915B (en) | Semiconductor device | |
| KR100329407B1 (en) | Electrode structure of semiconductor element | |
| US5604161A (en) | Semiconductor device assembly with minimized bond finger connections | |
| US7834435B2 (en) | Leadframe with extended pad segments between leads and die pad, and leadframe package using the same | |
| US5606196A (en) | High-frequency, high-density semiconductor chip package with screening bonding wires | |
| CN203103294U (en) | Semiconductor packaging element | |
| US5898217A (en) | Semiconductor device including a substrate having clustered interconnects | |
| CN100352050C (en) | Semiconductor with multiple rows of bond pads | |
| CN101540308B (en) | Semiconductor chip package | |
| US20040124545A1 (en) | High density integrated circuits and the method of packaging the same | |
| US7466021B2 (en) | Memory packages having stair step interconnection layers | |
| US20230082767A1 (en) | Electronic package | |
| KR100874925B1 (en) | Semiconductor package, manufacturing method thereof, card comprising same and system comprising same | |
| US20120196438A1 (en) | Chip package structure | |
| CN1187819C (en) | Coating soldered pad configuration for reducing chip impedance | |
| CN2521757Y (en) | Overlay crystal welding pad allocation on chip for reducing impedance | |
| CN115995440A (en) | Semiconductor packaging structure and manufacturing method thereof | |
| US7122892B2 (en) | Multi-chip integrated circuit module for high-frequency operation | |
| CN105009279B (en) | Semiconductor devices and the method for manufacturing semiconductor devices | |
| CN103650131A (en) | Semiconductor device | |
| US20070029663A1 (en) | Multilayered circuit substrate and semiconductor package structure using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20050202 |
|
| CX01 | Expiry of patent term |