CN1357913A - Making process of protecting layer - Google Patents

Making process of protecting layer Download PDF

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Publication number
CN1357913A
CN1357913A CN00134488A CN00134488A CN1357913A CN 1357913 A CN1357913 A CN 1357913A CN 00134488 A CN00134488 A CN 00134488A CN 00134488 A CN00134488 A CN 00134488A CN 1357913 A CN1357913 A CN 1357913A
Authority
CN
China
Prior art keywords
lining
layer
weld pad
dielectric layer
protective layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN00134488A
Other languages
Chinese (zh)
Inventor
王木俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to CN00134488A priority Critical patent/CN1357913A/en
Publication of CN1357913A publication Critical patent/CN1357913A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

The making process of protecting layer is to form dielectrical layer, lining layer and soldering pads successively on the substrate provided with semiconductor elements. After electric connection of the semiconductor elements in the substrate with the outer packing support, a protecting layer is formed on the substrate to protect circuits and elements of chip. Then, partial protecting layer is removed to expose partial soldering pads for lead connection.

Description

The manufacture method of protective layer
The present invention relates to a kind of manufacture method of protective layer, particularly relate to a kind of manufacture method that the protective layer of higher hardness is provided.
In semi-conductive manufacture process, between the conductive structure normally with the insulating barrier of dielectric material as the isolate conductive structure.Wherein, conductive structure for example is intraconnections (Interconnect), grid or dielectric plugs (plug).Along with constantly reducing of the live width of semiconductor element, the spacing of adjacent lead is also along with dwindling, therefore the material that generally is used for dielectric layer for example contains the silicate (hydrogensilsesquioxane of hydrogen, HSQ) and methylic silicate (methyl silsequioxane, MSQ, dielectric constant is approximately between 2.6 to 2.8) etc., be dielectric material between low-k.
Yet the dielectric material of these low-ks has porousness usually, and material is comparatively soft, therefore, in follow-up lead joint technology, a relative stress can't be provided, make that the adherence between lead and weld pad is bad, in addition, because its porous character, so aqueous vapor is easy to enter among the dielectric material, and makes the dielectric constant shakiness of dielectric material, even the problem of generation leakage current, and the reliability of reduction element.
Therefore the present invention is providing a kind of manufacture method of protective layer; promptly on dielectric layer, form lining; can provide in the follow-up lead joint technology; preferable adherence is arranged between lead and weld pad; simultaneously also can avoid aqueous vapor to enter dielectric layer; to promote the stability of dielectric layer, avoid producing the problem of leakage current, thereby improve reliability of products.
The present invention proposes a kind of manufacture method of protective layer.At first, provide substrate, then with semiconductor element; form dielectric layer providing in the substrate with semiconductor element, then, on dielectric layer, form lining; afterwards, on lining, form weld pad to electrically connect the semiconductor element and extraneous structure dress support in the substrate, then; in substrate, form protective layer, with the circuit and the element of protection chip, then; remove partial protection layer; and expose part of solder pads, afterwards, on weld pad, carry out the lead joint technology.
In above-mentioned step, wherein the material of lining for example is that (fluorosilicate glass, FSG) or silicon nitride, and this lining also can be the structure of multiple-level stack to fluorine-containing glass.And the material of dielectric layer for example is the material that silicates etc. has low-k.
The present invention forms lining on dielectric layer, this lining has a kind of higher hardness, and providing in the follow-up lead joint technology has a relative stress, makes lead and weld pad that adherence preferably be arranged.In addition,, have porous character and make aqueous vapor be easy to enter, therefore on dielectric layer, form the higher lining of hardness, can avoid water to enter, cause the dielectric constant shakiness because of dielectric layer is the material of low-k, and the problem of generation leakage current.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 is the manufacturing process profile of a kind of protective layer according to one preferred embodiment of the present invention.
100: the semiconductor-based end
102: dielectric layer
104: weld pad
106: lead
108: protective layer
110: lining
Embodiment
Fig. 1 illustrates the manufacture method profile according to a kind of protective layer of one embodiment of the present invention.
With reference to Fig. 1, at first, a kind of substrate 100 with several semiconductor elements (not shown) is provided, in substrate 100, form dielectric layer 102, the formation method of dielectric layer 102 for example is a chemical vapour deposition technique, and dielectric layer 102 is the material of low-k, for example is silicates, preferably hydrogeneous silicate or methylic silicate.
Form in substrate 100 after the dielectric layer 102, form one deck lining 110 for example for chemical vapour deposition technique forms fluorine-containing glassy layer or silicon nitride layer on dielectric layer 102, wherein the preferred material of lining 110 is the fluorine-containing glass or the material of hardness.And dielectric layer 102 is adjusted with the visual required dielectric constant total value of thickness proportion of lining 110, and under the situation of the dielectric constant that does not change dielectric layer 102, dielectric layer 102 is about about 10: 1 with the preferred thickness ratio of lining 110.
Form lining 110 on dielectric layer 102, therefore follow-up in the lead joint technology because this lining 110 can provide a higher hardness, lining 110 can provide a relative stress to improve the adherence between lead and the weld pad.In addition, adjustment dielectric layer 102 is about 10: 1 with the thickness ratio of lining 11 0, the dielectric constant of dielectric layer 102 can not changed because of the existence of lining, and can reach the purpose of the hardness that improves dielectric layer 102.In addition, because dielectric layer 102 is the material of low-k, has porous character, and make that easily aqueous vapor enters, cause the dielectric constant shakiness of dielectric layer 102, even produce the problem of leakage current, therefore also can avoid aqueous vapor to enter among the dielectric layer 102 forming lining 110 on the dielectric layer 102.
Except forming lining 110 104 of dielectric layer 102 and weld pads, the stress when the lead joint technology can be provided, so that the adherence between lead and weld pad to be provided, and dielectric layer 102 provides better elastic, and it is cracked to avoid chip to produce in wire bond process.
On dielectric layer 102, form after the lining 110, on lining 110, form weld pad 104.The method that forms weld pad 104 for example forms conductive layer with chemical vapour deposition technique, defines this conductor layer again and forms.And this weld pad 104 is the semiconductor elements and extraneous package support that are used for being electrically connected in the substrate.
Then, after weld pad 104 forms, form layer protective layer 108 on the semiconductor-based end 100, the formation of protective layer 108 for example is chemical vapour deposition technique, and its material for example silicon nitride and phosphosilicate glass (phosphosilicate glass, PSG).Protective layer 108 can be used to keep out penetrating of extraneous aqueous vapor and alkali metal ion, and protection component avoids suffering nonvolatil mechanical wounding, to prolong the life-span of integrated circuit.
Then, after protective layer 108 forms, remove partial protection layer 108 with exposed portions serve weld pad 104, afterwards, carry out the lead joint technology on weld pad 104, form lead 106, wherein the material of lead 106 for example is a gold.
Owing on dielectric layer 102, cover a lining 110, higher hardness can be provided, therefore, in the lead joint technology, can make lead 106 and weld pad 104 that adhesion strength is preferably arranged.
In the present invention, on dielectric layer 102, form the lining 110 of a higher hardness, a relative stress in the follow-up lead joint technology can be provided, make lead 106 and weld pad 104 that adhesion strength preferably be arranged.In addition,, therefore, on dielectric layer 102, form lining 110, can prevent that aqueous vapor from entering, avoid the dielectric constant shakiness of dielectric layer 102 and the problem that produces leakage current because dielectric layer 102 has porousness aqueous vapor is easily entered.
Though the present invention describes as above in conjunction with a preferred embodiment, yet it is not to be used to limit the present invention.Those skilled in the art can make various changes and variation under the situation that does not break away from the spirit and scope of the present invention.So protection range should be limited by accompanying Claim.

Claims (16)

1. the manufacture method of a protective layer comprises the following steps:
One substrate is provided, forms dielectric layer in this substrate;
On dielectric layer, form a lining;
On lining, form a weld pad;
On this semiconductor-based end, form a protective layer;
Limit this protective layer, up to exposing weld pad; And
On weld pad, carry out the lead joint technology.
2. method according to claim 1, wherein, this lining comprises fluorine-containing glass.
3. method according to claim 1, wherein, this lining comprises silicon nitride.
4. method according to claim 1, wherein, this dielectric layer is 10: 1 with the thickness ratio of this lining.
5. method according to claim 1, wherein, this lining also comprises a multiple-level stack structure.
6. method according to claim 1, wherein, this lining forms with chemical vapour deposition technique.
7. method according to claim 1, wherein, this protective layer that forms in this substrate comprises phosphosilicate glass and silicon nitride.
8. method according to claim 1, wherein, the lead in this lead joint technology comprises metallic gold.
9. method according to claim 1, wherein, the step that forms this weld pad on lining also comprises:
On this lining, form a conductive layer; And
Limit this conductive layer, form this weld pad.
10. the manufacture method of a protective layer is applicable in the semiconductor substrate, wherein has been formed with a silicates layer on this semiconductor-based end, and this manufacture method may further comprise the steps:
On this silicates layer, form a fluorine-containing glassy layer;
On this fluorine-containing glassy layer, form a weld pad;
On this semiconductor-based end, form protective layer;
Limit this protective layer, up to exposing this weld pad; And
Carry out a lead joint technology.
11. method according to claim 10, wherein, this dielectric layer is 10: 1 with the thickness ratio of this lining.
12. method according to claim 10, wherein, this lining also comprises a multiple-level stack structure.
13. method according to claim 10, wherein, this lining forms with chemical vapour deposition technique.
14. method according to claim 10, wherein, this protective layer that forms in this substrate comprises phosphosilicate glass and silicon nitride.
15. method according to claim 10, wherein, the lead in this lead joint technology comprises metallic gold.
16. method according to claim 10, wherein, the step that forms this weld pad on lining also comprises:
On this lining, form a conductive layer; And
Limit this conductive layer, form this weld pad.
CN00134488A 2000-12-04 2000-12-04 Making process of protecting layer Pending CN1357913A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN00134488A CN1357913A (en) 2000-12-04 2000-12-04 Making process of protecting layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN00134488A CN1357913A (en) 2000-12-04 2000-12-04 Making process of protecting layer

Publications (1)

Publication Number Publication Date
CN1357913A true CN1357913A (en) 2002-07-10

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ID=4596239

Family Applications (1)

Application Number Title Priority Date Filing Date
CN00134488A Pending CN1357913A (en) 2000-12-04 2000-12-04 Making process of protecting layer

Country Status (1)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738105A (en) * 2011-03-29 2012-10-17 精工电子有限公司 Semiconductor device and method of manufacturing the same
CN105762086A (en) * 2014-12-16 2016-07-13 中芯国际集成电路制造(上海)有限公司 Bonding pad structure manufacturing method, bonding structure manufacturing method, and bonding structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102738105A (en) * 2011-03-29 2012-10-17 精工电子有限公司 Semiconductor device and method of manufacturing the same
CN102738105B (en) * 2011-03-29 2016-09-28 精工半导体有限公司 Semiconductor device and manufacture method thereof
CN105762086A (en) * 2014-12-16 2016-07-13 中芯国际集成电路制造(上海)有限公司 Bonding pad structure manufacturing method, bonding structure manufacturing method, and bonding structure

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PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication