CN1357890A - DRAM structure and its operation method - Google Patents
DRAM structure and its operation method Download PDFInfo
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- CN1357890A CN1357890A CN 00134866 CN00134866A CN1357890A CN 1357890 A CN1357890 A CN 1357890A CN 00134866 CN00134866 CN 00134866 CN 00134866 A CN00134866 A CN 00134866A CN 1357890 A CN1357890 A CN 1357890A
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Abstract
The present invention is the structure and operation method of DRAM suitable for static RAM compatible transistor. The monotransistor static RAM structure can maintain the data of the DRAM unit effectively without loss. The structure may operate in low voltage condition, and can reduce the power consumption of whole DRAM structure operate. In ready or sleep modes, the structure can maintain the data of the DRAM unit and reduce the overall power consumption.
Description
The present invention relates to a kind of dynamic RAM (Dynamic Random AccessMemory, hereinafter referred to as DRAM) structure and its method of operating, be particularly related to a kind of static RAM (Static Random Access Memory that is applicable to, hereinafter referred to as SRAM) dynamic RAM (the Dynamic Random Access Memory of storage unit, hereinafter referred to as DRAM) structure and method of operating thereof, and this dynamic RAM just has the static RAM of one-transistor as the compatible transistor of static RAM.
Traditional DRAM storage unit (Cell), it includes a transistor AND gate one capacitor, and the area that it had and the cost of manufacturing are much smaller than SRAM.Because traditional SRAM structure has 4 to 6 transistors.Therefore, use lower-cost DRAM storage unit to use as SRAM, be the direction that industry is made great efforts always.
Yet,, but be to upgrade termly if data storing in the storage unit of DRAM, must be upgraded (Refresh) termly again, and be stored in the data of SRAM.Renewal again in the DRAM storage unit is operated, and will waste the frequency range (Bandwidth) of storer.For example, have the DRAM of 100 1,000,000 frequencies (100MHz) operation, the time of its each clock is 10 nanoseconds (nsec).Under such DRAM structure, the time of each external access data was 10 nanoseconds, and the time that each upgrades again also was 10 nanoseconds, and this will see designed circuit and memory size and decide certainly, also may from 16 to 500 nanoseconds.Because the time of access may be at one time with the time of upgrading again, therefore, this DRAM may just must stop to wait for (Idle) once that so that do the action of upgrading again, therefore, the usefulness that it showed may be reduced to 50-90% per approximately 500 nanoseconds.Because such considers, and the frequency range of whole operation is reduced.
In technique known, once attempted in SRAM utilization structure, using the DRAM storage unit, but can't effectively reach this feature of SRAM with storing data permanently, since the operation that such DRAM storage unit needs outside signal controlling to upgrade, and such SRAM structure can postpone to some extent because of the operation of upgrading.This causes such DRAM storage unit is not to be compatible to fully in the structure of SRAM.
In addition, the someone proposes high-speed SRAM memory cache (Cache) and uses in the lump with the DRAM of relative low speed, with the time (U.S. the 5th, 559, No. 750 patents) of the average access of speeds up memory.The access time that such structure is real, but must consider this SRAM memory cache hit rate (Hit Rate).And there is circuit that the renewal operation of DRAM storage unit is provided in addition.Yet such structure still can have influence on the operation of external access, and can't meet whole random access time.
Have a structure to be to use the DRAM of a lot of column of memory cells in addition, with the time of reduction DRAM access, and such structure can't be allowed the time that wherein column of memory cells delay is upgraded.
In addition, in the 6th, 028, No. 804 patents of the U.S., a kind of device that uses the DRAM storage unit in the SRAM structure is proposed.Right its structure is to use an access resolver (Access Arbiter), requires clock and the inner refresh clock that is produced to do a ruling access of outside, preferentially allows the clock operation of external access, with the generation that avoids conflict.Yet, under this structure, but be must loss operating frequency partly.
In view of this, the purpose of this invention is to provide a kind of SRAM structure and its method of operating of the DRAM of use storage unit, can preserve the stored data of DRAM storage unit effectively, but can not have influence on the normal running of SRAM.
Another object of the present invention, a kind of SRAM structure and its method of operating of the DRAM of use storage unit are provided, particularly this SRAM has under the situation of low voltage operating, still can keep the stored data of DRAM storage unit, and can reduce the power that whole SRAM structure operation is consumed.
Another purpose of the present invention, a kind of SRAM structure and its method of operating of the DRAM of use storage unit are provided, particularly this SRAM can be under standby (Stand-by) pattern, or under sleep pattern (Sleep Mode), still can keep the stored data of DRAM storage unit, and can reduce the power that whole SRAM structure operation is consumed.
For reaching above-mentioned purpose, the invention provides a kind of compatible transistorized DRAM structure of static RAM that is applicable to, wherein DRAM structure is to operate under a normal manipulation mode and a low voltage operating pattern.This DRAM structure is to use the foundation of a reference clock signal as operation.Above-mentioned DRAM structure comprises a storage unit, in order to storage data; One detects multiplying arrangement, then have a detecting unit, a first transistor and a transistor seconds, wherein this detecting unit is connected with a paratope line with this first transistor, this transistor seconds, a bit line, wherein this bit line and this paratope line read in order to conduct and upgrade the stored data of this storage unit, and upgrade the stored data frequency of this storage unit according to this reference clock signal; And a switching device shifter, in order to receiving one first voltage and one second voltage, and in order to switch output both one of and be an operating voltage, wherein the level of this first voltage is higher than the level of this second voltage.When this DRAM structure during at this normal manipulation mode, this operating voltage is this second voltage, for should DRAM structure manipulating, to save the operation consumed power, when this DRAM structure is operated under this low voltage operating pattern, this operating voltage is this first voltage, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.
Above-mentioned DRAM structure, wherein storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of capacitor terminates to the 3rd transistorized source end, and the other end of capacitor is then received a tertiary voltage.The 3rd transistorized another source/drain terminates to bit line, the one gate terminal is then received word line, wherein when DRAM structure during at normal manipulation mode, tertiary voltage is a ratio of operating voltage, but tertiary voltage is less than operating voltage, when DRAM structure during in the low voltage operating pattern, tertiary voltage is then according to reference clock signal, when reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of storage unit of dynamic RAM with reduction.
Above-mentioned DRAM structure, wherein the 3rd a transistorized base lining (Substrate) connects a base lining bias voltage (Substrate Bias), and this base lining bias voltage provides with reference to reference clock signal.
Above-mentioned DRAM structure wherein also comprises a dropping equipment, is connected to switching device shifter and this first voltage, and exports second voltage to switching device shifter.
For reaching above-mentioned purpose, the invention provides a kind of compatible transistorized DRAM structure of static RAM that is applicable to, wherein DRAM structure is operated under a normal manipulation mode, a standby mode and one of them pattern of a sleep pattern.This DRAM structure is to use the foundation of a reference clock signal as operation.This DRAM structure comprises a storage unit, in order to storage data; One detects multiplying arrangement, then have a pick-up unit, a first transistor and a transistor seconds, wherein detecting unit is connected with a paratope line with the first transistor, transistor seconds, a bit line, its neutrality line and paratope line be in order to as reading and upgrade the stored data of said memory cells, and the stored data frequency in updated stored unit is according to reference clock signal; An and switching device shifter, in order to receive one first voltage and one second voltage, and in order to switch output both one of and be an operating voltage, wherein the level of first voltage is higher than the level of second voltage, wherein when DRAM structure ties up to normal manipulation mode, operating voltage is above-mentioned second voltage, manipulate with the supply DRAM structure, to save the operation consumed power, when DRAM structure was operated under standby mode, operating voltage can be adjusted into first voltage or second voltage according to reference clock signal; When DRAM structure is operated under sleep pattern, operating voltage can be fixed as above-mentioned first voltage, manipulate with the supply DRAM structure, with the stored above-mentioned data of the storage unit of keeping dynamic RAM.
Above-mentioned DRAM structure, wherein storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of capacitor terminate to the 3rd transistorized source end, the other end of capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to above-mentioned bit line, the one gate terminal is then received word line, wherein when DRAM structure during at normal manipulation mode, tertiary voltage is a ratio of operating voltage, but tertiary voltage is less than aforesaid operations voltage, when DRAM structure is operated under sleep pattern, tertiary voltage is then according to reference clock signal, when reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of data of storage unit of dynamic RAM with reduction.
Above-mentioned DRAM structure, a wherein transistorized base lining (Substrate) connect a base lining bias voltage (Substrate Bias), and base lining bias voltage provides with reference to reference clock signal.
For reaching above-mentioned purpose, the invention provides a kind of method of operating that is applicable to the compatible transistorized DRAM structure of static RAM, wherein above-mentioned DRAM structure comprises that a storage unit, detects a multiplying arrangement and a switching device shifter, and DRAM structure is operated under a normal manipulation mode and a low voltage operating pattern.This method of operating comprises the following steps: to provide one first voltage and one second voltage, and switch output both one of and be an operating voltage of aforesaid operations method, wherein above-mentioned first voltage is higher than above-mentioned second voltage; It is the operation signal of aforesaid operations method that one reference clock signal is provided; Store data in said memory cells; Time sequence frequency according to above-mentioned reference clock signal upgrades the stored data of said memory cells; When above-mentioned normal manipulation mode, it is aforesaid operations voltage that above-mentioned second voltage is provided, manipulate to supply above-mentioned DRAM structure, save the operation consumed power, when under above-mentioned low voltage operating pattern, operating, it is aforesaid operations voltage that above-mentioned first voltage is provided, and manipulates to supply above-mentioned DRAM structure, with the stored above-mentioned data of the said memory cells of keeping above-mentioned dynamic RAM.
Above-mentioned method of operating, wherein storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of capacitor terminate to the 3rd transistorized source end, the other end of capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to bit line, the one gate terminal is then received above-mentioned word line, wherein when the time at normal manipulation mode, above-mentioned tertiary voltage is a ratio of operating voltage, but tertiary voltage is less than aforesaid operations voltage, when in the low voltage operating pattern, above-mentioned tertiary voltage is then according to above-mentioned reference clock signal, when reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of data of said memory cells of dynamic RAM with reduction.
The above-mentioned method of operating that is applicable to the compatible transistorized dynamic randon access transistor arrangement of static RAM, wherein DRAM structure comprises a storage unit, one detects a multiplying arrangement and a switching device shifter, DRAM structure is at a normal manipulation mode, operate under one standby mode and the sleep pattern, wherein the aforesaid operations method comprises the following steps to provide one first voltage and one second voltage, and switch output both one of and be one of aforesaid operations method operating voltage, wherein above-mentioned first voltage is higher than above-mentioned second voltage; It is the operation signal of aforesaid operations method that one reference clock signal is provided; Store data in said memory cells; Time sequence frequency according to above-mentioned reference clock signal upgrades the stored data of said memory cells; When DRAM structure during at normal manipulation mode, it is aforesaid operations voltage that above-mentioned second voltage is provided, manipulate to supply above-mentioned DRAM structure, to save the operation consumed power, when DRAM structure is operated, determine above-mentioned first voltage or above-mentioned second voltage is aforesaid operations voltage according to the clock of above-mentioned reference clock signal under standby mode; When DRAM structure is operated under sleep pattern, above-mentioned first voltage of fixing output is aforesaid operations voltage, manipulate to supply above-mentioned DRAM structure, with the stored above-mentioned data of the said memory cells of keeping above-mentioned dynamic RAM.
In the above-mentioned method of operating, storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of capacitor terminate to the above-mentioned the 3rd transistorized source end, the other end of above-mentioned capacitor is then received a tertiary voltage, the above-mentioned the 3rd transistorized another source/drain terminates to above-mentioned bit line, the one gate terminal is then received word line, wherein when DRAM structure during at normal manipulation mode, above-mentioned tertiary voltage is a ratio of operating voltage, but above-mentioned tertiary voltage is less than operating voltage, when DRAM structure is operated under above-mentioned sleep pattern, above-mentioned tertiary voltage is then according to above-mentioned reference clock signal, when above-mentioned reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of above-mentioned data of said memory cells of above-mentioned dynamic RAM with reduction.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. are done detailed explanation.
The simple declaration of accompanying drawing:
Fig. 1 be according in the preferred embodiment of the present invention in order to DRAM memory cell structure figure as the SRAM storage unit;
Fig. 2 is the sequential chart that data read in Fig. 1 and storage unit are upgraded;
Fig. 3 be according in the preferred embodiment of the present invention in order to DRAM memory cell structure figure as the SRAM storage unit, it has the sequential chart of low voltage operating pattern;
Fig. 4 be according in the preferred embodiment of the present invention in order to DRAM memory cell structure figure as the SRAM storage unit, it has the sequential chart of standby operating mode and sleep operation pattern; And
Fig. 5 is in the DRAM memory cell structure of capacitor in the preferred embodiment of the present invention of the storage unit in Fig. 1, at general operation pattern and the stored electric charge comparison diagram of sleep operation pattern.
The drawing reference numeral simple declaration
Capacitor C
Detect multiplying arrangement 120
Switching device shifter 130
Dropping equipment 140
First-class makeup puts 150
PMOS transistor SAP
Nmos pass transistor SAN
PMOS transistor P1 and P2
Nmos pass transistor N1 and N2
Embodiment
The preferred embodiments of the present invention provide a kind of static RAM (Static RandomAccess Memory, under be called SRAM), and especially in the present widely used action electronic device, the structure that needed SRAM is designed and its method of operating.
And in this structure and method of operating, the static RAM of present embodiment (SRAM) uses the do source of storage data of dynamic RAM (Dynamic Random Access Memory is called DRAM down) storage unit.Because, the DRAM storage unit (Cell) of a use one-transistor and a capacitor, the area that it had and the cost of manufacturing are much smaller than having 4 to 6 transistorized SRAM.As long as and can overcome the problem that DRAM must constantly upgrade (Refresh) again, and determine that stored content does not run off, then the manufacturing cost of whole SRAM must significantly reduce.
And in static RAM (1-TSRAM) structure of the utilization one-transistor of present embodiment, can preserve the stored data of DRAM storage unit effectively and be unlikely to run off.In addition,, can under the low-voltage situation, operate, still can keep the stored data of DRAM storage unit, and can reduce the power that whole SRAM structure operation is consumed according to SRAM structure of the present invention.
If adopt the system of this SRAM structure, under standby (Stand-by) pattern, or under sleep pattern (Sleep Mode), still can keep the stored data of DRAM storage unit, and can reduce the power that whole SRAM structure operation is consumed.This so-called standby mode refers to that the electric weight that total system supplies is still enough, for no other reason than that system and in order to reduce the consumption of power, then enters the holding state of low power consumption not in user mode at present.And sleep pattern is meant that the electric weight of total system is not enough, but still is higher than exercisable specification; this pattern is present in the data of handling in order to protect, and can keep long time in limited electric weight; can allow the user reply the data of its former use if having time, and unlikely loss.
These two kinds of patterns, the most normal being used in used battery and had on the electronic installation of certain restriction service time, for example mobile phone, portable computer, personal data assistant device (PDA) or the like.Because SRAM has the characteristic of long preservation data, therefore, if the DRAM storage unit (Cell) with an one-transistor and a capacitor is used as SRAM, then must consider many factors, wherein, for example under low voltage operating (for example standby mode or sleep pattern), stored contents how to upgrade (Refresh) DRAM storage unit again all is the problem that must consider with data how to keep storage.
Please refer to Fig. 1, show in the present invention in order to DRAM memory cell structure as the SRAM storage unit.At this for convenience of description, only at single memory cell and single detecting unit (SenseAmplifier), so have the knack of this skill person and all know to have plurality of memory cells and a plurality of detecting unit in the DRAM structure, its method of operating and this diagram associated description are identical, do not state superfluous.
The normal operating voltage of this SRAM structure of definition is Vcca at first, earlier.Under normal operation, to equal external voltage be Vccext to Vcca.And in the present embodiment, if when entering standby mode, in order to save the consumption of power, the value of operating voltage Vcca can be fallen a predetermined value from external voltage Vccext, for example, as shown in fig. 1, transfer Vccsa to after the pressure drop via dropping equipment 140, as the operating voltage Vcca that is exported.
In the structure for this 1-T SRAM, comprise that a storage unit 110, detects multiplying arrangement 120, a switching device shifter 130, a dropping equipment 140 and first-class makeup and puts 150.
And this storage unit 110 is made up of a transistor 112 and a capacitor C.One of capacitor C terminates to the source end of this transistor 112, and the other end of capacitor is then received a voltage source V
PL, this voltage source V
PLMagnitude of voltage when normal running, be about half of operating voltage Vcca value.The source end of transistor 112 is except receiving this capacitor C, and in addition, another source/drain of this transistor 112 is received a bit line (Bit Line, under be called BL), and its grid system receives a word line (Word Line, under be called WL).In addition, the base of this transistor 112 lining (Substrate) is to connect base lining bias voltage (Substrate Bias) Vbb, and when normal running, the voltage of base lining bias voltage Vbb is-1V that this helps transistor 112 at low voltage operating.In addition, be used for the magnitude of voltage of turn-on transistor 112 then to be defined as Vpp, and Vpp system comes from word line WL.
Detect 120 of multiplying arrangements and comprised a detecting unit and a PMOS transistor SAP and a nmos pass transistor SAN, and detecting unit is made up of 2 PMOS transistor P1 and P2 and 2 nmos pass transistor N1 and N2.Its connected mode is identical with general detection multiplying arrangement, be that the grid of PMOS transistor P2 and the grid of nmos pass transistor N2 are connected to bit line BL jointly, in addition, the grid of PMOS transistor P1 and the grid of nmos pass transistor N1 are connected to a paratope line (Complementary Bit Line, under be called CBL) jointly.And this two bit line of this bit line BL and paratope line CBL is in order to the circuit as the stored data of reading cells 110.
And the source end of PMOS transistor P1 and P2 is connected to one source plate/drain electrode end of another PMOS transistor SAP jointly, and in addition, another source/drain terminal of PMOS transistor P1 and P2 then is connected respectively to the source end of nmos pass transistor N1 and N2.Another source/drain terminal of nmos pass transistor N1 and N2 then is connected to the source end of another nmos pass transistor SAN jointly.Another source/drain terminal of PMOS transistor SAP is then received switching device shifter 130, and another source/drain terminal of nmos pass transistor SAN is ground connection then.
Switching device shifter 130 receives two voltage source Vcc ext and Vccsa, and in order to switch an output voltage source wherein.And as mentioned above Vccsa less than Vccext one predetermined level.And in the present embodiment, can transfer Vccext to Vccsa via dropping equipment for example 140, and the method for its actual enforcement for example can be finished via threshold voltage (Threshold Voltage) Vtn of a transistor 142, and the value of Vccsa equals Vccext reduction Vtn.The change action of switching device shifter 130 can be controlled by a control signal CTL.
At the DRAM memory cell structure as the SRAM storage unit among Fig. 1, the read operation when normal manipulation mode is done an explanation earlier.
At first, under normal manipulation mode, employed external voltage then can adopt the value of Vccext as operating voltage Vcca.The voltage V that the capacitor C of storage unit 110 is connect
PL, then be set in half of operating voltage Vcca, to quicken the operation of storage unit, the voltage of base lining bias voltage Vbb then is set at-1V, to reduce threshold voltage value.
In the pre-charging stage of reading cells 110 (Pre-charge stage) not, equalizing apparatus 150 can be charged to certain voltage with two bit line BL and CBL by the control of voltage Vg, generally speaking be half of operating voltage Vcca, and these makeups to put 150 for example be that two MOS transistor are formed, and the signal EQ of control grid is at this stage its magnitude of voltage V
EQBe high levels (logical one), in order to this two bit line is charged to predetermined level.
Then, after selecting word line WL, electric charge is promptly shared between storage unit 110 and bit line BL.If stored data are " 1 " in storage unit 110, then the current potential of bit line BL can be increased to the operating voltage Vcca greater than half, and the voltage of bit line CBL then can be reduced to half a little less than operating voltage Vcca.
Then after the nmos pass transistor SAN conducting that detects multiplying arrangement 120, just after node 122 ground connection, detect multiplying arrangement 120 and begin action, promptly can make nmos pass transistor N2 conducting and move the voltage of bit line CBL to ground connection, and because the voltage ground connection of CBL will can make PMOS transistor P1 conducting simultaneously.Will make the SAP conducting of PMOS transistor and make operating voltage Vcca be charged to Vcca by bit line BL to the capacitor of storage unit 110 this moment, is updated to former predetermined level again.
This process of reading is presented among Fig. 2 and illustrates, for example after EQ stops pre-charge, after word line WL transfers logical one to, then bit line BL can raise a part of earlier, then after nmos pass transistor SAN conducting, bit line BL will heighten level, and the capacitor C of storage unit 110 is charged to store charge again is set value.
If data stored in storage unit 110 are " 0 ", then operating process is similar.The current potential of bit line BL can be reduced to half less than operating voltage Vcca when word line WL transfers high level (logical one) to, the voltage of bit line CBL then can be a little more than a little less than half of operating voltage Vcca.
Then after the nmos pass transistor SAN conducting that detects multiplying arrangement 120, just after node 122 ground connection, detecting multiplying arrangement 120 comes into operation, promptly can make nmos pass transistor N1 conducting and the voltage of bit line BL is received ground connection, and because the voltage ground connection of BL will can make PMOS transistor P2 conducting simultaneously.Will make the SAP conducting of PMOS transistor and make bit line CBL draw high operating voltage Vcca this moment, and make bit line BL voltage minimum to dropping to, and the capacitor of storage unit 110 discharged, again the stored value " 0 " in updated stored unit 110.
Then, for the DRAM memory cell structure of present embodiment, how under (for example standby mode or sleep pattern) under the low voltage operating pattern, to preserve stored data effectively and to be described in detail at being.
In the system that uses this DRAM memory cell structure, if when not distinguishing the standby mode that reduces consumed power or further reducing the sleep pattern of consumed power, and only as low voltage operating the time, just only have low voltage operating pattern following time, then please be corresponding with reference to Fig. 1 and explanation shown in Figure 3.By the control of CS, transfer the value of operating voltage Vcca to after the step-down Vccsa value by original Vccext to switching device shifter 130.And V
PLWith V
EQValue from half of Vccext, reduce to half of Vccsa.Embodiments of the invention can utilize the voltage of the switching device shifter 130 control total system operations that increased, and then reach the purpose that reduces power consumption.
In addition, if in the system of the use DRAM memory cell structure of the embodiment of the invention, when having the standby mode that reduces consumed power or further reducing the sleep pattern of consumed power, then please refer to Fig. 1 and its Fig. 4 in order to the explanation sequential.For reducing the power consumption of total system, the DRAM memory cell structure of present embodiment only uses the source of the clock signal clk ref of an outside as clock, and all operations are all according to this outside clock signal clk ref, no longer increase clock generator, produce the clock internal signal separately.
Under general standby mode, the inverse value of messenger CS is controlled, and employed operating voltage can be by doing an action of switching between Vccext or Vccsa two values.And the V of this moment
PLWith V
EQValue, also and then switch to half of Vccext or half of Vccsa, to save power hungry.
If but under sleep pattern, then because last electric weight is low excessively, thus must maintain under the low-voltage, and be kept at the stored data of DRAM storage unit.Therefore, many factors then must be considered.
As shown in Figure 4, provide a sleep enable signal (Sleep), this sleep enable signal is used so that native system enters the enable signal of sleep pattern.After the Sleep signal enabled (Enabled), when just being positioned at high level (logical one), then operating voltage Vcca then was converted to Vccext, no longer needs step-down.This can reach for the control of the switching device shifter among Fig. 1 130 by signal Sleep.And this moment is for saving electricity consumption, and all word lines switch in the time of can be along with a reference clock CLKref low-voltage low level closes, and just is 0V voltage all.In addition, providing the base lining bias voltage Vbb of the transistor 112 of storage unit 110, also is according to the source of above-mentioned reference clock signal CLKref as clock.
In addition, in the present embodiment, the system that also proposes all DRAM memory cell structures is all with reference to same clock signal, just above-mentioned reference clock CLKref, and this reference clock is provided by outside total system, produced but not increase clock generator (Clock Generator) in addition by the DRAM memory cell structure, this needs the demand of three internal clockings different with general DRAM structure, also because so, can reduce producing the consumption of clock desired power, to reach the problem of the reduction consumed power that present embodiment institute desire solves.
The stored electric charge of capacitor C of storage unit 110 depends on the voltage difference at capacitor C two ends.The voltage vcc ext value of case of external is 3V, be 2V through the Vccsa magnitude of voltage after the pressure drop then, or outside voltage vcc ext value is 2V, is 1.5V through the Vccsa magnitude of voltage after the pressure drop then.These situations data of storage memory cells 110 effectively all still under sleep pattern.
In addition, if external voltage drops to lower situation, this is the trend of present portable electron device, for example during Vccext=1.5V, then, the operating voltage of present embodiment also has only 1.5V because switching to Vcca=Vccext, and the capacitor C other end voltage V of storage unit 110
PLIf still be half of Vcca, when just being about 0.7V, under this situation, the stored electric charge of capacitor C is Q1=C * (1.5V-0.7V) * k (k is the shared effect parameter of electric charge, Charge Sharing Effect)=C * 0.8 * k.The charge value that stores is low excessively, and probably have detection multiplying arrangement 120 and can't effectively detect stored value, and the doubt that has data to run off.
Then optionally change this moment for storage unit 110, for example the voltage V that an end of capacitor is connect
PLHalf definite value of operating voltage Vcca under the general normal manipulation mode changes into along with clock signal clk ref and changing, just voltage V
PLCan be from half (in fact be half of Vccext this moment) value wherein of 0V and Vcca along with clock signal clk ref switching.Because under sleep pattern,, do not need by V is provided can save power hungry
PLImprove the efficient of operation.And in order to the V as the pairs of bit line charging
EQValue is also along with clock signal clk ref switches to 0V or Vcca value half one of them.
Such structure if operate, has significant effect under low-voltage.For example, when supposing that this system switches to the time t1 of sleep pattern, the stored electric charge of capacitor C is Q1=C * (1.5V-0V) * k=C * 1.5 * k, and is high with original C * 0.8 * k, just do not have this moment and detects the doubt that multiplying arrangement 120 can't detect stored data.In addition, as shown in Figure 5, at same time t1, the stored electric charge of Sleep pattern of normal mode and present embodiment has tangible difference.
Certainly, the voltage V that connect of an end of the adjustment capacitor in the present embodiment
PLThe V of value and pairs of bit line charging
EQValue also is the situation that is used in non-low voltage operating, and is remarkable when just effect does not have low voltage operating.
In static RAM (1-T SRAM) structure of utilization one-transistor of the present invention, can preserve the stored data of DRAM storage unit effectively and be unlikely to run off.In addition,, can under the low-voltage situation, operate, still can keep the stored data of DRAM storage unit, and can reduce the power that whole SRAM structure operation is consumed according to SRAM structure of the present invention.
Though the present invention discloses as above with a preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention should limit with accompanying Claim.
Claims (21)
1. one kind is applicable to the compatible transistorized DRAM structure of static RAM, wherein this DRAM structure is to operate under a normal manipulation mode and a low voltage operating pattern, wherein this DRAM structure is used the foundation of a reference clock signal as operation, and wherein this DRAM structure comprises:
One storage unit is in order to storage data;
One detects multiplying arrangement, have a detecting unit, a first transistor and a transistor seconds, wherein this detecting unit is connected with a paratope line with this first transistor, this transistor seconds, a bit line, wherein this bit line and this paratope line read in order to conduct and upgrade the stored data of this storage unit, and upgrade the stored data frequency of this storage unit according to this reference clock signal; And
One switching device shifter, in order to receiving one first voltage and one second voltage, and in order to switch output both one of and be an operating voltage, wherein the level of this first voltage is higher than the level of this second voltage, wherein
When this DRAM structure during at this normal manipulation mode, this operating voltage is this second voltage, for should DRAM structure manipulating, and saving the operation consumed power,
When this DRAM structure is operated under this low voltage operating pattern, this operating voltage is this first voltage, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.
2. DRAM structure as claimed in claim 1, wherein this storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of this capacitor terminate to the 3rd transistorized source end, the other end of this capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to this bit line, the one gate terminal is then received this word line, wherein
When this DRAM structure during at normal manipulation mode, this tertiary voltage is a ratio of this operating voltage, but this tertiary voltage is less than this operating voltage,
When this DRAM structure during in this low voltage operating pattern, this tertiary voltage is then according to this reference clock signal, when this reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of this storage unit of this dynamic RAM with reduction.
3. DRAM structure as claimed in claim 2, when wherein operating when this normal manipulation mode, this tertiary voltage is half of this operating voltage.
4. DRAM structure as claimed in claim 1, wherein this transistorized base lining (Substrate) connects a base lining bias voltage (Substrate Bias).
5. DRAM structure as claimed in claim 4 wherein should provide with reference to this reference clock signal by base lining bias voltage.
6. DRAM structure as claimed in claim 1 wherein also comprises a dropping equipment, is connected to this switching device shifter and this first voltage, and exports this second voltage to this switching device shifter.
7. DRAM structure as claimed in claim 6, wherein this dropping equipment is made up of one the 4th transistor, and wherein this first voltage and this second voltage phase difference are the 4th a transistorized threshold voltage.
8. DRAM structure as claimed in claim 1, wherein this switching operation of switching device can be controlled by a control signal and select this first voltage of output or this second voltage.
9. one kind is applicable to the compatible transistorized DRAM structure of static RAM, wherein this DRAM structure is to operate under a normal manipulation mode, a standby mode and a sleep pattern pattern wherein, wherein this DRAM structure is used the foundation of a reference clock signal as operation, and wherein this DRAM structure comprises:
One storage unit is in order to storage data;
One detects multiplying arrangement, have a detecting unit, a first transistor and a transistor seconds, wherein this detecting unit is connected with a paratope line with this first transistor, this transistor seconds, a bit line, wherein this bit line and this paratope line are according to this reference clock signal in order to as reading and upgrading the stored data of this storage unit and upgrade the stored data frequency of this storage unit; And
One switching device shifter, in order to receiving one first voltage and one second voltage, and in order to switch output both one of and be an operating voltage, wherein the level of this first voltage is higher than the level of this second voltage, wherein
When this DRAM structure during at this normal manipulation mode, this operating voltage is this second voltage, for should DRAM structure manipulating, and saving the operation consumed power,
When this DRAM structure was operated under this standby mode, this operating voltage can be adjusted into this first voltage or this second voltage according to this reference clock signal;
When this DRAM structure is operated under this sleep pattern, this operating voltage can be fixed as this first voltage, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.
10. DRAM structure as claimed in claim 9, wherein this storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of this capacitor terminate to the 3rd transistorized source end, the other end of this capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to this bit line, the one gate terminal is then received this word line, wherein
When this DRAM structure during at this normal manipulation mode, this tertiary voltage is a ratio of this operating voltage, but this tertiary voltage is less than this operating voltage,
When this DRAM structure is operated under this sleep pattern, this tertiary voltage is then according to this reference clock signal, when this reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of this storage unit of this dynamic RAM with reduction.
11. DRAM structure as claimed in claim 10, when wherein operating when this normal manipulation mode, this tertiary voltage is half of this operating voltage.
12. DRAM structure as claimed in claim 9, wherein this transistorized base lining (Substrate) connects a base lining bias voltage (Substrate Bias).
13. DRAM structure as claimed in claim 12 wherein should provide with reference to this reference clock signal by base lining bias voltage.
14. DRAM structure as claimed in claim 9 wherein more comprises a dropping equipment, is connected to this switching device shifter and this first voltage, and exports this second voltage to this switching device shifter.
15. DRAM structure as claimed in claim 14, wherein this dropping equipment is made up of one the 4th transistor, and wherein this first voltage and this second voltage phase difference are the 4th a transistorized threshold voltage.
16. DRAM structure as claimed in claim 9, wherein this switching operation of switching device can be controlled by a control signal and select this first voltage of output or this second voltage.
17. DRAM structure as claimed in claim 9, wherein this switching device shifter can be controlled and fixing this first voltage of output by a sleep enable signal when entering this sleep pattern.
18. method of operating that is applicable to the compatible transistorized DRAM structure of static RAM, wherein this DRAM structure comprises that a storage unit, detects a multiplying arrangement and a switching device shifter, this DRAM structure is operated under a normal manipulation mode and a low voltage operating pattern, and wherein this method of operating comprises the following steps:
One first voltage and one second voltage are provided, and switch output both one of and be an operating voltage of this method of operating, wherein this first voltage is higher than this second voltage;
The operation signal of one reference clock signal for this method of operating is provided;
Store data in said memory cells;
Time sequence frequency according to this reference clock signal upgrades the stored data of this storage unit;
When this normal manipulation mode, it is this operating voltage that this second voltage is provided, and for should DRAM structure manipulating, saves the operation consumed power,
When operating under this low voltage operating pattern, it is this operating voltage that this first voltage is provided, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.
19. method of operating as claimed in claim 18, wherein this storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of this capacitor terminate to the 3rd transistorized source end, the other end of this capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to this bit line, the one gate terminal is then received this word line, wherein
When at this normal manipulation mode, this tertiary voltage is a ratio of this operating voltage, but this tertiary voltage is less than this operating voltage,
When in this low voltage operating pattern, this tertiary voltage is then according to this reference clock signal, when this reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of this storage unit of this dynamic RAM with reduction.
20. method of operating that is applicable to the compatible transistorized DRAM structure of static RAM, wherein this DRAM structure comprises that a storage unit, detects a multiplying arrangement and a switching device shifter, this DRAM structure is operated under a normal manipulation mode, a standby mode and a sleep pattern, and wherein this method of operating comprises the following steps:
One first voltage and one second voltage are provided, and switch output both one of and be an operating voltage of this method of operating, wherein this first voltage is higher than this second voltage;
The operation signal of one reference clock signal for this method of operating is provided;
Store data in said memory cells;
Time sequence frequency according to this reference clock signal upgrades the stored data of this storage unit;
When this DRAM structure during at this normal manipulation mode, it is this operating voltage that this second voltage is provided, for should DRAM structure manipulating, and saving the operation consumed power,
When this DRAM structure is operated, determine this first voltage or this second voltage is this operating voltage according to the clock of this reference clock signal under this standby mode;
When this DRAM structure is operated under this sleep pattern, fixing this first voltage of output is this operating voltage, for should DRAM structure manipulating, with these stored data of this storage unit of keeping this dynamic RAM.
21. method of operating as claimed in claim 20, wherein this storage unit is made up of one the 3rd transistor AND gate, one capacitor, wherein one of this capacitor terminate to the 3rd transistorized source end, the other end of this capacitor is then received a tertiary voltage, the 3rd transistorized another source/drain terminates to this bit line, the one gate terminal is then received this word line, wherein
When this DRAM structure during at this normal manipulation mode, this tertiary voltage is a ratio of this operating voltage, but this tertiary voltage is less than this operating voltage,
When this DRAM structure is when operating under this sleep pattern, this tertiary voltage is then according to this reference clock signal, when this reference clock signal is the low level of logical zero, reduce to no-voltage, keep the stored required magnitude of voltage of these data of this storage unit of this dynamic RAM with reduction.
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| CN100446122C (en) * | 2002-10-31 | 2008-12-24 | 海力士半导体有限公司 | Semiconductor memory having self updating for reducing power consumption |
| CN100449643C (en) * | 2002-12-02 | 2009-01-07 | 三星电子株式会社 | Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level |
| CN1811987B (en) * | 2005-01-14 | 2011-05-18 | 三星电子株式会社 | Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor |
| CN102332301A (en) * | 2010-07-13 | 2012-01-25 | 台湾积体电路制造股份有限公司 | Memory array and memory array method |
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| CN101188138B (en) * | 2006-11-20 | 2012-05-30 | 国际商业机器公司 | Dynamic semiconductor storage device and method for operating same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100446122C (en) * | 2002-10-31 | 2008-12-24 | 海力士半导体有限公司 | Semiconductor memory having self updating for reducing power consumption |
| CN100449643C (en) * | 2002-12-02 | 2009-01-07 | 三星电子株式会社 | Reference voltage generating circuit and internal voltage generating circuit for controlling internal voltage level |
| CN1811987B (en) * | 2005-01-14 | 2011-05-18 | 三星电子株式会社 | Bit line voltage supply circuit in semiconductor memory device and voltage supplying method therefor |
| CN101188138B (en) * | 2006-11-20 | 2012-05-30 | 国际商业机器公司 | Dynamic semiconductor storage device and method for operating same |
| CN101903954B (en) * | 2007-11-08 | 2013-03-27 | 高通股份有限公司 | Systems and methods for low power, high yield memory |
| CN101458812B (en) * | 2007-12-11 | 2012-03-28 | 株式会社东芝 | Apparatus and method for detecting update of image information |
| CN101465151B (en) * | 2007-12-17 | 2012-07-18 | 富士通半导体股份有限公司 | Memory system and control method for memory |
| CN102332301A (en) * | 2010-07-13 | 2012-01-25 | 台湾积体电路制造股份有限公司 | Memory array and memory array method |
| CN104246892B (en) * | 2012-07-10 | 2017-04-12 | 慧与发展有限责任合伙企业 | List sort static random access memory |
| TWI659420B (en) * | 2017-03-17 | 2019-05-11 | 日商東芝記憶體股份有限公司 | Semiconductor memory device |
| CN110867204A (en) * | 2018-08-28 | 2020-03-06 | 华邦电子股份有限公司 | Memory device and memory control method |
| CN110867204B (en) * | 2018-08-28 | 2021-10-15 | 华邦电子股份有限公司 | Memory device and memory control method |
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