CN1347140A - Application of heat radiator with support effect for circuit board with chip - Google Patents
Application of heat radiator with support effect for circuit board with chip Download PDFInfo
- Publication number
- CN1347140A CN1347140A CN 01134449 CN01134449A CN1347140A CN 1347140 A CN1347140 A CN 1347140A CN 01134449 CN01134449 CN 01134449 CN 01134449 A CN01134449 A CN 01134449A CN 1347140 A CN1347140 A CN 1347140A
- Authority
- CN
- China
- Prior art keywords
- chip
- thermal conductance
- circuit board
- thin plate
- fin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
An application of heat radiator with supporting effect for the circuit board with chip is disclosed, which is characterized by high heat radiating effect, light weight, thin thickness and eliminating warpage and twist. Said heat radiator is made by using a frist bonding sheet which is a fibre reinforced resin to combine the first heat conducting sheet (heat radiating sheet) with the second one, and using a second bonding sheet which is single-layer adhesive layer or a stack of several adhesive layers to combine said heat radiator with circuit board having an opening for installing chip.
Description
Technical field
The present invention relates to a kind of processing procedure of Electronic Packaging, comprise the encapsulation of single-chip and multicore sheet, particularly a kind of making is with the heat sinking type chip method for packing of fin (heat spreader), and this fin also has support effect (stiffener) simultaneously.
Background technology
Along with semi-conductor industry is constantly progressive, electronic system and Electronic Packaging are typically designed to and use minimum space (space) as far as possible in practicalities.Therefore the space of bearer circuit should utilize along with technological progress has become a valuable source as far as possible; For reaching this purpose, the downsizing circuit then be can yet be regarded as and is apt to use effective ways in space, and it can increase the speed of service, reduces the advantage that noise and other manifested.So downsizing is all quite satisfactory in the application facet of many electronic products, as the application of aspects such as airborne vehicle, automobile, mobile phone, laptop computer or taking videocorder.Yet heat dissipation problem also displays along with downsizing, and especially the increase of assembly causes the heat that produces, also increases along with increase transistorized number on single semiconductor subassembly.
The form of one of semiconductor die package comprises one or more chip and is connected on the substrate, can be a ceramic substrate, this ceramic substrate with ceramic material as insulating barrier; Or a plastic base, this plastic base with plastic basis material as insulating barrier.Traditionally this base plate for packaging is called a chip carrier (chip carrier), usually with its configuration and be connected in a Printed Circuit Card (printed circuit card) or a printed circuit board (PCB) (printed circuit board), chip then can be connected on the substrate in many ways.Generally the most common as beating gold thread mode (wire bonding), electrically connect to superfine little gold thread of substrate tie point by the chip assembly place; Another kind then is to cover chip (flip chip) mode of connection, and it is to electrically connect with the entity contact of projection (solderbumps) as chip.
Various different modes have been developed and have been used on the cost plastic base low than ceramic substrate chip being set.Be considered in the running of chip, to possess more key advantages mainly due to plastic base always, comprise high current capacity, in low-k and the low inductance and the electric capacity etc. of short operation time of delay (delaytime) than ceramic substrate.Yet the high-temperature stable degree of plastic base still has problems, and the development of existing plastic base is caused very big challenge.The settling mode of one then is to use a kind of Open Side Down (cavity down) Chip Packaging, comprise a base plate for packaging with the opening (opening) that can accept chip, and post a heat radiating metal piece or a fin, and Printed Circuit Card that its openend is faced or printed circuit board (PCB) in chip bottom.
Fig. 1 shows the downward Chip Packaging mode of traditional typical plastics base openings (cavitydown plastic chip carrier).The encapsulation assembling constitutes 100 and comprises a plastics circuit board 101, and this plastics circuit board 101 is provided with the heat radiating metal piece or the fin 103 of a recess (cavity) 102 and a bond layer (bonding layer) 104 and substrate 101 bonds.The electricity of one routine wall is led or/and 105 on thermal conductance layer can be used as the circuit layer that connects on fin 103 and the substrate 101, to promote thermoelectricity capability.106 positions of chip and paste on fin 103 in recess 102.107 of gold threads of conduction are used for the electric connection of chip 106 and substrate 101.After beating the gold thread step, 102 of recess are filled out with sealing 108 (encapsulant) covering protection conduction gold thread 107 and chip 106, destroy to avoid environmental corrosion.In addition, the position is at the outermost external connecting pin 109 of substrate, then as the electric connection of substrate 101 with printed circuit board (PCB) 110.Described external connecting pin can be conductive pin (pins), tin ball or tin post, be applied to plastics pin array (plastic pin grid array respectively, PPGA), baton round array (plastic ballgrid array, PBGA) or plastic cylinder array (plastic column grid array, packaged type PCGA).
U.S. Pat 5,357,672 have disclosed a kind of easily Open Side Down chip plastic carrier (cavity down plastic chip carrier) processing procedure.This method uses preimpregnation material (prepreg) as the bond layer, that is bond layer 104 in Fig. 1 or the bond layer 206 among Fig. 2.Yet according to practical experience, the chip carrier (chip carrier) that this method is made is in hot pressing, and the preimpregnation material often has the phenomenon generation that causes warpage because of cure shrinkage.
Chip Packaging is assemblied in the processing procedure in order to overcome plastic base Open Side Down, and warpage that is taken place or twisted phenomena can add a robust support thing (stiffener) or more copper layer (copper layer) sometimes.Fig. 2 shows an exemplary, it is another plastic base Open Side Down Chip Packaging mode, one encapsulation assembling constitutes 200, also can be described as super ball array package (superBGA), and it comprises copper layer (internal copper layer) 202 in a circuit board 201 and; This circuit board 201 includes opposite first 201a and second surface 201b, and first surface 202a of copper layer 202 utilizes an adhesion layer 203 to be connected with the second surface 201b of circuit board 201 in this.At described circuit board 201 and the copper layer 202 middle opening that forms, make a recess (cavity) 204 penetrate this circuit board 201 and copper layer 202.One fin 205 utilizes second 202b of an adhesion layer 206 attached to copper layer 202, to increase radiating effect.One chip 207 is placed in recess 204, and is attached on this fin 205 by a heat conduction adhesion layer 208.Conduction gold thread 209 is then as the line of chip 207 with circuit board 201.After beating the gold thread step, 204 of recess are filled out with sealing 210 (encapsulant) covering protection conduction gold thread 209 and chip 207, destroy to avoid environmental corrosion.And tin ball 211 is located at the appropriate location on the first surface 201a of circuit board 201, electrically connects with printed circuit board (PCB) 212.Other one common structure then is that the extra heat abstractor (heat sink) that adds also can directly be attached on the second surface 205b of fin 205, with the radiating effect of Da Gengjia.
U.S. Pat 6,034,427 have also disclosed a kind of tool supporter Open Side Down BGA processing procedure is pasted a robust support thing (stiffener) on a circuit board by a preimpregnation material (prepreg) earlier, and then with an adhesion layer fin is attached on this robust support thing.The fin that this patent is used is copper ground (copper base material), that is common soft materials (soft material) such as copper or copper alloy, and the cure shrinkage of adhesion layer can make and causes warping phenomenon at the hot pressing fin with containing in the circuit boards of supporter.
U.S. Pat 6,060,778 have also disclosed the processing procedure of a kind of simple and easy Open Side Down BGA, and it has good radiating effect, low weight, minimal thickness and low manufacture cost and other advantages.This patent has been instructed and has been used the first thermal conductance thin plate to stick together at circuit board earlier, and then is connected with the circuit board that contains the first thermal conductance thin plate with one second thermal conductance thin plate (that is fin).The method is illustrated among Fig. 7 of this patent specification.Yet this patent also can run into the problem with aforementioned U.S. Pat 6,034,427: that is the warping phenomenon that causes in the processing procedure that is difficult to prevent.
Summary of the invention
For this reason, the present invention provides a kind of manufacturing plastic base Open Side Down the Chip Packaging mode, and it has, and good radiating effect, weight are low, thin thickness, the warpage of preventing and twisted phenomena and low manufacture cost and other advantages.
According to method proposed by the invention, at first two thermal conductance thin plates are fitted and form a fin, again this fin is engaged with a circuit board that Open Side Down (or claiming base plate for packaging), obviously be different from U.S. Pat 6,034,427 and US6,060,778 method that is proposed, two pieces of patents are stated according to this, system all engages with a thermal conductance thin plate elder generation and a plastic base, and circuit board and another thermal conductance thin plate of this being pasted with a thermal conductance thin plate engage again.Another does not obviously exist together again, be that the present invention uses the preimpregnation material as the bond layer, be then to use the adhesion material of non-preimpregnation material to fit between substrate and thermal conductance thin plate as the bond layer, but it is opposite, U.S. Pat 6,034,427 methods that proposed, then the adhesion material that uses non-preimpregnation material between two thermal conductance thin plates then uses fitting as the bond layer of preimpregnation material as the bond layer between substrate and thermal conductance thin plate.According to method proposed by the invention, two or more thermal conductance thin plates are fitted formed fin as the bond layer with the preimpregnation material, because of having the high mechanical properties characteristic, therefore when fitting,, available to prevent that warpage or twisted phenomena from taking place as supporter with circuit board.
Purpose of the present invention provides a kind of firm fin of tool support effect to be applied to circuit board with chip, has that good radiating effect, weight are low, a thin thickness and do not have warpage and advantage such as twisted phenomena.
According to an aspect of the present invention, the fin with support effect that is provided is applied to circuit board with chip, may further comprise the steps: a plastic circuit substrate with opposite first and second surface a) is provided, and this circuit substrate includes at least more than one can be for the opening that loads chip; B) provide first a thermal conductance thin plate (thermally conductive sheet) with opposite first and second surface; C) provide second a thermal conductance thin plate with opposite first and second surface, this second thermal conductance thin plate includes at least more than one can be for the opening that loads chip; D) with one first bond thin slice the first surface of the described first thermal conductance thin plate and the second surface of the second thermal conductance thin plate are connected, this first bond thin slice is made up of the preimpregnation material (prepreg) of a fiber-reinforced resin (fiber-reinforced resin); E) with the second made bond thin slice of a non-preimpregnation material (non-prepreg) first surface of the described second thermal conductance thin plate and the second surface of circuit substrate are connected.
According to a further aspect in the invention, the fin with support effect that is provided is applied to circuit board with chip, may further comprise the steps: a plastic circuit substrate with opposite first and second surface a) is provided, this circuit substrate and can include at least more than one can be for the opening that loads chip; B) provide a thermal conductance thin plate (thermally conductive sheet) with opposite first and second surface; C) provide a thermal conductance sheet pack compound with opposite first and second surface, this thermal conductance sheet pack compound and can include at least more than one can be for the opening that loads chip; D) with one first bond thin slice the first surface of described thermal conductance thin plate and the second surface of described thermal conductance sheet pack compound are connected, this first bond thin slice is made up of the preimpregnation material of a fiber-reinforced resin (fiber-reinforced resin); E) with the second made bond thin slice of a non-preimpregnation material (non-prepreg) first surface of described thermal conductance sheet pack compound and the second surface of circuit substrate are connected.
In addition, but the invention provides the first bond thin slice (bonding sheet) of a bond first thermal conductance thin plate (thermally conductivesheet) and the second thermal conductance thin plate, to form a firm fin, and this first bond thin slice can be a fiber-reinforced resin, but this second thermal conductance thin plate has the opening of a holding electronic chip.
In addition, but the invention provides the second bond thin slice (bonding sheet) of a bond one plastic circuit board and a firm heat radiating fin structure, this plastic circuit board have one can ccontaining chip opening.Described bond thin slice is made up of individual layer adhesion layer or the superimposed institute of multilayer adhesion layer, described adhesion layer sticks together material, short thin slice by one fills the stick together material, fiber of (flake-filled) and fills stick together material or the shot-like particle of (fiber-filled) and fill the material that sticks together of (particle-filled) and formed, and non-be the preimpregnation material.
Below in conjunction with accompanying drawing the object of the invention, feature and effect are elaborated.Certainly, the present invention can multitude of different ways implement, and has more than to be limited to content described in this specification.Explanation hereinafter is disclosed quite complete, also can express the spirit that the present invention will disclose fully.
Description of drawings
Fig. 1 is the schematic diagram of the downward Chip Packaging mode of conventional art split shed.
Fig. 2 is the schematic diagram of tool supporter Open Side Down Chip Packaging mode in another conventional art.
Fig. 3 is the schematic diagram that forms each layer be pasted with heat radiating fin structure Open Side Down circuit board in the first embodiment of the invention.
Fig. 4 is the schematic diagram of heat radiating fin structure in another embodiment of the present invention.
Fig. 5 forms the schematic diagram that has as knife-edged outstanding linking part (sharped-edge connector) structure in another embodiment of the present invention.
Fig. 6 is the schematic diagram that forms fin with a plurality of thermal conductance thin plates in another embodiment of the present invention Open Side Down board structure of circuit.
Forming in Fig. 7 institute another embodiment of the present invention can be for the schematic diagram that has a fin Open Side Down circuit board of multicore sheet encapsulation.
The drawing reference numeral explanation: 1,30,32,101, the 201-substrate; 2,11,27,33, the 34-opening; 3-stratum; 4-substrate first surface; 5-substrate second surface; The 6-first thermal conductance thin plate; The 7-first thermal conductance thin plate first surface; The 8-first thermal conductance thin plate second surface; 9-sticks together reinforcing agent; The 10-second thermal conductance thin plate; The 12-second thermal conductance thin plate first surface; The 13-second thermal conductance thin plate second surface; 14,15,29-sticks together reinforcing agent; 16,19,31,36-bond thin slice; 17,28, the 35-heat radiating fin structure; The 17a-protective layer; 18,18a, 105-electricity lead or/and the thermal conductance layer; The linking part of 20-tool sharp end; The 22-first thermal conductance thin plate; The 23-second thermal conductance thin plate; The 25-first bond thin slice; 26-thermal conductance sheet pack compound; 100,200-encapsulation assembling constitutes; 101, the 201-substrate; 102, the 204-recess; 103, the 205-fin; 104,206-bond layer; 106, the 207-chip; 107, the 209-gold thread; 108, the 210-sealing; 109, the 211-connecting pin; 110, the 212-circuit board; 202-copper layer; 202a-copper layer first surface; 202b-copper layer second surface; 203,206, the 208-adhesion layer; 205a-fin first surface; 205b-fin second surface.
Embodiment
The present invention a kind of firm fin of tool support effect be applied to circuit board with chip, particularly relevant for the heat radiating type integrated circuit of on processing procedure, prevent warpage and twisted phenomena Open Side Down chip encapsulating manufacturing procedure.Simultaneously, this encapsulates the effect that also can possess good heat radiating.Yet diagram of the present invention only is simple declaration, is not to describe according to physical size, that is does not reflect in the chip carrier structure, the actual size of each level and characteristic.
See also Fig. 3, be first embodiment of the invention.One chip plastic carrier substrate 1 at first is provided, and this substrate 1 comprises an opening 2 and some stratum 3.This substrate 1 can include wired circuit layer, through hole (through-holes), via (conductive through-holes) or the interlayer hole (via) etc. that separate with organic insulator as traditional; Electrode on stratum 3 surfaces (or claiming that bond refers to bonding finger) and protective layer; Electrode on stratum's first surface 4 (or claiming weld pad, landing pad), barrier (dam) and protection coating; Weld pad on the second surface 5 and protection coating etc.One first thermal conductance thin plate (thermally conductivesheet) 6 (or claiming fin), this first thermal conductance thin plate 6 can be copper or copper alloy thin plate, the aluminum or aluminum alloy that copper that the aluminum or aluminum alloy that copper that graphite fibre is filled or copper alloy, graphite fibre are filled, silicon-carbide particle are filled or copper alloy, silicon-carbide particle are filled etc., and can all carry out chemistry or physics alligatoring (roughen) step with second surface 8 at its first surface 7.This first surface 7 is to be formed with one to stick together reinforcing agent 9 (adhesion promoter), is preferably an oxide layer or couplant (coupling agent), to increase its tackness.This couplant can comprise silicon alms bowl couplant (silane), titanium couplant, cobalt couplant or aluminium couplant etc.One second thermal conductance thin plate 10 (or claiming internal layer thermal conductance thin plate), it is provided with an opening 11 and penetrates wherein, similarly, this second thermal conductance thin plate 10 can be copper or copper alloy thin plate, the aluminum or aluminum alloy that copper that the aluminum or aluminum alloy that copper that graphite fibre is filled or copper alloy, graphite fibre are filled, silicon-carbide particle are filled or copper alloy, silicon-carbide particle are filled etc., and can all carry out chemistry or physics alligatoring step at its first surface 12 and second surface 13, and this first surface 12 all is formed with second surface 13 and sticks together reinforcing agent 14 and 15.Yet the described reinforcing agent that sticks together has more than and is defined as oxide layer of the present invention or couplant.The first surface 7 of this first thermal conductance thin plate 6 and the second surface 13 of the second thermal conductance thin plate 10 fit with a bond thin slice 16.Described bond thin slice 16 is preferably a fiber-reinforced resin, as preimpregnation material (prepreg) etc.By heat-press step, here a firm fin 17 (stiff heatspreader element) that comprises the first thermal conductance thin plate 6 and the second thermal conductance thin plate 10 is finished in.After bond thin slice 16 (preimpregnation material) hot pressing sclerosis, this heat radiating fin structure 17 promptly becomes a firm sandwich structure.18 of one thermal conductance or conductance layers can be used as the hot binding of the first thermal conductance thin plate 6 and the second thermal conductance thin plate 10, more to promote radiating effect.In addition, the first thermal conductance thin plate 6 and the second thermal conductance thin plate 10 can be configured to equal thickness, and this symmetry sandwich structure can get best warpage and the distortion effect of preventing.
Another execution mode as shown in Figure 4, wherein a thermal conductance or conductance layer 18a can be thin copper or copper alloy layer etc., can be formed at the downside surface of heat radiating fin structure 17.Certainly, before forming thermal conductance or conductance layer 18 or 18a, can be earlier the downside surface of heat radiating fin structure 17 be carried out that acid is cleaned or electricity slurry cleaning steps such as (plasma cleaning).Second surface 8 at the first thermal conductance thin plate 6 can be formed with the protective layer (not shown); epoxy resin (epoxy resin), diamond film or class diamond carbon film etc. as nickel, gold or heat conduction particle filling; and before forming protective layer, the second surface 8 of this first thermal conductance thin plate 6 can carry out physics or chemical roughen earlier.One second bond thin slice 19 is located between the second surface 5 of the first surface 12 of the second thermal conductance thin plate 10 and substrate 1.Through the pressing step, after the described second bond thin slice 19 hardens with heating or mode such as radiation, heat radiating fin structure 17 just with second surface 5 bonds of substrate 1.Through sidewall platings, chip setting, beat gold thread, fill sealing and outer terminal connect general conventional process such as pin is provided with after, Chip Packaging that Open Side Down is as shown in Figure 2 assembled formation 200 and just can be formed in this way.
According to method proposed by the invention, as shown in Figure 4, heat or conductance layer 18a have carried out the first thermal conductance thin plate 6 and the second thermal conductance thin plate 10 the heat biography and have been connected, and can further promote radiating effect; But U.S. Pat 6,034,427 and US 6,060,778 proposition method, and can't obtain the advantage that this promotes radiating effect, because of it engages a thermal conductance thin plate and a circuit board earlier, but not method as proposed by the present invention engages two or more thermal conductance thin plates earlier, then just engages with a circuit board.
Described chip carrier plastic base 1 can be a single or multiple lift substrate, described substrate is to be made up of with the conductive material intermeshing dielectric material (for forming the usefulness of insulating barrier), described dielectric material can be an organic material, the organic material of the organic material material of fibre strengthening (fiber-reinforced) or shot-like particle reinforcement (particle-reinforced) is formed, as epoxy resin, poly-ethanamide (polyimide), two butadiene dilute acid vinegar imines/three nitrogen traps (bismaleimide triazine), hydrocyanic ester class (cyanate ester), polyphenyl ring tetraene (polybenzocyclobutene) or its glass fiber composition.This plastic chip carrier substrate 1 be preferably in heat radiating fin structure 17 bonds before finish in advance be formed at substrate 1 so that via can pass through, the Chip Packaging assembling constitutes and form that Open Side Down.With the present invention, when substrate 1 during with heat radiating fin structure 17 bonds, because substrate solidified forming in advance, the cure shrinkage (cure shrinkage) that therefore forms during the substrate 1 is moved, and can avoid causing any warpage or twisted phenomena because of cure shrinkage.
Please consult Fig. 1 again, fin 103 is generally copper or copper alloy material.As everyone knows, when the practical operation temperature was between 300-400 ℃, copper sheet had ruckbildung.If therefore the copper thickness of fin 103 is too thin, when being lower than 0.5mm, then when the described plastic base Chip Packaging of manufacturing is assembled the fin 103 that constitutes in 100, will be difficult to control because of fin 103 easy deformation, cause greatly puzzlement on the processing procedure.Therefore the thickness of this copper fin 103 should be chosen in more than the 0.5mm at least to good.Yet during thin if necessary fin 103 (thickness is thinner than 0.5mm), one forms fin 103 for good to the copper alloy with the tool higher mechanical strength, and the preferably is more than the thickness 0.1mm.The interpolation alloying component ratio of this copper alloy should account for below 5% of total copper alloy weight, as C194 or C305 copper alloy; The preferably, it adds the alloying component ratio should account for below 0.5% of total copper alloy weight, as the C151 copper alloy, will make copper alloy have lower thermal conductance (thermally conductivity) because of adding higher alloying component.It is noted that at this " copper " of the present invention is meant and is difficult to avoid alloying component content at the copper alloy of part by weight below 0.1%.
Yet when using sandwich type heat radiating fin structure 17 of the present invention, the thickness that can remove copper radiating rib needs the restriction more than 0.5mm.For instance, the first thermal conductance thin plate 6 that thickness is all 0.254mm promptly can combine formation fin 17 by the preimpregnation material with the second thermal conductance thin plate 10, it constitutes 200 to forming the encapsulation assembling, enough hardness and the thickness of tool, and can overcome the warping phenomenon that forms in the chip carrier processing procedure; At this moment, the bond layer 16 between the first thermal conductance thin plate 6 and the second thermal conductance thin plate 10 also can be made up of two or more preimpregnation materials, more can increase the mechanical strength of heat radiating fin structure.The preferably, this first thermal conductance thin plate 6 is to have identical thickness with the second thermal conductance thin plate 10, forms the warping phenomenon in the chip carrier processing procedure to preventing, and will have optimum efficiency.
For making heat radiating fin structure 17 can prevent environmental attack completely, the sidewall around fin 17 can be covered with a protective layer 17a, the epoxy resin of filling as nickel, gold, heat conduction particle, diamond film, class diamond carbon film etc.When protective layer 17a overlays on the sidewall all around of fin 17,, also can promote radiating effect simultaneously because of surface area increases.
In embodiments of the present invention, described bond thin slice 19 is made up of an adhesion layer or superimposed many adhesion layers.This adhesion layer is sticked together the material that sticks together that sticks together material or shot-like particle filling (particle-filled) that sticks together material, short fiber filling (fiber-filled) of material, short thin slice filling (flake-filled) as one.And because of braided fiber is not filled in described adhesion material, so adhesion layer of the present invention also with regard to non-for the preimpregnation material.This adhesion layer can be one (1) resin, is as epoxy resin, poly-ethanamide resin (polyimide resin), polyurethane (polyurethane) or acrylic resin (acrylic) etc.; (2) different amount Molecularly Imprinted Polymer (copolymer) is as epoxy-acrylic resin (epoxy-acrylic resin), epoxy-butadiene resin (epoxy-butadiene resin) or epoxy-carbamate resins (epoxy-urethane) etc.; (3) polymer is mixing, as epoxy resin/halogenatedpolyhydroxystyrene blend or the mixing thing of epoxy resin/phenol resin (epoxyresin/phenolic resin blend) etc.Described organic material more can be through halogen, silicones (silicone) or the phosphite character that makes alterations such as (phosphite).Described short fiber (short fiber) is made with metal, organic or inorganic material, as tungsten short fiber, aramid short fiber or staple glass fibre etc., can insert described organic material to increase mechanical strength and to lower the thermal coefficient of expansion of adhesion layer.For reaching same purpose; short thin slice (flake) or shot-like particle can make an addition to organic material; short thin slice can be as silver-colored thin plate or graphite flake (graphite), and shot-like particle such as tripoli particle (silica particles), barium sulfate particle, clay (clay), calcium carbonate, milamine particles, polystyrene (polystyrene), copper particle or silver-colored particle etc.Described adhesion layer also can comprise other additive, as chemical catalyst, antioxidant, rheological agent (reological agent), coupling agent or colouring agent (color agent) etc.
Warpage or the twisted phenomena of described selection of sticking together material when lowering the chip carrier of making that Open Side Down is extremely important.Now in the industry, sticking together material and mainly be with heat curing-type (thermalsetting) resin is main flow.Typical thermosetting resin is to solidify in higher temperature, cools off in the room temperature.Therefore, the preferably, the adhesion layer material is enough soft (that is the low mechanical index of tool, mechanical modulus), material can dilatating and deformable with the cure shrinkage of compensation in curing schedule.Normal, reduce the thermal coefficient of expansion (CTE) of adhesion layer, and the processing forward part solidifies this thermosetting resin, will help to such an extent that cause the good bond effect of low warpage.But the preimpregnation material of the high mechanical index of tool but is difficult to the bond effect that provides good concerning Open Side Down chip carrier in fact.For reaching good bond effect, the loading of too high filling material and the higher engineering properties of tool, or the loading of too low filling material all must be avoided with the situation that higher thermal coefficient of expansion is provided.In addition, the thermal coefficient of expansion of adhesion layer is preferably in below 150ppm/ ℃, and the preferably is below 100ppm/ ℃, and 50ppm/ ℃ be best.
In preferred embodiment of the present invention, the described first bond thin slice 16 and the second bond thin slice 19 are not limited to Any shape or structure.
In another preferred embodiment of the present invention, heat radiating fin structure can be provided with as knife-edged outstanding linking part (sharped-edge connector).As shown in Figure 5, the linking part 20 as some blades are sharp is formed on the first surface 12 of the second thermal conductance thin plate 10, and this first surface 12 also is covered with one and sticks together reinforcing agent 14, as oxide layer or couplant etc.With hot pressing mode,, sandwich type heat radiating fin structure 17 is engaged with substrate 1 by bond thin slice 19.Simultaneously, respectively these some knife-edged linking parts 20 also penetrate bond thin slice 19, and with the second surface 5 of substrate 1 on predetermined contact mat (contact pad) (not shown) link.Certainly, also bond thin slice 19 can be holed at coupling position with laser drill or machine drilling mode before the joint in advance, then will more help linking part 20 to penetrate bond thin slice 19 and link with predetermined contact mat.And described respectively these some knife-edged linking parts 20 are electrical conductance or thermal conductance, and can be Any shape and structure.The binding of this type can make heat radiating fin structure 17 participate in playing the part of role as " ground connection ", and a heat conduction path is provided, and can conduct the heat energy that chip internal produces.So, can promote described plastic base Open Side Down the pyroelectricity of chip carrier.
In another preferred embodiment of the present invention, heat radiating fin structure can use two or more thermal conductance thin plates.As shown in Figure 6, the second thermal conductance thin plate 23 utilizes the first bond thin slice 25 and another second thermal conductance thin plate 23 to fit, and formation thermal conductance sheet pack compound 26, this thermal conductance thin plate 26 and have can ccontaining chip opening 27, another first bond thin plate 25 of thermal conductance sheet pack compound 26 mats combines with the first thermal conductance thin plate 22, to form heat radiating fin structure 28.One sticks together reinforcing agent 29, and as oxide layer or couplant, the outer surface that can be formed at each thermal conductance thin plate 22,23 is to increase its tackness.This heat radiating fin structure 28 can combine with plastic circuit substrate 30 by the second bond thin slice 31, and forms the plastic chip carrier that Open Side Down.Wherein the first bond thin slice 25 is the preimpregnation material, and the second bond thin slice 31 is formed by individual layer adhesion layer or superimposed multilayer adhesion layer, and this adhesion layer can be one and sticks together the material that sticks together that sticks together material or granular filling that sticks together material, fiber filling of material, short thin slice filling.
In another preferred embodiment of the present invention, described chip carrier is not limited to single-chip or the encapsulation of multicore sheet.Wherein a typical multicore sheet packaged type as shown in Figure 7, a circuit substrate 32 comprises two openings 33,34, respectively this opening all each can install a chip.With hot pressing mode, with bond thin slice 36, heat radiating fin structure 35 is engaged with circuit substrate 32, to make a multi-chip carrier.
In preferred embodiment of the present invention, when described chip carrier is in the industry cycle produced in batches, can sandwich type fin panel (panel) be bonded on the circuit substrate panel with the bond thin slice.And described panel can be Any shape or structure, as strip (strip) etc.
In preferred embodiment of the present invention, described chip carrier is not limited to semiconductor die package, so also can be applicable to electronic building brick, optical assembly or the photoelectric subassembly etc. of other chip kenel (chip type), for example resistance (resistor), oscillator (oscillators), lasing fluorescence diode (laser diodes), optical inductor (optical sensors) and thermal sensor (thermal sensors) etc.
In sum, the present invention has disclosed a kind of fin with support effect and has been applied to circuit board with chip, can on processing procedure, prevent warpage or twisted phenomena, and the processing procedure of the good tackness between circuit layer, high heat resistance and good reliability is provided.
Certainly, the above only is the structure of circuit substrate of the present invention and processing procedure preferred embodiment, is not in order to restriction the present invention.Any those of ordinary skill in the art all should belong to scope of the present invention in the modification of making without prejudice to spirit of the present invention, so protection scope of the present invention is when classifying foundation as with claims.
Claims (14)
1, a kind of fin with support effect is applied to circuit board with chip, may further comprise the steps:
(a) provide a plastic circuit substrate with opposite first and second surface, this circuit substrate includes at least more than one can be for the opening that loads chip;
(b) provide first a thermal conductance thin plate (thermally conductive sheet) with opposite first and second surface;
(c) provide second a thermal conductance thin plate with opposite first and second surface, this second thermal conductance thin plate includes at least more than one can be for the opening that loads chip;
(d) with one first bond thin slice the first surface of the described first thermal conductance thin plate and the second surface of the second thermal conductance thin plate are connected, this first bond thin slice is made up of the preimpregnation material (prepreg) of a fiber-reinforced resin (fiber-reinforced resin);
(e) with the second made bond thin slice of a non-preimpregnation material (non-prepreg) first surface of the described second thermal conductance thin plate and the second surface of circuit substrate are connected.
2, the fin with support effect as claimed in claim 1 is applied to circuit board with chip, and the wherein said first thermal conductance thin plate or the second thermal conductance thin plate are metal material.
3, the fin with support effect as claimed in claim 1 is applied to circuit board with chip, and the wherein said first thermal conductance thin plate is the metal material of fibre strengthening or particle strengthening.
4, the fin with support effect as claimed in claim 1 is applied to circuit board with chip, and the wherein said second thermal conductance thin plate is the metal material of fibre strengthening or particle strengthening.
5, the fin with support effect as claimed in claim 1 is applied to circuit board with chip, and the wherein said first bond thin slice is superimposed by single or multiple lift preimpregnation material (prepreg).
6, the fin with support effect as claimed in claim 1 is applied to circuit board with chip, and wherein this second bond thin slice is made up of the single or multiple lift adhesion layer.
7, the fin with support effect as claimed in claim 6 is applied to circuit board with chip, and wherein this adhesion layer is that short fiber is filled the material of sticking together that (short fiber-filled), thin slice filling (flake-filled) or shot-like particle are filled (particle-filled).
8, a kind of fin with support effect is applied to circuit board with chip, may further comprise the steps:
(a) provide a plastic circuit substrate with opposite first and second surface, this circuit substrate and can include at least more than one can be for the opening that loads chip;
(b) provide a thermal conductance thin plate (thermally conductive sheet) with opposite first and second surface;
(c) provide a thermal conductance sheet pack compound with opposite first and second surface, this thermal conductance sheet pack compound and can include at least more than one can be for the opening that loads chip;
(d) with one first bond thin slice the first surface of described thermal conductance thin plate and the second surface of described thermal conductance sheet pack compound are connected, this first bond thin slice is made up of the preimpregnation material of a fiber-reinforced resin (fiber-reinforced resin);
(e) with the second made bond thin slice of a non-preimpregnation material (non-prepreg) first surface of described thermal conductance sheet pack compound and the second surface of circuit substrate are connected.
9, the fin with support effect as claimed in claim 8 is applied to circuit board with chip, and the wherein said thermal conductance thin plate system that coincides forms as the pressing of adhesion layer institute with the first bond thin slice at least two above thermal conduction plates.
10. the fin with support effect as claimed in claim 8 is applied to circuit board with chip, and wherein said thermal conductance thin plate is a metal material.
11, the fin with support effect as claimed in claim 8 is applied to circuit board with chip, and wherein said thermal conductance thin plate is the metal material of fibre strengthening or particle strengthening.
12, the fin with support effect as claimed in claim 8 is applied to circuit board with chip, and the wherein said first bond thin slice is superimposed by single or multiple lift preimpregnation material (prepreg).
13, the fin with support effect as claimed in claim 8 is applied to circuit board with chip, and wherein this second bond thin slice is made up of the single or multiple lift adhesion layer.
14, the fin with support effect as claimed in claim 13 is applied to circuit board with chip, and wherein this adhesion layer is that short fiber is filled the material of sticking together that (short fiber-filled), thin slice filling (flake-filled) or shot-like particle are filled (particle-filled).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01134449 CN1187805C (en) | 2001-11-02 | 2001-11-02 | Application of heat radiator with support effect for circuit board with chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01134449 CN1187805C (en) | 2001-11-02 | 2001-11-02 | Application of heat radiator with support effect for circuit board with chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1347140A true CN1347140A (en) | 2002-05-01 |
| CN1187805C CN1187805C (en) | 2005-02-02 |
Family
ID=4672499
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01134449 Expired - Fee Related CN1187805C (en) | 2001-11-02 | 2001-11-02 | Application of heat radiator with support effect for circuit board with chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1187805C (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100388447C (en) * | 2004-12-20 | 2008-05-14 | 全懋精密科技股份有限公司 | Semiconductor structured chip embedded structure of base plate and method of preparation |
| US7727807B2 (en) | 2006-08-11 | 2010-06-01 | Dongbu Hitek Co., Ltd. | Semiconductor device |
| CN101459147B (en) * | 2007-12-14 | 2011-04-20 | 三星电子株式会社 | Heat radiation fin, encapsulation piece comprising the heat radiation fin and encapsulation method |
| CN102543905A (en) * | 2010-12-22 | 2012-07-04 | 矽品精密工业股份有限公司 | Semiconductor package and method of manufacturing the same |
| CN102664170A (en) * | 2012-04-19 | 2012-09-12 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| WO2021208322A1 (en) * | 2020-04-13 | 2021-10-21 | 烽火通信科技股份有限公司 | Multi-chip heat-dissipating packaging structure and packaging method |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800204B (en) * | 2009-02-11 | 2012-01-11 | 日月光半导体制造股份有限公司 | Semiconductor sealing structure with model lock and radiating fin thereof |
-
2001
- 2001-11-02 CN CN 01134449 patent/CN1187805C/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100388447C (en) * | 2004-12-20 | 2008-05-14 | 全懋精密科技股份有限公司 | Semiconductor structured chip embedded structure of base plate and method of preparation |
| US7727807B2 (en) | 2006-08-11 | 2010-06-01 | Dongbu Hitek Co., Ltd. | Semiconductor device |
| CN101459147B (en) * | 2007-12-14 | 2011-04-20 | 三星电子株式会社 | Heat radiation fin, encapsulation piece comprising the heat radiation fin and encapsulation method |
| CN102543905A (en) * | 2010-12-22 | 2012-07-04 | 矽品精密工业股份有限公司 | Semiconductor package and method of manufacturing the same |
| CN102543905B (en) * | 2010-12-22 | 2014-12-24 | 矽品精密工业股份有限公司 | Semiconductor package and method of manufacturing the same |
| CN102664170A (en) * | 2012-04-19 | 2012-09-12 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| CN102664170B (en) * | 2012-04-19 | 2015-06-17 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| WO2021208322A1 (en) * | 2020-04-13 | 2021-10-21 | 烽火通信科技股份有限公司 | Multi-chip heat-dissipating packaging structure and packaging method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1187805C (en) | 2005-02-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6627997B1 (en) | Semiconductor module and method of mounting | |
| US6475327B2 (en) | Attachment of a stiff heat spreader for fabricating a cavity down plastic chip carrier | |
| US6784541B2 (en) | Semiconductor module and mounting method for same | |
| CN1092397C (en) | High performance, low cost multi-chip module package | |
| US7115444B2 (en) | Semiconductor device with improved heat dissipation, and a method of making semiconductor device | |
| US7900809B2 (en) | Solder interconnection array with optimal mechanical integrity | |
| US7719021B2 (en) | Light efficient LED assembly including a shaped reflective cavity and method for making same | |
| US20020180035A1 (en) | Semiconductor package with heat sink | |
| US20080006936A1 (en) | Superfine-circuit semiconductor package structure | |
| US7531386B2 (en) | Semiconductor package | |
| KR19990037125A (en) | Semiconductor package and manufacturing method thereof | |
| CN1192041A (en) | Method of manufacturing semiconductor device | |
| CN1816904A (en) | Mold compound cap in a flip chip multi-matrix array package and process of making same | |
| US6828676B2 (en) | Semiconductor device manufacturing method, semiconductor device, and semiconductor device unit | |
| CN1187805C (en) | Application of heat radiator with support effect for circuit board with chip | |
| JPH0832183A (en) | Semiconductor chip package | |
| US20020124955A1 (en) | Attachment of a heat spreader for fabricating a cavity down plastic chip carrier | |
| EP1122779A2 (en) | Carbon fiber reinforced resin heat radiation fin mounted on a substrate | |
| US20040262746A1 (en) | High-density chip scale package and method of manufacturing the same | |
| US20060278975A1 (en) | Ball grid array package with thermally-enhanced heat spreader | |
| CN1347141A (en) | Method for mounting heat radiator to cavity down plastic chip carrier | |
| CN1209801C (en) | Production method of radiating plate with grounded reference potential function for radiating type chip plastic package | |
| JP4115712B2 (en) | Manufacturing method of chip package substrate having heat sink device having reinforcing effect | |
| KR100696050B1 (en) | Attachment of a stiff heat spreader for fabricating a cavity down plastic chip carrier | |
| Kohara et al. | New developed of thin plastic package with high terminal counts |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050202 Termination date: 20191102 |