CN1338810A - Method for generating control pulses of electric or electronic equipment - Google Patents
Method for generating control pulses of electric or electronic equipment Download PDFInfo
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- CN1338810A CN1338810A CN 01136252 CN01136252A CN1338810A CN 1338810 A CN1338810 A CN 1338810A CN 01136252 CN01136252 CN 01136252 CN 01136252 A CN01136252 A CN 01136252A CN 1338810 A CN1338810 A CN 1338810A
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Abstract
A method for generating the control pulses of electric power or electric equipment includes such steps as processing the synchronizing signals at front end or counting the amount of phase pulse signals to obtain phase scaling data, converting input control signal, storing it in storage space, reading out pulse data, comparing phase angle in it with said phase scaling data, logic conversion of pulse level to generate original pulse signal, and pulse shaping to obtain said control pulse. Its advantages include easy synchronization control, unified management of storage space, high data transmission efficiency and good speed match.
Description
Technical field:
The present invention relates to a kind of method for generation of control impuls of power electronic equipment, the signal that this method produces is mainly used in the power electronic equipment of electric power system, and for power electronic device provides various square-wave pulse control signals, belongs to power electronics control field.
Background technology:
In initial power electronic equipment, the generation of control impuls mostly is to adopt analogy method to realize, and these analogy methods have a lot of shortcomings.At first, used number of devices is numerous in the analog circuit, the circuit relationships complexity, and the debugging design is difficulty relatively.Difficulty in this design also makes the pulse generating circuit function singleness often of analog form, and range of application is narrow, very flexible.Secondly, adopt devices such as potentiometer, dial to realize the adjusting of circuit working situation in the analog pulse generation circuit, and adopt analog voltage signal or analog current letter to carry out the control of pulse generation, this control methods are neither directly perceived, and are not easy again.Have, analogue device is subjected to environmental factors such as noise and temperature easily and disturbs again, and analogy method realizes that the control precision of pulse generation is also lower.At last, the working condition of analog control system is not easy to supervise and shows that man-machine interaction is poor.
Along with the appearance of little process chip such as single-chip microcomputer, DSP and CPU, be a kind of digitized implementation method that provides of the control impuls of power electronic equipment.This method has solved the disadvantage of analogy method to a certain extent, but has introduced new problem simultaneously again.This is because little process chip generally can only be with single-threaded mode executive program, and the calculating of pulse and transmission need take time for each instruction as a part of program.And the control impuls of power electronics in using often need synchronous generation again, and this speed and priority arrangement that microcontroller is handled these tasks has proposed constraint, and the difficulty of software design and debugging is increased.In the control device of power electronics, the control impuls output that corresponding a plurality of power electronic device need provide multichannel to have nothing in common with each other, each road pulse not only will take into account in programming mutually, also can take the interface resource of most.
The method that another kind of solution thinking is the employing Digital Logic realizes the generation of the control impuls of power electronic equipment.Especially along with the development of programmable logic device, make the design studies of the control impuls generation of adopting the Digital Logic method to realize power electronic equipment many towards extensive and high integrated direction.One piece of article " based on the static compensator pwm pulse generator design of FPGA " is arranged in the 24th 23 phases of volume of December in 2000 " Automation of Electric Systems ", a kind of Digital Logic of having introduced this article realizes the production method of width-modulation pulse in the power electronics application, and accompanying drawing 1 has provided its theory diagram.According to Fig. 1, this system at first needs to establish in memory space into the pulsewidth parameter by data/address bus, then under synchronizing signal control, clock signal is counted, when count value is identical with current pulsewidth parameter, just switch the signal level of output pulse, then count zero clearing and read next pulsewidth parameter, continue computing like this and go down, produce the pulse train waveform of setting pulsewidth.In addition, the pulse output logic of this system also has the dead band and forms function, and this function can realize the interlocking control of two output signals.
The control pulse generation circuit scale of the power electronic equipment that existing this employing Digital Logic realizes is less, and function singleness can only produce width-modulation pulse.This method needs to rely on external micro treatmenting controller to calculate pulse-width data in actual applications, insert its memory space then, just can produce control wave, promptly must cooperate other micro treatmenting device to work, so this method does not produce the ability of pulse voluntarily, control mode is more complicated also.Have, because the pulse generating method utilization that this system adopts is pulse-width data, this data can not reflect the phase angle of pulse again, so this method is difficult to realize the synchronous output control of pulse, functional reliability is low.In addition, this pulse generating method does not have demonstration and monitoring function yet, is not easy to understand the working condition of system's pulse generation.On the data speed coupling, have only little process chip to calculate the speed of pulse-width data, and data are inserted the speed of the speed of memory space greater than pulse generation, this pulse method ability operate as normal.This Data Control and transmission means underaction are had relatively high expectations to the speed ability of micro treatmenting controller.
Summary of the invention:
The objective of the invention is to propose a kind of method for generation of control impuls of power electronic equipment, adopt the Digital Logic structure to realize the generation of the control impuls of power electronic equipment, directly send pulse, thereby be easy to realize the synchronous generation of pulse based on phase angle; This method can realize the various control pulse generation function at different power electronics application, can realize pulse modulation, minimum pulse width control and pulse interlocking; This method can provide control mode flexibly, simplifies control procedure; Realize the unified addressing visit of memory space, improve exchanges data efficient, the coupling requirement that underspeeds.
The method for generation of the control impuls of the power electronic equipment that the present invention proposes comprises following each step:
1, to carrying out Synchronous Processing, produces the phase scale data, perhaps the phase pulse signal that is obtained by frequency synthesis is carried out phase count, obtain the phase scale data by the synchronizing signal of front end signal processing section input.
2, to carrying out conversion process by the control signal of controlling platform input, the control data of controlled pulse generation, control data deposits in the memory space under the control of exchanges data logic, above-mentioned control data comprises state control data and pulse data, comprises phase angle in the pulse data and corresponding to the impulse level value of this phase angle.
3, according to the exchanges data logic, from memory space, read above-mentioned pulse data, the phase scale data that the phase angle of the pulse data that reads and above-mentioned the 1st step are obtained compare, according to this comparative result and under the control of state control data, the impulse level value of the pulse data that reads out is carried out logic and transform, produce original burst signal.
4, above-mentioned original burst signal is carried out the pulse conditioning, obtain final output pulse signal.
The inventive method has realized the pulse generation based on phase angle, is easy to realize synchronization control function; This method structure can also realize the generation function of the control impuls of various power electronic equipment, can extensively satisfy requirement of actual application; This method has realized the unified management of memory space, and adopts the visit of exchanges data logic control data, has improved data transmission efficiency, has solved the speeds match problem.
Description of drawings:
Fig. 1 is that a kind of Digital Logic method in the prior art realizes the theory diagram that the control impuls of power electronic equipment takes place.
Fig. 2 is the theory diagram of method for generation of the control impuls of power electronic equipment of the present invention.
Fig. 3 is the theory diagram of an embodiment of phase control part in the inventive method.
Fig. 4 is the theory diagram of first embodiment of pulse generation part in the inventive method.
Fig. 5 is the theory diagram of second embodiment of pulse generation part in the inventive method.
Fig. 6 is the theory diagram of width-modulation pulse data computation part among the 3rd embodiment of pulse generation part in the inventive method.
Fig. 7 is the theory diagram of an embodiment of pulse conditioning part in the inventive method.
Fig. 8 is the theory diagram of second embodiment of control interface part in the inventive method.
Fig. 9 is the theory diagram of an embodiment of storage space management part in the inventive method.
Embodiment:
The inventive method has been divided phase control, pulse generation, pulse conditioning, control interface, storage space management and six processing links of exchanges data logic and has been realized that the control impuls of power electronic equipment takes place, and Fig. 2 has provided the theory diagram that the inventive method is implemented.As shown in Figure 2, when adopting the synchronizing signal of being imported by the front end signal processing section, phase control part will carry out Synchronous Processing to synchronizing signal, and produce the phase scale data according to this.When not adopting synchronizing signal, phase control part will utilize its inner frequency synthesis function to produce phase pulse signal, then this phase impulse be counted, and obtain the phase scale data.Then, the pulse generation part is based on phase scale, and according to state control data in the memory space and pulse data, the paired pulses level carries out logical operation, produces original burst signal.Original burst signal also will be nursed one's health part through extra pulse, carries out high frequency modulated, minimum pulse width control, interlocking output time-delay and output and blocks processing such as control, obtains exporting pulse at last.The control interface of native system is partly finished the conversion of control signal to control data, and by to the exchange of exchanges data logical gate request for data, realizes the data access to memory space.The storage space management part is carried out unified addressing and Access Management Access to the memory space of system of the present invention.The exchanges data logical gate has adopted the exchanges data between application response control logic and priority processing method realization control interface, storage space management and these parts of pulse generation.
Fig. 3 is the theory structure of an embodiment of phase control part of the present invention, this implements structure can realize three kinds of working methods under the control of phase-locked selection signal and online selection signal, they are phase-locked synchronous working mode, non-phase-locked working method voluntarily and online synchronous working mode.Under phase-locked synchronous working mode, the phase-locked loop closure of phase-locked selection signal by to the control of selecting module phase demodulation, loop filtering, frequency synthesis and frequency division being formed, the synchronizing signal of input be by phase locking frequency multiplying, thereby obtain phase pulse signal.The frequency of phase pulse signal is by the N of the fundamental frequency of genlock times, and wherein N is by the multiple decision of frequency division part in the phase-locked loop.Set out the offset angle parameter according to the phase shift that the signal processing of system front end causes synchronizing signal, this offset angle parameter and fundamental signal are being controlled the phase compensation part together.The phase compensation part is counted judgement to phase impulse, produces the first-harmonic synchronization pulse of phase shift.Under phase-locked synchronous working mode, online selection signal gating phase impulse and first-harmonic synchronization pulse entering signal adjustment member, the blanking time that will make adjusted phase impulse of the computing judgement time greater than the pulse generation part is handled in the signal adjustment of this part, and also will guarantee simultaneously has N phase impulse in cycle of each first-harmonic synchronizing signal.The signal of adjusting the back acquisition on the one hand will be as online synchronizing signal output, and they are also with the input phase segment count on the other hand.Adjusted first-harmonic synchronization pulse will be to phase count computing zero clearing, and adjusted phase impulse will make the phase count part count from 0 to N-1.At last, the output result of phase count is exactly the phase scale of native system.
If in the production process of above-mentioned phase scale, the work that phase-locked selection mode signal selection comes the control frequency composite part by frequency parameter, this moment, phase-locked loop was disconnected, and the frequency synthesis part will produce phase pulse signal voluntarily.The phase compensation part in this time also no longer is subjected to the control influence of offset angle and fundamental signal, but directly the phase impulse of input is counted, and every N of counting phase impulse just produces a first-harmonic synchronization pulse.Last first-harmonic synchronizing signal and phase impulse obtain phase scale through signal adjustment and phase count, have so just realized the non-phase-locked working method voluntarily of phase control part.In order to realize the expansion of pulse output way, also provide the third clock work mode in this example---online synchronous working mode.Under this working method, the online synchronization output signal that is in the main pulse generation equipment generation of phase-locked synchronous or non-phase-locked working method voluntarily can be used as the online synchronous input signal of native system, through behind the gating of online selection mode signal, after as long as online synchronous input signal carries out signal adjustment and phase count, just produce the phase scale data identical with main pulse generation equipment.
The theory diagram of first embodiment of pulse generation part as shown in Figure 4, this embodiment is in order to produce the individual pulse signal in a primitive period.According to this method, the original phase scale that phase control part produces at first with start-phase parameter addition by the trigger angle decision, and if less than N, then this and directly export as the phase shift scale value, if and more than or equal to N, then this and deduct N after export again as the phase shift scale.After this, phase shift scale is imported the pulse generation arithmetic section on each road respectively.Pulse generation computing with the P1 road is an example, and rating unit constantly compares with the phase shift scale with by the definite phase parameter of the phase relation between each road pulse, and when both numerical value were the same, then rating unit was exported an effective inceptive impulse signal.Inceptive impulse signal and forced-triggered signal will enable and force logical operation under the management of one group of control signal, this group control signal comprises enable signal and forced signal.The rule of this logical operation is: if the enable signal on P1 road and forced signal are all invalid, then this logical gate does not have pulse output; If P1 road enable signal is effective, and forced signal is invalid, then this logical gate is exported inceptive impulse signal; If P1 road enable signal is invalid, and forced signal is effective, then this logical gate is exported forced-triggered signal; If P1 road forced signal is effective, and enable signal is become effectively by invalid, after this moment, an effective forced-triggered pulse must be accepted and export to this logical gate earlier, just normal output was from the inceptive impulse signal of comparison circuit, and the forced-triggered input signal will no longer work then.From pulse enable with what force logical gate output is burst pulse, pulsewidth adjustment member subsequently is adjusted into the set width of pulsewidth parameter with this burst pulse, finally exports the original burst signal on P1 road.
Fig. 5 has provided the theory diagram of second embodiment of pulse generation part, and this embodiment is in order to realize comprising in the primitive period generation of the width-modulation pulse signal of a plurality of pulses.As shown in Figure 5, bus management partly is responsible for reading pulse data to the application of exchanges data logical gate by PWM1BUS bus or PWM2BUS bus from the memory space of assigned address, here and the bus of hereinafter mentioning all form by a group address signal, data-signal and access control signal, and each pulse data in the present embodiment comprises phase angle and two parts of pulse output level.To be deposited earlier from the pulse data that memory space reads out, continuous and the current phase scale of numerical value of its phase angle part compares then, when the two numerical value was identical, the numerical value of pulse generation logic basis pulse data level part was revised the impulse level of output.A pulse data is through above-mentioned phase bit comparison judgement, and behind the generation output impulse level, the bus management part reads the next pulse data with regard to automatic addressing to the application of exchanges data logical gate then.Continue like this, constantly, finally obtain the width-modulation pulse sequence at the different impulse level of out of phase scale output.As shown in Figure 5, adopted identical two group pulse generation part PWM1 and PWM2 in the theory structure of present embodiment, such structure is in order to realize common under the management of alternation control logic and to replace two kinds of pulse generation mode of operations.Under normal mode of operation, part takes place for PWM1 and PWM2 two group pulses works simultaneously, they read pulse data respectively from the different memory paragraph of memory space, finish the pulse generation function independently, the pulse output control part is assigned to each road output port with the output that part takes place in two group pulses, as shown in Figure 5, what the original pulse on P1p road was exported is the P1 pulse signal that the PWM1 pulse generation partly produces, and the original pulse on P1n road output is the P2 pulse signal that the PWM2 pulse generation partly produces, and the output of other each road pulse is similar with it.Yet under the alternation pattern, part alternately is responsible for the controlled original pulse on some road under switching command control output takes place in PWM1 and PWM2 two group pulses, and the output of all the other each road pulses is complementary signals of these controlled pulses.Particularly, when PWM1 enables, when PWM2 quits work, drive the original pulse on P1p road by the P1 pulse signal of PWM1 generation; And when switching command requirement alternation, PWM2 is enabled, and when PWM1 stopped, the output of the original pulse on P1p road changed the P2 pulse signal that is produced by PWM2 into and drives; Under this alternate mode, the pulse on P1n road output is the complementary signal after the pulse signal negate of P1p road all the time; The working condition on other road is similar with it.In addition, alternately switch not is just to carry out when switching command signal arrives at once, but effective, and after a set of pulses of working part takes place handled last pulse data of designated store section section tail, just carry out the switching of pulse generation at switching command.Alternate mode can realize the complicated control algolithm of some pulse generations.No matter be in normal mode of operation or in the alternation pattern, one group of PWM1 that is working or PWM2 pulse generation part are after handling last pulse data of designated store section, do not stop to produce pulse as long as require it, it will be according to the first address parameter of the pulse data memory paragraph of setting in the bus management part, and the pulse data that restarts a new round reads, processing and pulse generation.
The 3rd embodiment of pulse generation part is the computing function voluntarily that has increased the width-modulation pulse data on second above-mentioned embodiment basis again.Fig. 6 is the theory diagram of the pulse data calculating section of this embodiment increase, and this part can calculate pulse data voluntarily, and by switching command signal control PWM1 and PWM2 two group pulse generation part alternations shown in Figure 5.The width-modulation pulse data computing can be selected nature sampling method, regular sampling, directly pulse-width modulation method, multiple algorithm principle realization such as slope pulse-width modulation method and space vector at random.No matter but adopt any computational methods, when the phase angle of the variation that calculates impulse level and corresponding this variation constantly after, must impulse level and phase angle be combined into complete pulse data according to the pulse data form that pulse generation shown in Figure 5 partly be adopted.As shown in Figure 6, the constants of using in the width-modulation pulse data computing such as look-up table will read from memory space by REFBUS bus management part request for data exchange logic part.If the calculating of the pulse data of N phase sample point in the primitive period is referred to as one push start, wherein N is a phase impulse number in the primitive period.Then in starting each time, the width-modulation pulse data computation partly calculates the corresponding 0 output impulse level to each phase scale point of N-1, only need choose the pulse data that the last relatively phase point of output level changes then, PDATBUS bus management part partly deposits these data in memory space by PDATBUS bus request for data exchange logic.Finish when the pulse data of one push start calculates, PDATBUS bus management part will partly provide the addressing parameter of these pulse datas that just calculated in memory space for the pulse generation of Fig. 5.Simultaneously, the width-modulation pulse data computation partly produces switching command signal by the control signal output logic, this signal input alternation control logic part shown in Figure 5.After this, one group of PWM1 that is working or PWM2 pulse generation part are after the calculation process of finishing its pairing last pulse data of pulse data section, to under the control logic effect, quit work, switching of each road original pulse partly driven by another group PWM2 or PWM1 pulse generation, the pulse generation part of new starting produces width-modulation pulse according to the pulse data that is newly calculated by width-modulation pulse data computation part.In case alternately switching, PWM1 and PWM2 finish, width-modulation pulse data computation part will begin again to fall into a trap to calculate accurately at corresponding memory space and be equipped with new pulse data for part takes place for an out-of-work set of pulses, finish until another starting calculating, and then application PWM1 and the alternation of PWM2 two parts.
The original burst signal that above-mentioned pulse generation partly produces also will just be used as final pulse output through extra pulse conditioning part, and Fig. 7 has provided the theory diagram of an embodiment of pulse conditioning part.The pulse conditioning comprises pulse high frequency modulated, minimum pulse width control, interlocking output time-delay and exports and block, these processing links all are controlled, if the pairing control signal of wherein a certain processing links enables, then carry out corresponding burst process, if and do not enable, then pulse signal is processed and directly by this link.If the pulse high frequency modulated is enabled, then the significant level signal of each road original pulse will be modulated to and have one group of sequence of high frequency pulses setting duty ratio and frequency.If minimum pulse width control is enabled, this part is adjusted to the value of setting that width is not less than the minimum pulse width parameter with pulse duration in the pulse signal of input less than the positive or negative pulse of set point.If interlocking output time-delay control enables, this pulse conditioning part will make by the output level of the two-way pulse of interlocking ineffective simultaneously, and take place to ensure when level changes one of them must be become when invalid again through one period by the interlocking time delay parameter setting at the level of the pulse signal of another interlocking by the pulse signal of interlocking after at their and just allow to become effectively.Last output block part can be directly under the control signal effect in the output of output port locking pulse, and do not influence the work of system's other parts.
A simple embodiment of control interface part of the present invention is directly to adopt digital control interface.External control device visits digital control interface by a group address signal, data-signal and control signal, and input will be visited the address parameter and the access type of memory space, if external control device will carry out write-access to the memory space of system of the present invention, then also to import the data that are about to write.Digital control interface section proposes the visit application by the bus management logic to the exchanges data logical gate, and accepts the response of exchanges data logical gate, thereby realizes the read and write access to state control data in the memory space and pulse data.If external control device need read memory space, after the sense data of bus control logic reception from numeral exchange control section, again these data are sent to external control device.
Second embodiment of control interface part of the present invention adopted theory structure shown in Figure 8, and this embodiment provides the method that adopts analog level control signal and the pulse generation of button control signal control native system, and it also has certain Presentation Function simultaneously.At first, logical operation obtains the addressing parameter to address button control signal through the button control interface, and this addressing parameter is stored in by in the registration section of change of address.Then, select control section can select to adopt input of analog level control signal or button control signal to import and carry out parameter control.If the analog level input control of having selected the control section gating, through controlled parameter after the analog-to-digital conversion, Control Parameter is deposited in the Control Parameter registration section by the analog level control signal of external control appliance input.If the button input control of having selected the control section gating, then the button control interface is after just being enabled or the addressing parameter changes, and it will be at first partly reads with the addressing parameter by BTNBUS bus management part request for data exchange logic is initial data in the memory space of address.Then, the button control interface is accepted the button control signal of data modification, increases and decreases computing on the initial data basis of reading, and obtains new Control Parameter.Certainly, button control interface logic also can adopt other algorithm that Control Parameter is set, but the Control Parameter that last button control interface produces all will deposit the Control Parameter registration section in by selecting control section.After no matter adopting analog level control input or obtaining new Control Parameter by the key control input, BTNBUS bus management part all will be according to the application of exchanges data logical gate new control data being write corresponding memory space by the address of the decision of the addressing parameter in the registration section of change of address.In addition, BTNBUS bus management part also will deposit in and read the parameter registration section according to being refreshed by demonstration and time interval that button operation speed is determined is read data in the respective stored space to the application of exchanges data logical gate then according to the addressing parameter.This reads parameter and can partly be read by the button control interface on the one hand, and as the initial data of above-mentioned button control logic computing, this reads parameter and will constantly deliver to the display interface part on the other hand.The display interface part is according to the addressing parameter and read parameter, drives and refresh to show the control output signal.
The theory diagram of an embodiment of storage space management part of the present invention as shown in Figure 9.Whole memory space is made up of state control data memory space, NVSRAM memory space and SRAM memory space, and by storage space management unified logic addressing visit.The state control data memory space is to be put together by status signal and Control Parameter in phase control part among the present invention, pulse generation part, pulse conditioning part and the control interface part, thus unified addressing and manage a part of memory space that their visit constitutes.When the storage space management logical gate provides effective address and read-write, just can read or revise corresponding status signal and Control Parameter by the administrative section of state control data.In the present embodiment, the reference address of state control data memory space will have identical address with a part of memory paragraph in the NVSRAM memory space.NVSRAM is the memory space that the storage data are difficult for losing after a kind of power down, can be used for preserving important data after system's power down, and the control logic of NVSRAM is in charge of the visit of NVSRAM memory space.A part of memory paragraph in the NVSRAM memory space will be used to preserve aforesaid state control data, so this memory paragraph has identical reference address with the state control data memory space.The NVSRAM memory space can also be used to storing constant data such as the needed look-up table of width-modulation pulse data computation, and is used for storage pulse data etc.SRAM then is can high speed access but a part of memory space of loss of data after the power down, and in order to the data that need not to preserve after the storage power down, its Access Management Access is finished by the SRAM control logic.Aforesaid three part memory spaces are all addressed by the storage space management unified logic, and finish the exchanges data logical gate by the data access of memory space access bus to memory space.When the native system reset initialization, this storage space management logic also will be responsible for the state control data before the power down is read from the respective stored section of NVSRAM, and be loaded into again in the state control data memory space.When the native system operate as normal, the exchanges data logical gate is by storage space management logic reading an Access status control data memory space state control data; And the exchanges data logical gate writes Access status control data memory space not only the modification of state control data, also modification is had the NVSRAM memory space of same address, in order to realize the preservation of data.Memory space access bus between the storage space management logical AND exchanges data logical gate not only comprises address signal and data-signal, also comprises control signals such as read and write access order, read and write access response and the effective indication of data.
Exchanges data logical gate of the present invention is exchanges data and the transmission that is used for realizing between other various piece of native system, thereby they are organized into a holonomic system.Exchanges data in the native system comprises that mainly control interface is to the visit to the pulse data in the memory space of the control visit of memory space and pulse generation part.The exchanges data logical gate with the initialization procedure of control whole system, is finished the transmission of the control data and the pulse data of some initial phases automatically after system reset.Finish in initialization, during the system operate as normal, the exchanges data logical gate is constantly inquired about the visit application of check from control interface or pulse generation partial data bus, responds these applications by certain priority order then, finishes the exchange transmission of data.That is to say, when synchronization has a plurality of visit application, the exchanges data logical gate will at first respond the highest access request of priority, if the application of response is the access request that reads memory space, this exchanges data logical gate will be according to reference address control store space management part sense data from corresponding memory address, and then data are sent to the visit applicant by corresponding bus.If the exchanges data logical gate has responded the visit application that writes data to memory space, it just receives by write data from corresponding bus, sends to the storage space management part by the memory space access bus then, and finishes data by this part and write.
The present invention for constructing of the required various control waves of power electronic equipment the complete implementation of a cover.Can see that from embodiment phase control division is divided into native system provides multiple clock work mode, they comprise non-phase-locked working method voluntarily, phase-locked synchronous working mode and online synchronous working mode.Non-phase-locked working method voluntarily directly relies on the adjusting that the control of the frequency parameter of incoming frequency composite part has been realized paired pulses generation fundamental frequency; Phase-locked synchronous working mode makes system can be synchronized with external input signal and produces pulse, and this mode all needs to use in the power electronic equipment of various dependence trigger angle work; The on-line working mode can make many group pulses generation systems synchronous working, has realized the expansion of pulse output way simply.Which kind of clock work mode no matter phase control part adopt, and finally all for system provides phase scale numerical value, thereby lays the first stone for system of the present invention can send pulse based on phase angle.
As previously mentioned, pulse generation part of the present invention can adopt multiple scheme to realize different pulse output functions.Utilize three given embodiment of Fig. 4, Fig. 5 and Fig. 6 all to be based on phase scale work, thereby really realized the present invention is based on the target that phase angle produces pulse.Providing of first embodiment of pulse generation part is the application need that takes place at the numerous pulses in the power electronic equipment, control when this embodiment both can realize the triggering phase angle of each road output control pulse, also can realize single adjusting to a certain road pulse-triggered phase angle, the width of trigger impulse also can change.And enabling in embodiment illustrated in fig. 4 can be dropped into or the like controlled function in order to realize the capacitance apparatus voltage zero-cross with the forced-triggered logic, and this function is widely used in the power electronic equipment of power system reactive power compensation.By second embodiment of pulse generation part of the present invention, can make system of the present invention realize aiding in the pulse generation of other micro treatmenting controller.In the application, adopt external little stage process handling equipment to calculate desired pulse data among second embodiment of coincidence pulse generation part, insert then in the memory space of native system, pulse generation second embodiment just can produce the control impuls of power electronic equipment according to these pulse datas.Owing to comprise PWM1 and PWM2 two group pulse generation parts in the pulse generation scheme shown in Figure 5, but also designed their alternation pattern, this just makes native system can realize the control algolithm of rattling and storing again.Particularly, control system can allow PWM1 send pulse earlier, prepares new pulse data for PWM2 then; Because PWM1 meeting Automatic Cycle is called the pulse data in the memory paragraph, cutting off of pulse train generation can not appear; When system is after PWM2 is ready to pulse data, stop the work of PWM1 again by switching command, send pulse and start PWM2; After this, control system can then go to be that PWM1 revises prepares new pulse data; Under over-over mode, PWM1 and PWM2 take turns to operate like this.The mode of this alternately storage and deal with data is called the table tennis algorithm habitually, it can solve that pulse data calculates and pulse generation between do not match problem with data collision of speed.The 3rd embodiment of pulse generation part of the present invention increased width-modulation pulse data computation part shown in Figure 6 on second embodiment basis, system of the present invention is had be not subjected to external control appliance control and the independent ability that produces the width-modulation pulse of certain characteristic.
The embodiment of pulse conditioning part of the present invention can satisfy the driving needs of different power electronic device, has realized controlled pulse high frequency modulated, minimum pulse width control, pulse interlocking time delay and pulse output blockade.If the digital control interface that control interface part of the present invention adopts first embodiment to describe can be realized being connected of native system and numerical control device easily.And if control interface has partly adopted second embodiment, the analog-to-digital conversion interface can be realized being connected of native system and analog control equipment, and keystroke interface can only adopt one group of button just to finish the control that system of the present invention pulse is exported.These different control interfaces are suitable for satisfying the power electronics application requirements with differing complexity.
The inventive method can be organized unified management with dissimilar memory spaces.Such as described, utilize the state control data memory space status signal scattered in the system and Control Parameter can be managed concentratedly, thereby improved control efficiency according to the embodiment of storage space management part of the present invention; Adopt the NVSRAM memory space to realize that the parameter after the power down is recovered and the preservation of significant data; Adopt the SRAM memory space can satisfy the more data access needs of high speed again.Various types of memory spaces also can be allocated according to concrete application need and cost.
At last, the present invention has adopted the exchanges data logical gate that all the other various pieces are organized, and constitutes complete pulse generation system.The exchanges data logical gate adopts the exchanges data application between the priority control mode response each several part, finishes transfer of data.This institutional framework has solved the speed matching problem between the disparate modules in the system with simple form, and the priority control mode has guaranteed the priority access of pith to data, has avoided the transfer of data delay, has improved exchanges data efficient.
The inventive method finally can adopt the Digital Logic mode to realize fully, and the generation systems of the control impuls of the power electronic equipment that according to said method obtains has easy and simple to handle intuitively, is easy to safeguard control precision height, stable and reliable operation advantage.And, realized certain Presentation Function among second embodiment of control interface part of the present invention, can realize certain man-machine interaction.Realize the inventive method if adopt large-scale integrated circuit, finally can obtain a kind of dedicated IC chip that can be widely used in the power electronic equipment, this will simplify the realization of power electronic equipment control device greatly, reduce simultaneously and design and develop cost.In fact, the inventive method designs and tests based on large-scale programmable logic device, aforesaid embodiment has passed through actual using and verifying in design, and by functional simulation and circuit debugging, proof the inventive method can operate as normal, realizes set controlled target and exports correct pulse signal.
Claims (1)
1, a kind of method for generation of control impuls of power electronic equipment is characterized in that this method comprises following each step:
(1) to carrying out Synchronous Processing, produces the phase scale data, perhaps the phase pulse signal that is obtained by frequency synthesis is carried out phase count, obtain the phase scale data by the synchronizing signal of front end signal processing section input;
(2) to carrying out conversion process by the control signal of controlling platform input, the control data of controlled pulse generation, control data deposits in the memory space under the control of exchanges data logic, above-mentioned control data comprises state control data and pulse data, comprises phase angle in the pulse data and corresponding to the impulse level value of this phase angle;
(3) according to the exchanges data logic, from memory space, read above-mentioned pulse data, the phase scale data that the phase angle of the pulse data that reads and above-mentioned the 1st step are obtained compare, according to this comparative result and under the control of state control data, the impulse level value of the pulse data that reads out is carried out logic and transform, produce original burst signal;
(4) above-mentioned original burst signal is carried out the pulse conditioning, obtain final output pulse signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01136252 CN1123959C (en) | 2001-10-12 | 2001-10-12 | Method for generating control pulses of electric or electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01136252 CN1123959C (en) | 2001-10-12 | 2001-10-12 | Method for generating control pulses of electric or electronic equipment |
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| Publication Number | Publication Date |
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| CN1338810A true CN1338810A (en) | 2002-03-06 |
| CN1123959C CN1123959C (en) | 2003-10-08 |
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| CN 01136252 Expired - Fee Related CN1123959C (en) | 2001-10-12 | 2001-10-12 | Method for generating control pulses of electric or electronic equipment |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102624367A (en) * | 2011-01-30 | 2012-08-01 | 深圳迈瑞生物医疗电子股份有限公司 | Multi-channel pulse synchronization identification apparatus and method thereof |
| CN103762964A (en) * | 2014-01-17 | 2014-04-30 | 北京航空航天大学 | Multi-channel high-precision PWM signal sampling and generation device |
| CN113162585A (en) * | 2021-04-02 | 2021-07-23 | 浙江清华柔性电子技术研究院 | Pulse control method and device and electronic equipment |
-
2001
- 2001-10-12 CN CN 01136252 patent/CN1123959C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102624367A (en) * | 2011-01-30 | 2012-08-01 | 深圳迈瑞生物医疗电子股份有限公司 | Multi-channel pulse synchronization identification apparatus and method thereof |
| CN102624367B (en) * | 2011-01-30 | 2015-11-25 | 深圳迈瑞生物医疗电子股份有限公司 | Multichannel impulsive synchronization recognition device and method |
| CN103762964A (en) * | 2014-01-17 | 2014-04-30 | 北京航空航天大学 | Multi-channel high-precision PWM signal sampling and generation device |
| CN103762964B (en) * | 2014-01-17 | 2016-05-18 | 北京航空航天大学 | A kind of multi-channel high-accuracy pwm signal sampling and generating apparatus |
| CN113162585A (en) * | 2021-04-02 | 2021-07-23 | 浙江清华柔性电子技术研究院 | Pulse control method and device and electronic equipment |
| CN113162585B (en) * | 2021-04-02 | 2023-02-17 | 浙江清华柔性电子技术研究院 | Pulse control method and device and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1123959C (en) | 2003-10-08 |
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