A kind of sampling system of read channel of optical storage medium and sampling method
The present invention relates to a kind of sampling system and method for read channel of optical storage medium, particularly relate to sampling system and method with a kind of CD-ROM driver (CD-ROM) or digital multi-purpose CD player (DVD) simulating signal fetch channel.
Popular along with multimedia computer and internet, the mankind not only can also obtain comfortable seeing and hearing enjoyment than use computer more easily in the past.In addition, interpersonal distance is also more and more nearer along with the progress of communication science and technology.And one of this wherein maximum person who has rendered outstanding service, it is the quick progress of Storage Media technology, because not only above-mentioned application can use Portable high power capacity optical storage media, CD for example, VCD or DVD CD-RW discsCD-RW are propagated, the computer user also can come information such as transmission data, image and sound by above-mentioned optical storage media or by the internet or carry out the backup of related data, and is not only convenient but also safer reliable.
For the optical storage media technology, the result of market competition, still do not pursue the increase of capacity, for example by CD-ROM can storage volume the limit, promptly also advance to the high order of magnitude of capacity or above DVD sheet (G byte) from 640 (M byte) megabit tuple.Further, also simultaneously in the contest of carrying out speed; Be not CD-ROM (compact disc read-only memory), CD-R (making carbon copies No. one time videocorder) or CD-RW (rewritable videocorder), and all carrying out the contest of speed multiple as for the development of optical memory systems such as DVD-ROM or DVD-RW.
The reduction of the requirement that improves constantly in the face of speed of optical memory system and the cost problem that will face at first just needs the understanding numerical data be how to be stored in Storage Media for convenience of description, and the numerical data reduction technique that is stored in Storage Media is described afterwards again.As everyone knows, optics or magnetic stocking system are that numeral or simulation data are recorded on the discoid Storage Media (track) or helical orbit (spiral track) that has concentric circular tracks, for example CD or disk (dish).The operation of numerical data modulation write head (write-head) is to write down two-symbol data in regular turn in atwirl video disc.For optical recording system, numerical data is a modulation laser bundle light intensity, so that write down a series of continuous or discrete pits (pit) on CD.
When the numerical data of reading and recording on CD or disk, same read head (read-head) then reads facing to the video disc in the fast rotational with the distance of very pressing close to video disc.The variation on read head detecting Storage Media surface and produce the respective pulses of a sequence and exist with the signal that reads of simulation, these simulating signals can be read by analog fetch channel (analogread channel), also can be read by digital fetch channel (digital readchannel).Analog fetch channel circuit is detected the spike (peak) that signal is read in simulation that above-mentioned read head reads with the continuous time, cuts apart (segmented) time again and with decipher (interpreted) serve as most bit born of the same parents cycles (bit cell period).When there was spike in the bit born of the same parents cycle, the bit born of the same parents just represented with " 1 ", otherwise just represent with " 0 ".Yet, do not have the center in correct aligning bit born of the same parents' cycle to make a mistake if read the spike of signal.Therefore, just needing regularly to reply (time recovery) circuit proofreaies and correct.
When data density increases, be easy to produce mistake because of spiking too intensive makes the signal of off-peak signal and spike overlap each other, usually will be when therefore, the simulation read head reads data with Control of Voltage frequency generator (voltage control frequencygenerator; VCF) cooperate phase-locked loop (phase locked loop; PLL) to reduce the error rate of data.Secondly, when the reading rate demand is high more, if with analog fetch channel processing of circuit, not only cost will also be sinkd beneath one's burden because of the requirement growth fast (needing more assembly) of speed and for Signal Processing.Because the processing speed (DC offset tracklng) for simulation read head direct current off normal is crossed the detecting that has error of transmission slowly and not,, uses in analog fetch channel circuit so being applicable to the low speed data access usually.
If the problem that above-mentioned analog fetch channel circuit is faced change by digital fetch channel reads when handling, and then can obtain roughly satisfied solution.For example: digital fetch channel is with the sampling as simulating signal of the low-pass filter of antialiasing signal (anti-aliasing), and have self-adaptation eqalizing cricuit (adaptive equalizer), it can take place to compensate automatically when transmission distorts situation and minimum degree is reduced in interference such as nonlinear phase shift by factor tone of Chinese characters varying signal in the data transmission course.Secondly, the processing speed of direct current off normal is quick, in addition, and for the detecting of error of transmission or say that maximum possible detecting (maximum likelydetection) is easy, therefore, for the high power speed application epoch, digital fetch channel almost replaces analog fetch channel fully.
Because optical memory system, reading at a high speed is a kind of trend, though classic method is developed to the lower digital fetch channel of error rate by the simulation fetch channel, yet because channel rate (baud rate) is more and more higher, for example with 16 times of speed, speed is about 16 times of speed * 26Mbit/s/ times of speed=400Mbit/s, to read with traditional digital fetch channel, will be very difficult, because, it is generally acknowledged that ADC sampling frequency (sequential speed also is like this) will get caught up in channel rate at least, promptly sampling frequency is about anti-Qwest sampling rate (Nyquistrate) and just can produce mistake.But in the face of high speed like this, the more complicated and also therefore increase fast of its cost of the design element of ADC.Promptly as in the nearest patent documentation, No. the 5966415th, United States Patent (USP) is by the Bliss patent that obtained in October, 1999 in, and the idea of the sub-sampled that " Adaptiveequalization in a sub-sampled read channel for a disk storagesystem " provides is the same.Wherein " sub--sampled readchannel " indication is the technology of ADC sampling frequency less than channel rate.
The method that Bliss provides can be done a general introduction with calcspar shown in Figure 1.Among Fig. 1, fixed time sequence generator 10 provides one frequency f _ s to disengaging time (discrete time) sampling of A/D sample circuit module 20 to carry out simulation data.The speed of sampling, littler by 10% than the speed of fetch channel approximately, follow sampled data signal incoming timing answer interpolating circuit module (timing recovery interpolator module) 30 and carry out the interpolation sampling, regularly replying interpolating circuit module 30 also provides a signal 50 back couplings to reply the sequential (clock) of the work of interpolating circuit module 30 to sequential control (timing control) module 40 to adjust timing.But, its speed of on average carrying out interpolation is equal with fetch channel approximately.Therefore with regard to embodiment, the sampling rate of interpolation is to adjust upward (the synchronization of rate that 9/10T → T) and passage read, and then, the interpolation sampling value is carried out the compensation of high-frequency signals so that the signal of the signal of transverse axis (no-voltage) top or below is more obvious, to reduce the interference of noise via eqalizing cricuit (equalizer) 60 again.At last, find out the numerical data of maximum possible with the digital signal of output by tandem detecting device (sequence detector) 70 again near the zero error rate
Yet, the method that Bliss provides still need the following step (1) ADC sampling frequency approach (less than or be equal to 9/10) channel frequence; Therefore and synchronization of rate (being 1/T) generation interpolation sampling value (2) regularly reply interpolater (timingrecovery interpolator) and carry out the sampling conversion; And (3) carry out the data high-frequency compensation of the interpolate value of rate samples with eqalizing cricuit.Therefore, reply the design complexities of interpolater, help very limited for reducing ADC circuit and timing.
The object of the present invention is to provide a kind of sampling system with a kind of read channel of optical storage medium of low cost and high-speed information access features.
Another object of the present invention is to provide a kind of sampling method of read channel of optical storage medium in response to the reduction of ADC sample circuit frequency, it is a kind of new interpolation method, its required frequency of operation also is half of channel rate, therefore can significantly simplify the element that the required element of ADC sample circuit is also also saved simultaneously half interpolating circuit.
For achieving the above object, the invention provides a kind of sampling system of read channel of optical storage medium, it is characterized in that: comprise at least:
The analog-to-digital sampler, this analog-to-digital sampler is to be about the simulating signal that half frequency of fetch channel speed reads a Storage Media;
Regularly reply the interpolation module, this regularly replys the interpolation module and this analog-to-digital sampler is coupled, carry out interpolation with most samples, and obtain the interpolation data sample of all half numbers of bit born of the same parents of fetch channel according to this analog-to-digital sampler output;
The 2T time etc. are changed circuit module, compensate to improve the signal amplitude of this interpolation data sample in order to the high-frequency signal that the interpolation data sample is carried out data; And,
Twice factor interpolating circuit module obtains second half bit born of the same parents' of all bit born of the same parents of fetch channel data with interpolation method.
The sampling system of described read channel of optical storage medium, it is characterized in that: also comprise direct current off normal control circuit and and mix device, this is mixed device change circuit module such as this 2T time output is mixed mutually with this direct current off normal control circuit, in order to the direct current off-location alarm removal in the interpolation data sample of high-frequency signal compensation.
The sampling system of described read channel of optical storage medium is characterized in that: described twice factor interpolating circuit module also feedback a signal to this direct current off normal control circuit to open or to close the running of this direct current off normal control circuit and feedback another signal to one sequential control die set.
The sampling system of described read channel of optical storage medium, it is characterized in that: also comprise a direct current off normal control circuit and and mix device, this is mixed device this output of regularly replying the interpolation module is mixed mutually with the output of this direct current off normal control circuit, removes in order to the direct current off-location alarm in the interpolation data sample that will regularly reply.
The sampling system of described read channel of optical storage medium, it is characterized in that: also comprise a direct current off normal control circuit and and mix device, this is mixed device the output of this analog-to-digital sampler is mixed mutually with the output of this direct current off normal control circuit, in order to the direct current off-location alarm in the data sample of this analog-to-digital sampling is removed.
The sampling system of described read channel of optical storage medium, it is characterized in that: also comprise a tandem detecting device, being coupled with this twice factor interpolating circuit module, detecting and export two bit datas in order to the tandem numerical data with this two-phase ortho position cellular is one group binary number character code.
The sampling system of described read channel of optical storage medium is characterized in that: described analog-to-digital sampler is to carry out the analog-to-digital sampling with at least one half rate of fetch channel speed.
The sampling system of described read channel of optical storage medium is characterized in that: it is the interpolation of carrying out every 2T time data sample with the fetch channel speed of 1/ (2T) that the interpolation module is replied in described timing.
The sampling system of described read channel of optical storage medium is characterized in that: it is a finite impulse response (FIR) filtering circuit that the interpolation module is replied in described timing.
The sampling system of described read channel of optical storage medium, it is characterized in that: described timing answer interpolation module is to utilize the coefficient form of a quantification to the interpolation of every 2T time data sample, with the multinomial coefficient of the interpolate value that obtains most adjacent 2T time points, and calculated and obtained the interpolate value of this time point.
The sampling system of described read channel of optical storage medium is characterized in that: the bit born of the same parents data of described second half number is meant that described per two the adjacent and data time in the middle of this interpolation data of high-frequency signal compensation obtain with this twice factor interpolating circuit module interpolation method.
The sampling system of described read channel of optical storage medium is characterized in that: described twice factor interpolating circuit module comprises at least:
Most data working storages are in order to this interpolation data sample of high-frequency signal compensation that stores the 2T time interval;
Most the working storages that store the interpolation polynomial coefficient;
A most multiplier are in order to multiplying each other respectively with the interpolation data sample that compensates through high-frequency signal by a majority interpolation polynomial coefficient; And
One totalizer is in order to content that should majority multiplier output signal in addition mutually.
The sampling system of described read channel of optical storage medium, it is characterized in that: described twice factor interpolating circuit module is to multiply each other respectively to the multinomial coefficient of 8 fixed values and 6 to 8 the most adjacent these interpolation data samples through the high-frequency signal compensation with 6, and add up and obtain these 6 to 8 the middle bit outputs of this interpolation data sample of high-frequency signal compensation, and adjacent one should be through another bit output of this interpolation data sample of high-frequency signal compensation.
The sampling system of described read channel of optical storage medium is characterized in that: described tandem detecting device is the correctness of proofreading and correct the output data with the Trellls state transition diagram.
The present invention also provides a kind of sampling method of read channel of optical storage medium, it is characterized in that: comprise following steps at least:
Take a sample with half that is about this fetch channel speed, and obtain the simulating signal of this fetch channel thus;
Described simulating signal sample is carried out interpolation, to obtain the interpolate value sample of all half numbers of bit born of the same parents of fetch channel; And
In the middle of per two adjacent interpolate value samples, carry out the data interpolation in order to supply unsampled intermediate sample.
The sampling method of described read channel of optical storage medium is characterized in that: described sampling is to take a sample with the analog-to-digital sampler.
The sampling method of described read channel of optical storage medium is characterized in that: described interpolation sampling is a data sample of obtaining the 2T time interval regularly to reply the interpolation module.
The sampling method of described read channel of optical storage medium, it is characterized in that: it is to utilize the interpolation polynomial coefficient form that regularly changes that the interpolation that the interpolation module carries out every 2T time data sample is replied in described timing, with the multinomial coefficient of the interpolate value that obtains most adjacent 2T time points and calculated and obtain the interpolate value of this time point.
The sampling method of described read channel of optical storage medium is characterized in that: described interpolate value high-frequency signal compensation is with 2T time interval eqalizing cricuit compensation high-frequency signal.
The sampling method of described read channel of optical storage medium is characterized in that: described data interpolation of carrying out missing in the middle of two adjacent interpolate value samples is to produce with twice factor interpolating circuit.
The sampling method of described read channel of optical storage medium, it is characterized in that: described twice factor interpolating circuit module is to multiply each other respectively to the multinomial coefficient of 8 fixed values and 6 to 8 the most adjacent these interpolation data samples with 6, and adds up and obtain the middle bit output of this interpolation data sample.
The sampling method of described read channel of optical storage medium, it is characterized in that: described twice factor interpolating circuit module is once exported two bit datas, one is bit to be calculated, and another is adjacent this interpolation data sample of this bit to be calculated.
The sampling method of described read channel of optical storage medium is characterized in that: also be included in after the data interpolation step of carrying out leakage in the middle of per two adjacent interpolate value samples the wrong data of proofreading and correct two bit datas that this twice factor interpolating circuit module exported with a tandem detecting device.
The sampling method of described read channel of optical storage medium is characterized in that: the wrong data that this tandem detecting device is proofreaied and correct two bit datas that this twice factor interpolating circuit module exported is the correctness of proofreading and correct the output data with the Trellis state transition diagram.
The sampling method of described read channel of optical storage medium is characterized in that: also be included in the signal of removing flip-flop after the high-frequency compensation step of interpolate value sample with direct current off normal circuit.
The sampling method of described read channel of optical storage medium is characterized in that: after also being included in sampling procedure, reach the step of removing the signal of flip-flop before the analog signal sample carries out interpolation with direct current off normal circuit.
The sampling method of described read channel of optical storage medium is characterized in that: after also being included in the analog signal sample and carrying out the interpolation step, and the interpolate value sample carries out removing with direct current off normal circuit before the high-frequency compensation step step of the signal of flip-flop.
After having adopted technique scheme, the sampling system of a kind of read channel of optical storage medium of the present invention, this system comprises an analog-to-digital sampler at least, the analog-to-digital device is to be about half frequency of fetch channel speed, 8/7*1/ (2T) for example reads the simulating signal of Storage Media; In addition, one regularly replys interpolation module (timing recoveryinterpolator module) carries out interpolation according to the individual samples of the majority of analog-to-digital sampler output, in order to obtain the interpolation data sample of all half numbers of bit born of the same parents of fetch channel.
One 2T answering of time circuit module (2T-spaced equalizer) is carried out the interpolation data sample high-frequency signal compensation of data subsequently, to improve the signal amplitude of interpolation data sample, can reduce noise like this and disturb the data read error that is caused.One twice factor interpolating circuit module (factor2 interpolator) then refills the bit born of the same parents' of second half number of all bit born of the same parents of fetch channel data and once exports the tandem numerical data of two-phase ortho position cellular with interpolation method.
At last, again with tandem detecting device (sequence detector), utilize the Trellis state transition diagram of two samples input-two bits output that the tandem numerical data is detected and advance the mode that two bits go out with two samples in regular turn and export zero error rate bit data.
Therefore, the present invention has low cost and high-speed information access features; And method of the present invention is a kind of new interpolation method, and its required frequency of operation also is half of channel rate, so can significantly simplify the element that the required element of ADC sample circuit is also also saved simultaneously half interpolating circuit.
Below, with embodiment the present invention is done further detailed description in conjunction with the accompanying drawings.
Fig. 1 illustrates the block schematic diagram according to the digital fetch channel of classic method design.
Fig. 2 illustrates the block schematic diagram according to the optical memory system numeral fetch channel of first embodiment of the present invention design.
Fig. 3 (A) illustrates synoptic diagram according to each output signal node in the block schematic diagram of Fig. 2 to Fig. 3 (E), wherein:
Synoptic diagram, Fig. 3 (B) that Fig. 3 (A) illustrates ADC sampling back output signal illustrates the synoptic diagram that the synoptic diagram of regularly replying interpolating circuit module output signal, synoptic diagram, Fig. 3 (D) that Fig. 3 (C) illustrates change circuit module output signals such as 2T time illustrate twice factor interpolating circuit module output signal, and Fig. 3 (E) illustrates the synoptic diagram of tandem detector output signal.
Fig. 4 illustrates the thin portion of the twice factor interpolating circuit module calcspar according to the optical memory system of the inventive method design.
Fig. 5 illustrates the synoptic diagram that carries out the output of two sample input-two bits according to the tandem detecting device of the optical memory system of the inventive method design with the Trellis state transition diagram.
Fig. 6 illustrates the block schematic diagram according to the optical memory system numeral fetch channel of second embodiment of the present invention design.
Fig. 7 illustrates the block schematic diagram according to the optical memory system numeral fetch channel of third embodiment of the present invention design.
Because optical memory system, traditional analog fetch channel or the existing problem of digital fetch channel, with method provided by the present invention, the subsample (sub-sampled) that is provided compared to conventional digital fetch channel sampling method or Bliss will have more competitiveness.Because the frequency range limit system (bandwidthlimit) of the frequency spectrum (frequency spectrum) of the analog signal read-back (analog read-backsignal) of optical storage media is 1/ (4T), therefore the inventive method, be with (1) at first A/D speed only be slightly larger than half channel rate (about 1/ (2T)); (2) then carry out downward sampling with 1/ (2T) speed, to produce the interpolation sampling regularly to reply interpolater; (3) eqalizing cricuit with the 2T time interval compensates the interpolate value of an above-mentioned half rate and data that miss with two adjacent interpolate values of 2 times of number interpolating circuits generations centre at last (4) again.Therefore, the design or the element of A/D sample circuit will be simpler, and the same circuit that carries out interpolation also can be because of its speed needn't be as the speed of fetch channel fast (half gets final product only to need it), so the required number of element can be simplified especially.
The first preferred embodiment explanation of digital channel reading system of the present invention, calcspar with reference to shown in Figure 2 comprises A/D sample circuit module 100 at least, frequency generator module 110, regularly reply interpolating circuit module (timing recovery interpolator module is called for short TRI) 120, time schedule controller (timing control circuit) 130, the 2T time etc. are changed circuit module (2T-spaced equalizer) 140, direct current off normal control circuit 150, twice factor interpolating circuit module (factor2 interpolator) 160 and tandem detecting device (sequence detector) 190.Wherein, twice factor interpolating circuit module (factor2 interpolator) 160 exports two adjacent interpolation data with tandem, and feedback signal 170 and 180 respectively to direct current off normal control circuit 150 and sequential control die set 130, to adjust the opportunity of opening or closing.
Function and its mutual relationship of each circuit module below will be described respectively.At first A/D sample circuit module 100 is made up of a low-pass filter and sample circuit, the fixed frequency f_s that is provided with frequency generator module 110 carries out the sampling of fetch channel simulating signal, with a preferred embodiment, the f_s sampling frequency is about half or slightly high getting final product of simulating signal speed (1/T) that read head reads, A/D sampling output synoptic diagram with Fig. 3 A is an example, and selected speed is about 8/7*1/ (2T).With this sampling frequency, can significantly reduce the required number of elements of A/D sample circuit.
Still with reference to figure 2, the data of A/D sample circuit module 100 samplings is followed incoming timing and is replied interpolating circuit module TNI120 to carry out the interpolation sampling.Regularly replying the interpolating circuit module is a finite impulse response (FIR) filtering circuit (finite impulse responsefilter, simple FIRF).F1RF is that a kind of response of the input signal to unit pulse is the digital filter of finite length sequence, and it has accurate linear phase characteristic.
Because the frequency of TRI120 sampling is provided by sequential control module 130, with a preferred embodiment, the frequency that sequential control module 130 provides is about half of frequency of fetch channel.Sequential control module 130 also is subjected to the feedback signal 180 that twice factor interpolating circuit module 160 provides and adjusts the opportunity that TRI120 carries out the interpolation sampling, can determine when open or close.In this step still not with each bit data with interpolation polishing (so the bit born of the same parents (bit cells) of per two passages only need to calculate a sample), its reason is: because of the sequential (clock) of wafer is that the sequential of fetch channel is divided by 2, be I/ (2T), so can simplify assembly (component) number and the design complexities of regularly replying interpolating circuit module 120.
Yet, (frequency is about the data that 8/7*1/ (2T) obtains from A/D sample circuit module 100 owing to TRI120, when the interpolation of putting sometime (interpolation), in order to the A/D sampling spot that calculates as this time point and the distance of this time point is not equidistant, but time to time change.For satisfying this situation, then be to set up interpolation polynomial coefficient (timing-varying coefficient) form that regularly changes earlier, then, obtain multinomial coefficient by TRI 120 according to the gap of each time point in the time enquiry form, to calculate the interpolate value of every 2T time point.For example, the interpolation data of the k1 time of Fig. 3 B is that m1, m2, m3, m4, the m5 with Fig. 3 A, a plurality of data of m6 equi-time point are carried out interpolation, because both made m1, m2, m3, m4, m5, m6 equidistant, but with respect to the k1 time, m4 is not equidistant to k2 with the m5 that calculates the k2 time to k1.Therefore, have only according to the coefficient of the coefficient in the time enquiry form and could calculate as interpolation polynomial.
Please note, when the IC sequential is supplied A/D sample circuit module 100 with the frequency of fs, regularly reply 120 of interpolating circuit modules and be per second sampling rate synchronized sampling with 1/ (2T), in other words, when interpolating circuit module 120 produces an effective sampling value, attached sequential just allows to carry out next routine processes subsequently, when interpolating circuit 120 not in effect when (not activated), attached sequential just lost efficacy (disable), and this part is the back coupling signal 180 that is provided by twice factor interpolating circuit module 160 and controlling.Therefore, on average, per second will have the clock pulse of (fs-1/ (2T)) to lose efficacy, and the clock pulse of 1/ (2T) is activation (enable).
After carrying out the sampling of 1/ (2T) timing interpolation, change circuit module such as a 2T time 140 are then carried out the high-frequency signal compensation of data with 1/ (2T) timing interpolation data value.This is because of judgement that general DVD or CD laser disc system read two bit datas is with on crosspoint or judge that data is 1 or 0, therefore, as long as just have the interference of noise very likely to cause the differentiation mistake of data.Best mode is that the high-frequency signal of being omitted when A/D is taken a sample compensates.The amplitude of the signal of every 2T timing material point will suitably improve with amplifier shown in Fig. 3 C, so that signal amplitude height more obviously (away from the absolute time countershaft), but the HFS overcompensation also can not be added into otherwise have more noise.
Subsequently, twice factor interpolating circuit module 160 also feedback simultaneously signal 170 with control direct current off normal control circuit 150 effect (activated) or do not act on (non-activated) period (period) after eliminate the direct current off normal (negative value) of non-data signal via mixing device 145 again.
Because all do not obtain data in each T in the above-mentioned step, but get in interval time a bit at every 2T, therefore, twice factor interpolating circuit module 160 (with reference to figure 2) is in order to the sampling data polishing (with reference to figure 3D) with each bit.With a preferred embodiment, twice factor interpolating circuit is that most material points of utilization will be as the reference of computing, the multiple-effect fruit is better certainly more for the reference point of interpolation in utilization, but need get final product by 6 to 8 material points approximately based on the cost consideration of hardware structure and actual needs.For convenience of description how for the purpose of the computing, with reference to figure 4, suppose among Fig. 4 that X (n) point is a material point for the treatment of decision (pending), X (n) point is forward and backward, every 2T time interval has material point X (n-5T), X (n-3T), X (n-1T), X (n+1T), X (n+3T), the X (n+5T) of three references respectively, and is stored in respectively among working storage a, b, c, d, e, the f.Six constant coefficient C3, C2, C1, C1, C2, C3 that are stored in working storage 210 utilize six multipliers 220 to multiply each other respectively, and its product is stored in the totalizer 230.
Result through 160 computings of twice factor interpolating circuit module, except waiting to ask the X (n) by totalizer 230 outputs in sequential activation (clock enable), please noting has the impact damper 240 that carries out time delay 2T in addition among Fig. 4, could guarantee that like this two adjacent samples can export the value of X (n-T) simultaneously.Though the result of twice factor interpolating circuit module 160 computings has made the high or low of signal differentiate, shown in Fig. 3 D.But, but for the interference that prevents noise still needs tandem detecting device 190 at the data sample of two inputs of sequential activation phase single treatment and produce two digital output data to carry out the output of tandem dual code, its result please refer to shown in Fig. 3 E.
Fig. 5 illustrates how tandem detecting device 190 of the present invention (with reference to figure 2) utilizes two data samples that the single treatment of Trellis state transition diagram imported by twice factor interpolating circuit module 160 becoming one group tandem data, and order to produce two bits be one group dual code output.Because disc storage medium, DVD for example, minimum execution length (run-length) is 3, and do not allow independent dual code to occur, the state of " 010 ", " 101 " or have only two identical dual codes to occur simultaneously for example, for example cascade sequence " 0110 " or " 1001 " all be forbid to avoid reading the data that makes the mistake because of noise.Therefore at the data sample of two inputs of twice factor interpolating circuit module 160 1 less important processing, and produce two digital output data.Wherein last bit (b1) in every tuple (b3b2b1) of first file 250 is the situation in order to two input data samples (c2c1) maximum possible shown in 260 of inferring present input, 270 of the 3rd files are according to last bit of bit group (b3b2b1) (b1) of first file 250 and at present by 260 two inputs (c2c1) combinations of importing, to export new possible bit group (d3d2d1).
File 270 bit groups (d3d2d1) become the previous possibility bit group that twice factor interpolating circuit module 160 next group are exported, immediately promptly by (d3d2d1) a (b3b2b1).According to this, after tandem detecting device (sequence detector) 190 has received the array data sample in regular turn, promptly can be according to the path of front and back, comprehensively judge and to proofread and correct the mistake that causes because of noise extremely low or do not have the output of the digital dual code of (error free) to obtain complete error rate.
For example, at present the input of tandem detecting device 190 maximum possible is " 11 ", the previous dual code of interpretation have following several may be " 000 ", " 001 ", " 011 " or " 111 " other are all impossible, shown in file 250.Therefore the result of the digital dual code that may export at last then is " 011 " or " 111 " in second file 270, and other are all impossible.In addition, and for example 240 inputs of fruit tandem detecting device is " 01 ", and then previous first file 250 has only " 000 " or " 110 " for possible, and Shu Chu dual code has only " 001 " for allowing according to this.Therefore, utilize above-mentioned Trellis state transition diagram, the relation of proofreading and correct each other each other can be in order to pick the mistake that noise causes.
Because most important idea of the present invention is to use (1) eqalizing cricuit to allow every 2T-time interval to get a data, (2) to guarantee to reduce A/D speed, can not cause distortion with twice factor interpolating circuit.Position as for direct current off normal control circuit 150 is then also non-key, for example, among above-mentioned first embodiment, be after change modules 140 such as 2T-time are earlier to the data signal operation, remove flip-flop again, and according to the second embodiment of the present invention, design as shown in Figure 6, direct current off normal control circuit 150 and to mix 145 of devices be to be arranged between the change modules 140 such as regularly replying interpolating circuit module 120 and twice time, therefore, when regularly reply interpolating circuit module 120 carry out with A/D sampling module 100 asynchronous interpolations after, utilize and mix device 145 direct current off normal control circuit 150 is imported to remove flip-flop.
In addition, preferred embodiment of the present invention also can be changed to the 3rd embodiment as shown in Figure 7.Direct current off normal control circuit 150 and mix device 145 after A/D sampling module 100 is taken a sample promptly is about to flip-flop earlier remove, and carries out regularly replying the operation of interpolating circuit module 120 again.Because above-mentioned second embodiment and the 3rd embodiment only do suitable adjustment with direct current off normal control circuit 150 and the position of mixing device 145, other each module square functions are identical, therefore do not repeat them here.
The present invention with the preferred embodiment explanation as above, is not in order to limit application range of the present invention only.