CN1338681A

CN1338681A - Memory controller with page organizer

Info

Publication number: CN1338681A
Application number: CN 01109961
Authority: CN
Inventors: 吕忠晏
Original assignee: Silicon Integrated Systems Corp
Current assignee: Silicon Integrated Systems Corp
Priority date: 2000-08-15
Filing date: 2001-03-27
Publication date: 2002-03-06
Also published as: TW544575B

Abstract

A memory controller with page organizer is disclosed, which can detect the page-miss event in a multi-bank memory. When a page-miss event occurs in a memory bank, an overhead command is sent to it. As a result, when a memory bank is accessed by current memory request, the access set-up job for the memory bank suffering from the page-miss event has been done. So said overhead command is hidden by current access. The sequence of memory requests can not be changed.

Description

Memory Controller Hub with page organizer

The present invention is about a kind of Memory Controller Hub, particularly about a kind of Memory Controller Hub with page organizer, this Memory Controller Hub is before the memory set to no page loss situation sends an access command, the memory set that page loss situation is arranged is sent a preposition order, and reduce the loss (page-miss penalties) that the page is lost generation.

Memory Controller Hub focalization page during memory access of many known technologies is lost the reduction of loss.Wherein there is many known technologies system to utilize memory set (page) (bank (page)-interleaving) technology of interlocking.Page interleaving technique can distribute successional data in different memory set.Through planting method thus, may stride through many different memory set when desiring the successional data of access.On the typical case, memory access comprises preposition order and access command.Preposition order comprises pre-charge (pre-charge) and starts (activate) order, and access command comprise read, write, bursting to read (burst-read) or burst writes (burst-write) order.When access data in different memory set, some preposition orders can overlapping (overlapped) or flowing water (pipelined) mode handle.Thereby the loss that the page is lost can be used many known technologies and reduce.

Rearrange the memory access order and also can reduce the loss that the page is lost.This rearranges and comprises three steps on the method typical case.First step system sends memory access request, second step system stores these requests, and third step system makes arbitration (arbitration) to each memory access request, loses the target of loss to reach the reduction page.Widely known is that transmission and storage step relate to sorts out the memory access request of access same page part.Arbitration step system selects each time and sends one group of request, and one group of ground these request of transmission in a winding.

Yet the method for rearranging can cause the order confusion reigned of the data of being returned.The confusion of this kind order will be a problem for processor.Therefore, must in system, provide a sequential circuit (order circuit), perhaps must add label, correctly to carry out data processor in each memory request.Above-mentioned two kinds of known technology methods that solve chaotic problem all do not meet cost benefit.

The present invention is a Memory Controller Hub, and this Memory Controller Hub can reduce the loss that the page is lost, and the problem of no datat confusion.Method provided by the present invention system is with detecting the situation that the page is lost in advance, when carry out relevant other memory set of access read (or writing) order the time, carry out the preposition order of relevant access one memory set earlier.When Memory Controller Hub had been ready for sending in access order to a storer partly, whether Memory Controller Hub is at first checked had any page to lose in other storer.After the preposition order (if necessary) of all other storeies of access had sent, the order of access part just was sent out.Through planting method thus, Memory Controller Hub reduces the page and loses loss, and improves the usability of memory access.And the present invention can not cause the confusion of access sequence.

Fig. 1 shows a known memory system that is connected to a disposal system.

One simplified block diagram of Fig. 2 explicit declaration one Memory Controller Hub.

Fig. 3 shows according to the simplified block diagram with Memory Controller Hub of page organizer of the present invention.

Fig. 4 shows that one is used in the simplified block diagram of the page organizer of dual-memory group (dual bank) memory system.

Fig. 5 shows that one is used in the simplified block diagram of the page organizer of multi-memory group (multiple-bank) memory system.

Fig. 6 shows the block scheme of a page loss detector.

Fig. 7 shows that one is used in the operation process chart of the instruction control unit of dual-memory group system.

Fig. 8 is that an example shows how the present invention reduces the loss that the page is lost.

As shown in Figure 1, known memory system is made up of DRAM (Dynamic Random Access Memory) (DRAM) 11, via Memory Controller Hub 15 by processor 13 accesses.This Memory Controller Hub 15 sends a request to DRAM (Dynamic Random Access Memory) 11 via first bus (bus) 12.These memory request are not the requests of reading, and write request exactly.This Memory Controller Hub 15 is connected to disposal system 13 via one second bus 14.As shown in Figure 2, this known Memory Controller Hub comprises an input buffer 20, an output buffer 22, an instruction control unit 24, and a data sink 26.Input buffer 20 receives and stores memory request.Output buffer 22 is connected to data sink 26, and stores the data from DRAM (Dynamic Random Access Memory) 11, and sends output data.Instruction control unit 24 is fetched order from input buffer 20, and sends for example PRECHARGE (pre-charge), ACTIVATE (startup), READ (reading), WRITE orders such as (writing), with the operation of control DRAM (Dynamic Random Access Memory).Data sink 26 is via the GrantCMD signal wire, and the scheduled timing flow process according to instruction control unit 24 is notified receives data from DRAM (Dynamic Random Access Memory) 11.On the typical case, PRECHARGE order cause corresponding memory set carry out pre-charge operation, ACTIVATE order start in the corresponding memory pool address row (memory set) partly, READ or WRITE order start row (low) part in the corresponding memory pool address.

Fig. 3 shows one of the present invention embodiment, it comprises an input buffer 20, an output buffer 22, an instruction control unit 24, a data sink 26 and particularly one page covering weave device 30, this page organizer 30 is organized the page address of memory request, loses incident with the decision page.Except page organizer 30, the novelty that the present invention is better than known Memory Controller Hub also comprises the operation in the instruction control unit 24.By page organizer 30, Memory Controller Hub detects in advance corresponding to the page of each memory request of each memory set loses incident.Then, Memory Controller Hub is overlapped by the access command of the preposition order of the memory set that will have page loss situation and other memory set, and improves access usefulness.

Fig. 4 and Fig. 5 show the embodiment of the page organizer 30 that is used in dual-memory group and multi-memory group memory system respectively.In Fig. 4, page organizer 30 comprises two first in first out (FIFO)

impact damper

40,42, and two page loss detectors 41,43.The corresponding page loss detector of each impact damper, and an also corresponding memory set, this memory set is by 24 accesses of instruction control unit.The page of address partly is stored in corresponding in the impact damper of the memory set of access in memory request 45.For example, impact damper 40 is stored in the page number (page number) of the access memory group 0 that shows in the request bus 45, and impact damper 42 is stored in the page number of the access memory group 1 that shows in the request bus 45.Page number can correctly be stored in the

impact damper

40 or 42 of a correspondence by arbitrary widely known method.Page loss detector 41 decision to input page data of its input whether be stored in page loss detector 41 in the page address be identical.Page loss detector 43 decision to input page data of its input whether be stored in page loss detector 43 in the page address be identical.Fig. 6 shows the embodiment of a page loss detector.This page loss detector comprises the page (pre-page) register 64 before a comparator circuit 62 and, to store before the page address at the access request of same memory set.If the page signal 65 that enters is identical with the address 67 in preceding page register 64, then hit (hit) signal be triggered (asserted).Otherwise hiting signal is by write off.Whether hiting signal notification command controller 24 has a page to lose incident in corresponding memory set.When initial, preceding page register 64 is reset, so that hiting signal is by write off.In addition, the page signal 65 that enters is input to instruction control unit 24, as shown in Figure 4.Same, for the system that k memory set arranged, k=0 wherein, 1 ...., N-1, the arrangement of page organizer 30 is as shown in Figure 5.That is, the corresponding page loss detector of each impact damper, and an also corresponding memory set, this memory set system is by 24 accesses of instruction control unit.

Except order, address, and outside the data-signal, instruction control unit 24 also receives the hit signal from page loss detector, and page signal.Instruction control unit 24 one after the other is received in the interior memory request of input buffer 20, and instruction control unit 24 is through each memory request of two phase process.In the phase one, instruction control unit 24 sends the preposition order of memory request, for example pre-charge order and startup command.In subordinate phase, instruction control unit 24 sends the access command of memory request, for example reads, bursts and read, write or the write command of bursting.Yet, it should be noted that not to be that all memory request all need to send a preposition order.

When a memory request does not run into page loss situation, instruction control unit 24 not for this reason memory request send a preposition order.In the present invention, a group mark (flag (k)) is based upon in the instruction control unit 24, wherein the initial status of respectively corresponding each memory set of each sign.The corresponding memory set k of each flag (k), k=0 wherein, 1 ...., N-1.When a flag (k) is (=1) activated, this means and stops start-up time to the previous operations of storer k (lapsed).On the contrary, when (=0) of a flag (k) right and wrong activity, mean the start-up time of termination as yet to the previous operations of memory set k.

With flag (k), all hiting signal, and the state of first-in first-out buffer is the basis, the memory request that instruction control unit 24 is handled in input buffer 20.The state of first-in first-out buffer will point out whether first-in first-out buffer is empty (emptiness).In process flow diagram 7, be assumed to be a pair of memory set system.As shown in Figure 7, at first in step 703, whether inspection of the present invention has any request in input buffer.If yes, the present invention handles first request in input buffer, and this request is called as request (processingrequest) in the processing.Be called as existing memory set (current bank) with the memory set of request associated in the processing.In step 705, the present invention checks whether existing memory set has page loss situation.If yes, the present invention checks in step 707 whether initiating task is sent.If yes, then whether execution in step 711 stops with inspection startup effect.On the typical case, have three clock period (clock cycle) start-up time.If yes, in step 713, the present invention sets flag (0)=1.

If in step 705 is that then execution in step 713.If in step 707 is that then execution in step 709, whether send to check the pre-charge operation.Whether if yes, then execution in step 710, stop to check the pre-charge time.On the typical case, there are three clock period the pre-charge time.If yes, then execution in step 717, to send initiating task.If be that then execution in step 715 in step 711 or step 710, to set flag (0)=0.If be that then execution in step 719 in step 709, to transmit the pre-charge operation.

No matter after step 713 or step 715, all execution in step 721, to check any request whether corresponding other memory set is arranged in input buffer.If yes, the present invention checks whether this memory set has a page loss situation.If yes, whether inspection of the present invention initiating task in step 725 is sent.If yes, then execution in step 729, whether to check flag (0)=1.If yes, in step 733, access operation is sent.

If be that then execution in step 729 in step 721.If be that then execution in step 727 in step 725, whether be sent to check the pre-charge operation.If yes, whether the present invention tests the pre-charge time and stops in step 731.If then execution in step 729 not.If yes, initiating task is sent in step 735.If in step 727 is that the pre-charge operation is not sent in step 737.

In order to show the advantage of the present invention with respect to known schemes, Fig. 8 shows an example.As shown in the figure, from the period 0 to 5, input buffer 20 receives 6 memory access request.First request is reading operation at (memory set 0 and page x1) for reading operation, the 3rd request at (memory set 0 and page x1) for reading operation, the 4th request at (memory set 0 and page x1) for reading operation, second request to (memory set 0 and page x1), and the 5th request is the reading operation at (memory set 1 and page x2) for reading operation, the 6th request at (memory set 1 and page x2).In other words, the memory request order in the input buffer 20 is represented to be stored in second hurdle of Fig. 8.It should be noted that in Fig. 8, not specialize and be listed as by the internal memory of access.Third column in Fig. 8 represents how known Memory Controller Hub sends the internal memory order to these memory request.For example, sending the pre-charge operation at period 1 middle controller sends to memory set 0, at periods 4 middle controller and activates operation to (memory set 0, page x1), send reading operation respectively to (memory set 0 in

period

7,8,9 and 10 middle controllers, page x1), sending the pre-charge operation at periods 11 middle controller sends to memory set 1, at periods 14 middle controller and activates operation to (memory set 1, page x2), send reading operation respectively to (memory set 1, page x2) in

period

17 and 18 middle controllers.

In comparison, the order that sent of instruction control unit 24 of the present invention is presented in the 4th hurdle of Fig. 8.That is, send the pre-charge operation to memory set 0 at period 1 middle controller, send initiating task to (memory set 0 at periods 4 middle controller, page x1), send the pre-charge operation to memory set 1 at periods 5 middle controller, send reading operation to (memory set 0 at periods 7 middle controller, page x1), send initiating task to (memory set 1 at periods 8 middle controller, page x2), in the

period

9,10 and 11 middle controllers send reading operation respectively to (memory set 0, page x1), send reading operation respectively to (memory set 1, page x2) in

period

12 and 13 middle controllers.As can be seen, all correspondence orders were all finished before the end of period 13, this period 13 compared with period 18 of known schemes early a lot.By page organizer provided by the present invention, the loss that the page is lost reduces significantly.

Claims

One kind control one memory system Memory Controller Hub, this memory system has N memory set, and each N memory set is split into a plurality of pages, and this Memory Controller Hub is connected to a processor via a bus, N is the integer greater than 1, it is characterized in that described Memory Controller Hub comprises:

One input buffer, in order to store the memory request from this processor, each memory request comprises page number data at least;

One page covering weave device responds this page number data, and the page that is used for detecting respectively each N the relevant memory request of memory set is lost incident; And

One instruction control unit responds this page and loses incident, sends a preposition order to having the memory set that the page is lost incident with interlace mode, and sends an access command and do not lose other memory set of incident to there being the page.
According to claim 1 described within memory controller, wherein this input buffer is a first-in first-out buffer.
According to claim 1 described within memory controller, wherein this preposition order comprises:

One pre-charge order; And

One startup command.
According to claim 1 described within memory controller, wherein this access command comprises a reading order.
According to claim 1 described within memory controller, wherein this access command comprises the reading order of bursting.
According to claim 1 described within memory controller, wherein this page organizer comprises:

N page buffer, each page buffer are stored these page number data in a memory request, the corresponding memory set of this memory request; And

N page loss detector, the corresponding page impact damper of each page loss detector is lost incident with the page of the memory set that detects relevant memory request.
According to claim 6 described within memory controller, wherein each page loss detector comprises:

One register is in order to store the page number data at the relevant previous memory request of a corresponding memory set; And

One device, this device are used for existing page number data of comparison one and the page number data that are stored in register.
8. in a Memory Controller Hub, receive a plurality of memory request, these a plurality of memory request access one memory systems, this memory system has N memory set, these a plurality of memory request are divided into an existing memory request and unsettled (pending) memory request, corresponding each memory request of this Memory Controller Hub optionally sends a preposition order and an access command, a kind of method of handling memory request is characterized in that described method comprises following steps:

Store these a plurality of memory request in an input buffer;

One page address of corresponding each memory request is stored to a page impact damper the corresponding memory set of this page buffer respectively;

At a plurality of memory request, the decision storage stack group experience page is lost incident; And

Send preposition order with interlace mode, and send the access command of this existing memory request of correspondence this unsettled memory request that should organize memory set.