CN1336716A - Zero-voltage switch double-PWM frequency converter - Google Patents
Zero-voltage switch double-PWM frequency converter Download PDFInfo
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- CN1336716A CN1336716A CN00119526A CN00119526A CN1336716A CN 1336716 A CN1336716 A CN 1336716A CN 00119526 A CN00119526 A CN 00119526A CN 00119526 A CN00119526 A CN 00119526A CN 1336716 A CN1336716 A CN 1336716A
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Abstract
The invention relates to a three-phase voltage type pulse width modulating (PWM) frequency transformer. The characteristics are: the intermediate link in main circuit is a zero-voltage switching circuit, the closing of every semiconductor power switch components on bridge arm are occurred within the region that DC voltage of main circuit is zero, the actions of every semiconductor power switching components are started and drived by PWM pulse generated by PWM generating circuit or microprocessor. Besides the advantages in normal double PWM frequency transformer, it can slow down voltage changing rate, reduce switcher loss and eliminate electromagnetic interference generated by hard switch.
Description
The present invention relates to a kind of three-phase voltage type pulse-width modulation (PWM) frequency converter.
Traditional voltage type PWM frequency converter, the AC-DC current transformer of its input side are to adopt uncontrollable diode rectifier (see figure 1), contain serious harmonic components in the input current, cause that input power factor is low, harmonic pollution is serious.In order to overcome these shortcomings, generally adopt the two PWM frequency conversion scheme (see figure 2)s of hard switching.Though this scheme can improve power factor, still, its voltage and current jumpy makes semiconductor power switch device bear very big electric stress, causes serious electromagnetic interference, and the semiconductor power device switching loss is also very big.
The objective of the invention is to provide a kind of Zero-voltage switch double-PWM frequency converter, can keep High Power Factor, can suppress electromagnetic interference again, reduces the switching loss of semiconductor power device.
The object of the present invention is achieved like this: a kind of Zero-voltage switch double-PWM frequency converter, have input side AC-DC current transformer, outlet side DC-AC inverter, at the major loop that intermediate link constituted between input side and the outlet side and the electric current and voltage detection between microprocessor, microprocessor and the major loop and treatment circuit, semiconductor power switch device drive circuit, the intermediate link that it is characterized in that major loop is a zero voltage switch circuit, and it is by semiconductor power switch device V
C1, V
C2, diode VD
C1, VD
C2, capacitor C
D1, C
D2And inductance L
rForm semiconductor power switch device V
C1Emitter meets the dc bus P utmost point and diode VD
C1Anode, semiconductor power switch device V
C1Collector electrode connects capacitor C
D1With diode VD
C1Negative electrode, capacitor C
D1Another termination capacitor C
D2And inductance L
r, capacitor C
D2Another termination dc bus N utmost point; Semiconductor power switch device V
C2Collector electrode meets the dc bus P utmost point and diode VD
C2Negative electrode, semiconductor power switch device V
C2Emitter meets diode VD
C2Anode and inductance L
rThe other end; Buffer capacitor in parallel on each semiconductor power device of current transformer and inverter; Each semiconductor power switch device opens that all to drop on direct voltage on the major loop be to take place in zero the interval on the brachium pontis.
Described Zero-voltage switch double-PWM frequency converter is characterized in that, pwm pulse is by voltage comparator U
1, U
2, inverter U
3, driver U
4, U
5And the circuit that current zero crossing detector constitutes generates; The sawtooth wavelength-division two-way of input, one road direct sending voltage comparator U
1End of oppisite phase, another road is through resistance R
1After deliver to inverter U
3End of oppisite phase, U
3In-phase end ground connection, U
3End of oppisite phase through resistance R
2Be connected to U
3Output, this output is connected to voltage comparator U
2End of oppisite phase; The modulating wave e of input also divides two-way, and one the tunnel send voltage comparator U
1In-phase end, voltage comparator U is sent on another road
2In-phase end; U
1Output be connected to driver U
4Input, U
2Output be connected to driver U
5Input; U
4Output termination one OR-gate U
6An input, U
5Output termination U
6Another input; U
6Output divide two-way, the one road drives the semiconductor power switch device IGBT of the last brachium pontis of inverter, another Lu Jingyi inverter U
7The semiconductor power device IGBT of the following brachium pontis of rear drive inverter; Signal by current zero crossing detector output is connected to driver U
4Key player on a team go side and driver U
5Negative gating end; In phase current i＞0 o'clock, adopt positive slope sawtooth waveforms and modulating wave e relatively to produce pwm pulse; In phase current i＜0 o'clock, adopt through inverter U
3The negative slope sawtooth waveforms and the modulating wave e that generate after the paraphase relatively produce pwm pulse.
Described Zero-voltage switch double-PWM frequency converter is characterized in that pwm pulse is generated by microprocessor, provides the polarity transformation identification signal of phase current i by a current polarity judging circuit, in phase current i＞0 o'clock, adopts the modulation of positive slope sawtooth waveforms; In phase current i＜0 o'clock, still adopt the modulation of positive slope sawtooth waveforms, use e '=1-e replacement e modulating wave, the validity of production burst is opposite with the former; The current polarity judging circuit is by inverse gate U
1, or the door U
2, three input NOR gate U
3, delay circuit, Dead Time form circuit, resistance R
3, photoelectrical coupler U
4, resistance R
4, Schmidt's reshaper U
5, inverse gate U
6, with the door U
7, U
8, or the door U
9, d type flip flop U
10Constitute, drive semiconductor power switch device V
C1The control signal of IGBT is through inverse gate U
1After be connected to or the door U
2Input drives semiconductor power switch device V
C2The control signal of IGBT directly is connected to or door U
2Other end input, or door U
2Output is connected to three input NOR gate U
3An input; Pwm control signal is delivered to Dead Time and is formed circuit, and Dead Time forms two signals of circuit output, and one is delivered to three input NOR gate U
3An input, remove to drive the semiconductor power device IGBT of brachium pontis on each of inverter simultaneously, it two delivers to three input NOR gate U
3Another input, each that removes to drive inverter simultaneously be the semiconductor power device IGBT of brachium pontis down; Three input NOR gate U
3Output be connected to delay circuit, the output of delay circuit divides two-way, the one tunnel connect with the door U
7An input, another road connect with the door U
8An input; The voltage U that detects by main circuit inverter bridge output U and direct current negative busbar N
UN, its U end is through resistance R
3After meet photoelectrical coupler U
4Diode anode, this diode cathode of N termination; Photoelectrical coupler U
4Transistor collector meet control power supply V
Cc, its emitter connects the ground end of controlling power supply through resistance R 4, and this emitter is through Schmidt's reshaper U
5Two-way is divided in the back, and one connects and door U
7Another input, it is two through inverse gate U
6Send after anti-phase and door U
8Another input; With door U
7Output connect or the door U
9An input, with door U
8Output connect or the door U
9Another input; Or door U
9Output meet d type flip flop U
10Clock end or remove the micro processor controls signal input part, d type flip flop U
10Q be connected to D end, the Q end removes the micro processor controls end.
Technique effect of the present invention is: except that having general voltage switch double-PWM frequency converter High Power Factor, utilize the resonance action between buffer capacitor and the zero voltage switch circuit, make all semiconductor power devices all open-minded when the direct current bus bar pressure is zero, and because buffer capacitor in parallel exists, the shutoff of these semiconductor power devices always begins under the no-voltage situation, thereby the realization no-voltage is opened with no-voltage and is turn-offed, slow down the rate of change of voltage greatly, reduce the switching loss of semiconductor power device; Owing to substitute the hard switching action, eliminated the electromagnetic interference that causes because of hard switching again with zero voltage switch.
Be further described below in conjunction with embodiments of the invention and accompanying drawing thereof.
Fig. 1 is the main circuit of converter of known band diode rectifier.
Fig. 2 is known three-phase hard-switched current transformer-converter main circuit.
Fig. 3 is the main circuit and the control block diagram of the embodiment of the invention one.
Fig. 4 is the main circuit and the control block diagram of the embodiment of the invention two.
Fig. 5 is the pwm pulse generative circuit figure (U phase) among the embodiment one.
Fig. 6 is the current polarity judging circuit figure (U phase) among the embodiment two.
Fig. 7 is a main circuit equivalent circuit diagram of the present invention.
Fig. 8 is the equivalent circuit diagram of Fig. 7.
Fig. 9 is the harmonic motion operation mode of main circuit.
Oscillogram when Figure 10 is resonance.
Figure 11 is a sawtooth waveforms PWM modulation schematic diagram.
Figure 12 is that inverter U phase current flows to schematic diagram.
Figure 13 is the switching schematic diagram of sawtooth waveforms.
Figure 14 is a timing chart of realizing PWM modulation (U phase) with software approach.
Figure 15 is a positive slope modulation schematic diagram.
Figure 16 is a negative slope modulation schematic diagram.
Embodiment one shown in Figure 3, lead-out terminal R, the S of three phase mains 1, T are respectively through inductance L
R, L
S, L
TReceive on R ', S ', the T ' terminal of AC-DC current transformer.The upper and lower semiconductor power device V that is connected to respectively of R ' brachium pontis
1And V
4, V
1On be parallel with diode VD
1With the buffering capacitor C
1, V
4On be parallel with diode VD
4With the buffering capacitor C
4The upper and lower semiconductor power device V that is connected to respectively of S ' brachium pontis
2And V
5, V
2On be parallel with diode VD
2With the buffering capacitor C
2, V
5On be parallel with diode VD
5With the buffering capacitor C
5Be connected to semiconductor power device V on the T ' brachium pontis respectively
3And V
6, V
3On be parallel with diode VD
3With the buffering capacitor C
3, V
6On be parallel with diode VD
6With the buffering capacitor C
6V
1, V
2, V
3Collector electrode all receive on the anodal P of dc bus V
4, V
5, V
6Emitter all receive on the negative pole N of dc bus.
The outlet side of frequency converter, promptly the structure of DC-AC inverter section and AC-DC current transformer are similar, its output U, V, W and join as the winding input of load 2 (as three phase electric machine).The upper and lower semiconductor power device V that is connected to respectively of U brachium pontis
7And V
10, V
7On be parallel with diode VD
7With the buffering capacitor C
7, V
10On be parallel with diode VD
10With the buffering capacitor C
10The upper and lower semiconductor power device V that is connected to respectively of V brachium pontis
8And V
11, V
8On be parallel with diode VD
8With the buffering capacitor C
8, V
11On be parallel with diode VD
11With the buffering capacitor C
11The upper and lower semiconductor power device V that is connected to respectively of W brachium pontis
9And V
12, V
9On be parallel with diode VD
9With the buffering capacitor C
9, V
12On be parallel with diode VD
12With the buffering capacitor C
12V
7, V
8, V
9Collector electrode all receive on the anodal P of dc bus V
10, V
11, V
12Emitter all receive on the negative pole N of dc bus.
Intermediate link is a zero voltage switch circuit, semiconductor power device V
C1Emitter and V
C2Collector electrode all receive on the anodal P of dc bus.V
C1With diode VD
C1After the parallel connection, its collector electrode connects capacitor C
D1, C
D1The other end and capacitor C
D2Join C
D2The other end be connected with the negative pole N of dc bus.C
D1With C
D2Tie point and inductance L
rConnect.V
C2With diode VD
C2After the parallel connection, its emitter and above-mentioned inductance L
rThe other end join.
The input side of frequency converter, outlet side, intermediate link constitute major loop, are provided with electric current and voltage detection and treatment circuit 4, semiconductor power switch device drive circuit 7 between a microprocessor 3 and the major loop.
Embodiment two shown in Figure 4 and the major loop of embodiment one, microprocessor 3, electric current and voltage detects and treatment circuit 4, semiconductor power switch device drive circuit 7 are identical.
The present invention is the resonance action that utilizes between buffer capacitor and the zero voltage switch circuit, makes all semiconductor power devices all open-minded when the direct current bus bar pressure is zero.For the resonance action of main circuit is described, can represent with equivalent electric circuit Fig. 7.Because therefore the carrier frequency of current transformer-inverter, can think that the input current of current transformer and the output current of inverter are constant in a carrier cycle far above the output frequency of mains frequency and inverter, thereby can use constant current supply I
SAnd I
LRepresent input current and output current.And because C
D1, C
D2Capacity is very big, C in a carrier cycle
D1, C
D2On voltage certain substantially, for simplicity, use E among Fig. 7 respectively
d/ 2 represent C
D1, C
D2On voltage.Vs among Fig. 7, VDs, Cr represent power switch, fly-wheel diode and the buffering electric capacity of current transformer and inverter respectively.Because the last underarm power switch of three-phase bridge always has a side to connect, so get Cr=3Cs among Fig. 7.During the voltage U cr of Cr was zero, the power switch of three-phase bridge moved switching.Because during system works, the switch change action of current transformer and inverter carries out synchronously, so Fig. 7 can further represent with Fig. 8 equivalent electric circuit, at this moment Cr=6Cs.The switch motion of following analysis chart 8, it is made up of 9 patterns, as shown in Figure 9.The voltage waveform of the current waveform of inductance L r and buffering capacitor C r as shown in figure 10 during resonance.
Mode?a(～Vc2＝on)：(～t1)
Vc1 conducting during stable state, DC power supply I
SAnd E
dLoad current I is provided
L, and i
Lr=0, U
Cr=E
d
Mode?b(V
c2＝on～V
c1＝off)：(t
1～t
2)
At t
1Constantly allow V
C2Conducting, then L
rOn be applied with E
d/ 2 voltages, L
rElectric current increasing obvious V
C2Conducting carry out with ZVS, ZCS mode.Work as i
Lr=I
R1(I
R1Be set point, I
R1＞I
L) time, turn-off V
C1
Mode?c(V
c1＝off～VD
s＝on)：(t
2～t
3)
At t
2Constantly turn-off V
C1, L then
r, C
rBetween produce resonance, capacitor C
rLast electric charge is through L
rWith load I
LDischarge, voltage U
CrDescend gradually.Because L
rOn voltage equal E
s/ 2, so V
C1Shutoff carry out in the ZVS mode.Work as U
Cr=0 o'clock, diode VD
sConducting.
Mode?d(VD
s＝on～VD
c2＝on)：(t
3～t
4)
Because VD
sConducting, L
rEnergy transfer to power supply E
dOn/2, i
LrReduce gradually, until i
Lr=0.
Mode?e(VD
c2＝on～VD
s＝off，V
s＝on)：(t
4～t
5)
Power supply E
d/ 2 through diode VD
C2To L
rThe savings electric energy.Because L
rOn be applied with E
d/ 2 voltages, direction are just opposite during with pattern b, so i
LrDirection is put upside down, and progressively increases.Allow V around here
C2Turn-off, obviously this action is carried out under the ZVS state.At t
5Constantly, i
LrEqual load I
L, diode VD
sTurn-off.
Mode?f(VD
s＝off，V
s＝on～V
s＝off)：(t
5～t
6)
In order to make complete the carrying out of resonance energy of back, must give switch V
sShort circuit with moment makes L
rContinue to apply E
d/ 2 voltages, i
LrContinue to increase.
Mode?g(V
s＝off～VD
c1＝on)：(t
6～t
7)
At t
6Constantly, i
LrEqual set point I
R2Turn-off V
s, C then
rAnd L
rBetween resonance takes place again.V
sConducting and turn-off when all voltage is zero between bus and carry out, so its switch motion belongs to ZVS.Because i
Lr＞I
L, i
LrBeginning is to C
rCharging is until U
Cr=E
d
Mode h (VD
C1=on～VD
C1=off, V
C1=on): (t
7～t
8) capacitor C
rStop charging, diode VD
C1Conducting, L
rMiddle excess energy is returned DC power supply E
d/ 2.Allow V this moment
C1Conducting, obviously V
C1Action carry out in the ZVS mode.L
rElectric current in the power supply regeneration processes, reducing gradually.
Mode?i(VD
c1＝off，V
c1＝on～VD
c2＝off)：(t
8～t
9)
Work as i
Lr＜I
LThe time, diode VD
C1Turn-off DC power supply I
SAnd E
dSimultaneously to load I
LElectric current is provided.Until i
Lr=0 o'clock, load current I then
LFully by E
dProvide.
Before address, the conducting of each power device is all borrowed when the last voltage of dc bus P, N is zero during the zero voltage switch circuit resonance and is carried out on current transformer and the inverter brachium pontis, its conducting is the no-voltage conducting.On the other hand, all be parallel with buffer capacitor on each power device, it all must be the no-voltage mode that its shutoff is at any time carried out.Therefore, can be placed on the shutoff of these devices and whenever carry out.For three-phase PWM current transformer-inverter, at each carrier cycle, all necessary turn-on and turn-off respectively of every phase brachium pontis power device up and down once.
The present invention is to use sawtooth waveforms to generate the turn-on and turn-off that pwm pulse is controlled each power device as carrier wave and modulating wave, shown in Figure 11 (a), though the intersection point of three-phase modulations ripple and sawtooth waveforms hypotenuse is in the different moment, with the edge, back always intersect behind the sawtooth waveforms along (claiming that the back is along modulation) on the time point.Because the shutoff of power device can be carried out at any time, be placed on the back of sawtooth waveforms along constantly carrying out thereby can allow opening of three phase power device concentrate.Like this, as shown in FIG., sawtooth waveforms just has the identical cycle, thereby can trigger V with the fixed cycle
C1, V
C2, make it to take place resonance, made things convenient for the design of control circuit.Dash area is represented during the zero voltage switch circuit resonance among the figure, during this period, and each relevant power device triggering and conducting.Because sawtooth waveforms has the fixed cycle, resonance for once in each cycle, i.e. shade (or voltage is zero) for once, thus reduced the number of times of no-voltage output between dc bus P, N, correspondingly also improved the voltage utilization of frequency converter.
To the PWM frequency converter, traditionally just like giving a definition, promptly when modulation wave signal during greater than carrier signal, the last brachium pontis power device conducting of trigger converter or inverter, meanwhile block the corresponding break-over of device of brachium pontis down, upper and lower bridge arm trigger impulse sequential is shown in Figure 11 (a).
Work as i
u＞0 o'clock, U
+=1 makes i
uFrom the P utmost point through V
7Flow into the winding L of load 2
u, shown in Figure 12 (a) solid line, U
-=0 makes V
10Turn-off.U
+After trigger finishing, i.e. U
+=0, U
-=1 o'clock, V
7Turn-off V
10Though triggering and conducting, because L
uIn current i
uCan not swerve i
uTo change its course by the N utmost point through VD
10Flow to L
u, in other words, this moment V
10And VD
7All do not play a role.
Work as i
u＜0 o'clock, U
-=1 makes i
uWinding L from load 2
uIn flow out, through V
10To the N utmost point, shown in Figure 12 (b) solid line, U
+=0 makes V
7Turn-off.U
-After trigger finishing, i.e. U
-=0, U
+=1 o'clock, V
10Turn-off V
7Conducting heavily again, as a same reason, because L
uIn current i
uCan not swerve i
uTo change its course from L
uThrough VD
7Enter the P utmost point, at this moment V
7And VD
10All do not play a role yet.
As seen from the above analysis, work as i
u＞0 o'clock, U
+Make V
7Just behind Figure 11 (a) sawtooth waveforms, begin conducting, i.e. just in time conducting during the zero voltage switch circuit resonance along the place; And V
10Conducting at any time is because there is VD
10The bypass effect, make V
10Conducting have no the relation.And work as i
u＜0 o'clock, V
10And VD
7Conducting most important.If still the control strategy by Figure 11 (a) makes V
10Triggering and conducting, then U
-Pulse front edge do not locate on the back edge (shadow region) of sawtooth waveforms, promptly can't make V
10Open-minded during resonance.For this reason, must be with sawtooth wave line of propagation tune, shown in Figure 11 (b), V like this
10The rising edge (shade) that just can adjust at sawtooth waveforms of opening locate, promptly take place during the resonance.
To sum up, carrier wave of the present invention must be direction relatively/opposing staggered repeatedly sawtooth carrier wave, as shown in figure 13, be followed successively by i among the figure from top to bottom
u, i
v, i
wModulation schematic diagram with the sawtooth carrier wave.Work as current i
u＞0 o'clock, with the sawtooth carrier wave of positive slope; Work as current i
u＜0 o'clock, with the sawtooth carrier wave of negative slope.
Therefore in double-PWM frequency converter, current transformer has 6 mutually with inverter, 6 row sawtooth carrier waves is arranged, and sees Figure 13, and every row sawtooth carrier wave switches according to the variation of current polarity separately, direction relatively/opposingly arranging alternately repeatedly.This 6 row sawtooth carrier wave is accomplished strict synchronism by programming, 6 groups of shadow regions are overlapped, shown in vertical dotted line among Figure 13.Like this, all drop on during the resonance of main circuit in the shadow region, for the zero voltage switch action.These actions are to trigger driving by PWM generative circuit 6 or the pwm pulse that generated by microprocessor 3, because of the circuit of 6 phases is identical with process, below illustrate to be example mutually with U only.
Two embodiment of the present invention adopt the generation method of two kinds of pwm pulses, and the pwm pulse of embodiment one is generated by hardware circuit, are provided with pwm pulse generative circuit 6; The pwm pulse of embodiment two is generated by microprocessor 3 softwares, is provided with current polarity judging circuit 5.By hardware pwm pulse generative circuit 6 or pwm pulse signal each device for power switching on semiconductor power switch device drive circuit 7 rear drive main circuits of generating by microprocessor 3 softwares.
Referring to Fig. 3 and Fig. 5, the pwm pulse generative circuit 6 (U phase) that embodiment one adopts is by voltage comparator U
1, U
2, inverter U
3, driver U
4, U
5And the circuit that current zero crossing detector constitutes is formed.The sawtooth waveforms (U phase) of input divides two-way, one road direct sending voltage comparator U
1End of oppisite phase, another road is through resistance R
1After deliver to inverter U
3End of oppisite phase, U
3In-phase end ground connection, U
3End of oppisite phase through resistance R
2Be connected to U
3Output, this output is connected to voltage comparator U
2End of oppisite phase; The modulating wave e of input
uAlso divide two-way, the one tunnel send voltage comparator U
1In-phase end, voltage comparator U is sent on another road
2In-phase end; U
1Output be connected to driver U
4Input, U
2Output be connected to driver U
5Input; U
4Output termination one OR-gate U
6An input, U
5Output termination U
6Another input; U
6Output divide two-way, the one road drives the semiconductor power switch device V of the last brachium pontis of inverter
7IGBT, another Lu Jingyi inverter U
7Each of rear drive inverter be the semiconductor power device V of brachium pontis down
10IGBT; Signal by current zero crossing detector output is connected to driver U
4Key player on a team go side and driver U
5Negative gating end.As shown in Figure 5, U phase positive slope sawtooth waveforms is through inverter U
3Generate the negative slope sawtooth waveforms after the paraphase, positive negative slope sawtooth waveforms enters comparator U simultaneously
1, comparator U
2End of oppisite phase "-".U phase modulation wave signal voltage e
uEnter comparator U simultaneously
1, U
2Positive terminal "+", U
1Output termination buffer U
4Input, U
2Output termination buffer U
5Input.On the other hand, by the detected U phase current i of current transformer (being the part commonly used of PWM frequency converter, not shown in the figures)
uAfter handling, the zero passage testing circuit forms the polarity discriminating level.At phase current i
u, adopt positive slope sawtooth waveforms and modulating wave e at＞0 o'clock
uRelatively produce pwm pulse, gating U
4, the pwm pulse of promptly selecting the positive slope sawtooth waveforms to modulate; At phase current i
u＜0 o'clock, adopt through inverter U
3Negative slope sawtooth waveforms that generates after the paraphase and modulating wave e
uRelatively produce pwm pulse, gating U
5, the pwm pulse of promptly selecting the negative slope sawtooth waveforms to modulate.The two-way pulse is finally all passed through or door U
6Send, be used to trigger power device V
7And V
10
The pwm pulse that is generated by hardware circuit of two-phase (V, W phase) is identical with the U facies principle in addition.
The pwm pulse of embodiment two is generated by microprocessor 3 softwares, by a polarity transformation identification signal that provides phase current i, adopts different modulating waves according to the polarity of phase current i.Referring to Fig. 4 and Fig. 6, current polarity judging circuit 5 is by inverse gate U
1, or the door U
2, three input NOR gate U
3, delay circuit, Dead Time form circuit, resistance R
3, photoelectrical coupler U
4, resistance R
4, Schmidt's reshaper U
5, inverse gate U
6, with the door U
7, U
8, or the door U
9, d type flip flop U
10Constitute, drive semiconductor power switch device V
C1The control signal of IGBT is through inverse gate U
1After be connected to or the door U
2Input drives semiconductor power switch device V
C2The control signal of IGBT directly is connected to or door U
2Other end input, or door U
2Output is connected to three input NOR gate U
3An input; Pwm control signal is delivered to Dead Time and is formed circuit, and Dead Time forms two signals of circuit output, and one is delivered to three input NOR gate U
3An input, remove to drive the semiconductor power device V of the last brachium pontis of inverter simultaneously
7IGBT, it two delivers to three input NOR gate U
3Another input, remove to drive the semiconductor power device V of the following brachium pontis of inverter simultaneously
10IGBT; Three input NOR gate U
3Output be connected to a delay circuit, the output of delay circuit divides two-way, the one tunnel connect with the door U
7An input, another road connect with the door U
8An input; The voltage U that detects by main circuit inverter bridge output U and direct current negative busbar N
UN, its U end is through resistance R
3After meet photoelectrical coupler U
4Diode anode, this diode cathode of N termination; Photoelectrical coupler U
4Transistor collector meet control power supply V
Cc, its emitter connects the ground end of controlling power supply through resistance R 4, and this emitter is through Schmidt's reshaper U
5Two-way is divided in the back, and one connects and door U
7Another input, its two, through inverse gate U
6Send after anti-phase and door U
8Another input; With door U
7Output connect or the door U
9An input, with door U
8Output connect or the door U
9Another input; Or door U
9Output meet d type flip flop U
10Clock end or remove the micro processor controls signal input part, d type flip flop U
10Q be connected to D end, the Q end removes the micro processor controls end.
Referring to the U phase pwm pulse oscillogram that realizes with microprocessor 3 softwares shown in Figure 14, wherein singly increase the PWM modulation system continuously shown in Figure 14 (a), work as i
uMust adopt Figure 14 (a) sawtooth waveforms modulation at＞0 o'clock, the pwm pulse that is generated by its is shown in Figure 14 (c), (d).Work as i
u＜0 o'clock, must adopt the sawtooth waveforms modulation shown in Figure 14 (b), the pwm pulse that is generated by its is shown in Figure 14 (e), (f).But microprocessor 3 does not possess the PWM modulation function shown in Figure 14 (b).The present invention adopts e
u'=1-e
uReplace e
u, and give Figure 14 (c) the opposite effectively definition of polarity, and then can abandon Figure 14 (b), continue to continue to use the positive slope sawtooth waveforms shown in Figure 14 (a) and realize i
u＜0 o'clock PWM modulation, as Figure 14 (g), by the pwm pulse of its generation such as Figure 14 (h), (i), it and Figure 14 (e), (f) are just the same, thereby make i
u＜0 o'clock V
10Open also can drop on the positive slope sawtooth waveforms vertical back along place's (during resonance).This method only need adopt the positive slope sawtooth waveforms, just can satisfy i simultaneously
u＞0 and i
u＜0 modulation.
In frequency converter, in order to prevent that the upper and lower bridge arm power device is (as the V of Figure 12 (a)
7, V
10) straight-through, generally all Dead Time T must be set
d(Dead Time) works as i
u＞0 o'clock, shown in Figure 12 (a), at T
dDuring this time, V
7, V
10Not conductings, i
uThrough VD
10Flow into L
u, U point current potential U
uBe almost equal to zero; Otherwise, work as i
u＜0 o'clock, shown in Figure 12 (b), i
uFrom L
uIn flow out, through VD
7Arrive the P utmost point, U point current potential U
uBe close to the P level point.But above situation is not suitable for during the zero voltage switch circuit resonance, because voltage always zero, i.e. U between resonance period P, N
uAlso be zero, so the present invention reach with current polarity judging circuit 5 shown in Figure 6 and prevent that the upper and lower bridge arm power device from leading directly to.
When being carrier wave with the positive slope sawtooth waveforms, simultaneously referring to Fig. 6, Figure 15, the empty frame among Fig. 6 is that the expression Dead Time forms circuit.Figure 15 (a) is positive slope sawtooth waveforms PWM modulation, signal wave e among Figure 15
uRelatively generate pwm pulse with the carrier wave sawtooth waveforms, shown in Figure 15 (g), after the Dead Time of Fig. 6 forms processing of circuit, generate and trigger V
7, V
10Voltage such as Figure 15 (h), (i).Know by Figure 10, resonance be by V
C1, V
C2The triggering signal decision at t
1Constantly, V
C2There is a positive transition to trigger, as Figure 15 (c); t
7V afterwards
C1Also there is a positive transition to trigger, as Figure 15 (b), through the U of Fig. 6
1Anti-phase back is as Figure 15 (e), at U
2After the logic OR, get Figure 15 (f) waveform.During the resonance, voltage U between P, N
PNBe zero, as Figure 15 (d).After this, at i
u＞0 o'clock, V
7Triggering and conducting make U
UN=E
d, see the U of Figure 15 (j) and Fig. 6
UNBecause optocoupler pipe U
4Delay effect, a point current potential U
aThan U
UNLag behind (general 2～3 μ S), as Figure 15 (k).Work as i
u＜0 o'clock, V
7Triggering seek the logical U that also makes
UN=E
d, but know by Figure 12 (b), this moment U
UNT of trailing edge delay
dJust drop to zero after time, compare Figure 15 (n), (j), the U of this moment
aAs Figure 15 (o).If with U
cSuitable time-delay generates U
d, as Figure 15 (m), then U
d, U
aWith after obtain U
R, as Figure 15 (p), it is by U among Fig. 6
7R end output.
Current polarity judging circuit 5 can detect the following electric current of positive slope sawtooth waveforms PWM modulation from i
u＞0 to i
uThe identification signal U that＜0 o'clock the polarity first time (from just to negative) changes
R, and command control system transfers negative slope sawtooth waveforms PWM modulation to by positive slope sawtooth waveforms PWM modulation, shown in Figure 16 (a).
Control mechanism shown in Figure 16 is identical with Figure 15, and relatively Figure 16 (g) and Figure 15 (g) as seen distinguish the polarity reversed in order that is the PWM modulating pulse, by the V of its generation
7, V
10Trigger impulse such as Figure 16 (h), (i).Work as i
u＞0 o'clock, U
UN, U
aShown in Figure 16 (j), (k); i
u＜0 o'clock, U
UN, U
aShown in Figure 16 (o), (p).U
aAfter the paraphase U
b, i
a＞0 and i
a＜0 o'clock U
bAs Figure 16 (l), (q), obviously, the pulse trailing edge of Figure 16 (1) is than Figure 16 (q) hysteresis T
dTime.U by Fig. 6
3Detected T
dTime signal U
CAs Figure 16 (m), suitable time-delay U
C, get U
d, as Figure 16 (n).U
dU with Figure 16 (l)
bWith, can get the following electric current of negative slope sawtooth waveforms PWM modulation from i
u＜0 to i
uThe identification signal U that＞0 o'clock the polarity first time (from just bearing) changes
s, as Figure 16 (r), it is by by U among Fig. 6
8S end output, and command control system transfers positive slope sawtooth waveforms PWM modulation to by negative slope sawtooth waveforms PWM modulation, promptly returns the modulation of Figure 15 (a).
Claims (3)
1, a kind of Zero-voltage switch double-PWM frequency converter, have input side AC-DC current transformer, outlet side DC-AC inverter, at the major loop that intermediate link constituted between input side and the outlet side and the electric current and voltage detection between microprocessor, microprocessor and the major loop and treatment circuit, semiconductor power switch device drive circuit, the intermediate link that it is characterized in that major loop is a zero voltage switch circuit, and it is by semiconductor power switch device V
C1, V
C2, diode VD
C1, VD
C2, capacitor C
D1, C
D2And inductance L
rForm semiconductor power switch device V
C1Emitter meets the dc bus P utmost point and diode VD
C1Anode, semiconductor power switch device V
C1Collector electrode connects capacitor C
D1With diode VD
C1Negative electrode, capacitor C
D1Another termination capacitor C
D2And inductance L
r, capacitor C
D2Another termination dc bus N utmost point; Semiconductor power switch device V
C2Collector electrode meets the dc bus P utmost point and diode VD
C2Negative electrode, semiconductor power switch device V
C2Emitter meets diode VD
C2Anode and inductance L
rThe other end; Buffer capacitor in parallel on each semiconductor power device of current transformer and inverter; Each semiconductor power switch device opens that all to drop on direct voltage on the major loop be to take place in zero the interval on the brachium pontis.
2, Zero-voltage switch double-PWM frequency converter according to claim 1 is characterized in that, pwm pulse is by voltage comparator U
1, U
2, inverter U
3, driver U
4, U
5And the circuit that current zero crossing detector constitutes generates; The sawtooth wavelength-division two-way of input, one road direct sending voltage comparator U
1End of oppisite phase, another road is through resistance R
1After deliver to inverter U
3End of oppisite phase, U
3In-phase end ground connection, U
3End of oppisite phase through resistance R
2Be connected to U
3Output, this output is connected to voltage comparator U
2End of oppisite phase; The modulating wave e of input also divides two-way, and one the tunnel send voltage comparator U
1In-phase end, voltage comparator U is sent on another road
2In-phase end; U
1Output be connected to driver U
4Input, U
2Output be connected to driver U
5Input; U
4Output termination one OR-gate U
6An input, U
5Output termination U
6Another input; U
6Output divide two-way, the one road drives the semiconductor power switch device IGBT of the last brachium pontis of inverter, another Lu Jingyi inverter U
7The semiconductor power device IGBT of the following brachium pontis of rear drive inverter; Signal by current zero crossing detector output is connected to driver U
4Key player on a team go side and driver U
5Negative gating end; In phase current i＞0 o'clock, adopt positive slope sawtooth waveforms and modulating wave e relatively to produce pwm pulse; In phase current i＜0 o'clock, adopt through inverter U
3The negative slope sawtooth waveforms and the modulating wave e that generate after the paraphase relatively produce pwm pulse.
3, Zero-voltage switch double-PWM frequency converter according to claim 1, it is characterized in that pwm pulse is generated by microprocessor, provide the polarity transformation identification signal of phase current i by a current polarity judging circuit, in phase current i＞0 o'clock, adopt the modulation of positive slope sawtooth waveforms; In phase current i＜0 o'clock, still adopt the modulation of positive slope sawtooth waveforms, use e '=1-e replacement e modulating wave, the validity of production burst is opposite with the former; The current polarity judging circuit is by inverse gate U
1, or the door U
2, three input NOR gate U
3, delay circuit, Dead Time form circuit, resistance R
3, photoelectrical coupler U
4, resistance R
4, Schmidt's reshaper U
5, inverse gate U
6, with the door U
7, U
8, or the door U
9, d type flip flop U
10Constitute, drive semiconductor power switch device V
C1The control signal of IGBT is through inverse gate U
1After be connected to or the door U
2Input drives semiconductor power switch device V
C2The control signal of IGBT directly is connected to or door U
2Other end input, or door U
2Output is connected to three input NOR gate U
3An input; Pwm control signal is delivered to Dead Time and is formed circuit, and Dead Time forms two signals of circuit output, and one is delivered to three input NOR gate U
3An input, remove to drive the semiconductor power device IGBT of brachium pontis on each of inverter simultaneously, it two delivers to three input NOR gate U
3Another input, each that removes to drive inverter simultaneously be the semiconductor power device IGBT of brachium pontis down; Three input NOR gate U
3Output be connected to delay circuit, the output of delay circuit divides two-way, the one tunnel connect with the door U
7An input, another road connect with the door U
8An input; The voltage U that detects by main circuit inverter bridge output U and direct current negative busbar N
UN, its U end is through resistance R
3After meet photoelectrical coupler U
4Diode anode, this diode cathode of N termination; Photoelectrical coupler U
4Transistor collector meet control power supply V
Cc, its emitter connects the ground end of controlling power supply through resistance R 4, and this emitter is through Schmidt's reshaper U
5Two-way is divided in the back, and one connects and door U
7Another input, it is two through inverse gate U
6Send after anti-phase and door U
8Another input; With door U
7Output connect or the door U
9An input, with door U
8Output connect or the door U
9Another input; Or door U
9Output meet d type flip flop U
10Clock end or remove the micro processor controls signal input part, d type flip flop U
10Q be connected to D end, the Q end removes the micro processor controls end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001195263A CN1134100C (en) | 2000-07-28 | 2000-07-28 | Zero-voltage switch double-PWM frequency converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001195263A CN1134100C (en) | 2000-07-28 | 2000-07-28 | Zero-voltage switch double-PWM frequency converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1336716A true CN1336716A (en) | 2002-02-20 |
| CN1134100C CN1134100C (en) | 2004-01-07 |
Family
ID=4587770
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001195263A Expired - Fee Related CN1134100C (en) | 2000-07-28 | 2000-07-28 | Zero-voltage switch double-PWM frequency converter |
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| Country | Link |
|---|---|
| CN (1) | CN1134100C (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425798B (en) * | 2007-10-30 | 2011-09-07 | 比亚迪股份有限公司 | Dynamic current equalizing method and device for parallel IGBT |
| CN107546999A (en) * | 2017-08-22 | 2018-01-05 | 浙江大学 | A kind of band active power decouples single-phase ZVT inverter circuit and its modulator approach |
| CN107872185A (en) * | 2016-09-27 | 2018-04-03 | 德昌电机(深圳)有限公司 | Load drive device, electric machine assembly and motor driver |
| CN108233903A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of airborne high-voltage frequency converter IGBT anti-interference driving circuits |
| CN108390664A (en) * | 2018-01-30 | 2018-08-10 | 昆明理工大学 | A method of high-accuracy voltage is generated based on dual pulse width modulation |
| CN109980949A (en) * | 2019-03-20 | 2019-07-05 | 浙江大学 | A kind of Research on Unified Power Quality Conditioner based on soft switch circuit |
-
2000
- 2000-07-28 CN CNB001195263A patent/CN1134100C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101425798B (en) * | 2007-10-30 | 2011-09-07 | 比亚迪股份有限公司 | Dynamic current equalizing method and device for parallel IGBT |
| CN107872185A (en) * | 2016-09-27 | 2018-04-03 | 德昌电机(深圳)有限公司 | Load drive device, electric machine assembly and motor driver |
| CN108233903A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of airborne high-voltage frequency converter IGBT anti-interference driving circuits |
| CN107546999A (en) * | 2017-08-22 | 2018-01-05 | 浙江大学 | A kind of band active power decouples single-phase ZVT inverter circuit and its modulator approach |
| CN108390664A (en) * | 2018-01-30 | 2018-08-10 | 昆明理工大学 | A method of high-accuracy voltage is generated based on dual pulse width modulation |
| CN109980949A (en) * | 2019-03-20 | 2019-07-05 | 浙江大学 | A kind of Research on Unified Power Quality Conditioner based on soft switch circuit |
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| Publication number | Publication date |
|---|---|
| CN1134100C (en) | 2004-01-07 |
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Owner name: SHANGHAI XINYUAN ELECTRIC FREQUENCY CONVERTER CO., Free format text: FORMER NAME OR ADDRESS: SHANGHAI XINYUAN VARIABLE FREQUENCY ELECTRICAL APPLIANCE CO., LTD. |
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| CP03 | Change of name, title or address |
Address after: 200072, science building 2F, 149 extension Road, Shanghai Patentee after: Xinyuan Variable Frequency Electric Appliance Co., Ltd., Shanghai Address before: 200072, science building 2F, 149 extension Road, Shanghai Patentee before: Shanghai Xinyuan Variable Frequency Electrical Appliance Co., Ltd. |
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Granted publication date: 20040107 Termination date: 20120728 |