CN1334935A - Scalfable charge pump for use with low voltage power supply - Google Patents
Scalfable charge pump for use with low voltage power supply Download PDFInfo
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- CN1334935A CN1334935A CN99813730A CN99813730A CN1334935A CN 1334935 A CN1334935 A CN 1334935A CN 99813730 A CN99813730 A CN 99813730A CN 99813730 A CN99813730 A CN 99813730A CN 1334935 A CN1334935 A CN 1334935A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
Abstract
A charge pump (145) having predetermined number of serially connected pump stages (321-324) receiving clock signals (CLK1-4) having high logic levels of different amplitudes.
Description
The technology of the present invention field
The present invention relates generally to system, relates more specifically to use the ratio of low-tension supply to regulate charge pump.
Background technology of the present invention
The trend that personal computer and other electronic equipment reduce power requirement has appearred.For reducing power consumption, a large amount of integrated circuit that are used for personal computer are redesigned and are able to the operation of low-tension supply level.For example, many elements that are designed to 5 volts of voltage power supplies have in the past redesigned with 3.3 volts of voltage power supplies.Some new products and many products under development even have more low-voltage may be lower than 2 volts in many cases.
Although supply voltage is lowered, high voltage may continue on for some computer system parts.For example flash electric erasable program read-only memory (EEPROM) may be used in some computer systems the basic input/input system (BIOS) of storage or as random access memory stores equipment.Voltage that the voltage that the general use of flash memory device directly provides than low-tension supply is higher and power programming or the obliterated data of Geng Gao.
For example thereby negative gate erase technique may be used for some flash-EEPROM arrays and reduces power with the magnitude of current that reduces during the erase operation.Negative gate erase technique uses big negative voltage (generally negative nine or ten volts) and use Vcc on source terminal on the memory device gate terminal.
For the negative-grid erase operation being provided the negative voltage that needs, can use negative charge pump.In the people's such as Pantelakis that transfer the assignee of the present invention United States Patent (USP) 5532915, a kind of negative charge pump has been described.
, people's such as Pantelakis charge pump has shortcoming.Be lower than on the supply voltage of preset level, when the P of Pantelakis transistor npn npn (being also referred to as the P raceway groove) was connected, they may be operated in transistor and experience in the scope that measurable threshold voltage descends." connecting fully " causes not having on them the effective gate pressure limiting to be fallen if the P-transistor npn npn of Pantelakis does not have when they are worked, and may needing in addition, level realizes identical pumping output voltage.In addition, the electric current that the Pantelakis charge pump produces will be reduced.
If supply voltage drops to the threshold voltage that is lower than one or several p channel transistor, when needs even can not connect one or several transistor.In the case, bear pumping voltage and can not be delivered to subordinate from one-level.On the other hand, be lower than given supply voltage, the negative charge pump of Pantelakis may not worked.
The present invention's general introduction
The charge pump that uses low-tension supply has been described.This charge pump design is on the integrated device electronics with supply voltage work.Charge pump comprises the predetermined quantity pump stage that is connected in series, and connects one of these levels at least to receive the first pumping clock signal.Output node is connected in series on series connection pump stage one end of predetermined quantity the pumping output voltage is provided.
According to following drawings and detailed description, other features and advantages of the present invention will be clearer.
Brief description
Do not limit the present invention with way of example explanation the present invention in the accompanying drawings, identical in the drawings reference number is represented components identical, among the figure:
Fig. 1 is the block scheme that is advantageously used in a computer system among the embodiment.
Fig. 2 is the block scheme of more detailed expression mass-memory unit among Fig. 1.
Negative charge pump among the more detailed expression Fig. 1 and 2 of Fig. 3.
Fig. 4 is the circuit diagram of an embodiment of expression positive charge pump.
Fig. 5 is the calcspar of an embodiment of the clock driver of the expression pumping clock signal that produces Fig. 3.
Fig. 6 represents the circuit of an embodiment of control chart 3 negative charge pump output voltages.
Fig. 7 is the process flow diagram that expression provides an embodiment method of pumping voltage.
Describe in detail
Description provides the ratio of utilizing low-tension supply to regulate the method and apparatus of charge pump.Although with reference to describing the following example as the mass-memory unit flash memory, alternate embodiment also can be applicable to other type circuit, comprise the nonvolatile memory that is higher or lower than other type that the voltage that can use supply voltage is benefited from having, and/or as other type flash memory of other purpose.
Fig. 1 represents to be advantageously used in the block scheme of the system 100 of an embodiment.System 100 is personal computer systems, but also can be the system of other type, for example the server of other embodiment, digital camera or cellular telephone etc.
A ROM (read-only memory) 120 also is connected to system bus 110 and is processor 105 storage static informations, a supply voltage 122 provides voltage vcc for system on bus 123, a mass-memory unit 125, input equipment 130 is for example monitor and/or printer of keyboard or cursor control device and output device 135 for example.Computer system 100 also can comprise other peripheral component 140, for example Memory Controller and/or bus bridge device.
The system power supply voltage vcc of an embodiment be 1.8 volts+/-150 millivolts (mV) and provide by low battery power.For alternate embodiment, supply voltage can be higher or lower and can be provided by other type of power voltage.
For an embodiment, mass-memory unit 125 comprises flash memory, is also referred to as the flash electricity and wipes program read-only memory (EEPROM).It is identical that mass-memory unit 125 plays conventional hard disk drive in the embodiment shown in fig. 1.The flash-EEPROM mass-memory unit 125 of an embodiment comprises one or several positive charge pump 142, a clock driver 144,147, one mu balanced circuits 150 of 145, one voltage controlled oscillators of negative charge pump (VCO) and an array of flash memory cells 155.For other embodiment, mass-memory unit 125 can design with different modes.Below with reference to Fig. 3 to 6 charge pump 142 and 145 are described in more detail, clock driver 144, voltage controlled oscillator 147 and mu balanced circuit 150.
Be to be understood that not to be also can be used in the alternate embodiment with mode designed system shown in Figure 1.
Fig. 2 represents more detailed mass-memory unit 125.Particularly, Fig. 2 represents for example unit 202 programming and wipe the circuit of embodiment of flash memory array Unit 155.For the purpose of illustration, a memory cell 202 in Fig. 2, only having represented memory array 155.
For this embodiment, negative scrub techniques is used to wipe for example memory cell 202 of memory cell.Negative scrub techniques relates to the big negative voltage of application on the memory cell gate terminal of wiping, and for example-10.5 volt, provides Vcc voltage simultaneously on source terminal.It is enough low so that to be wiped free of memory cell source-substrate junction diode not breakdown to be applied to Vcc voltage on the source terminal.In this way, in erase process, only flow through relatively little source current.Therefore, even identical with positive scrub techniques difference in the voltage difference that is wiped free of between device gate and the source electrode, negative scrub techniques needs littler electric current.
The further details of flash-EEPROM mass-memory unit 125, for embodiment, positive charge pump 142 comprises 8 volts of charge pumps 205 and 10.5 volts of charge pumps 210.8 volts of charge pumps and 10.5 volts of charge pumps can dispose by any way.For an embodiment, 8 volts of charge pumps and 10.5 volts of charge pumps with below similar in greater detail the mode of negative charge pump 145 dispose.Be provided for two charge pump circuits 205 and 210 that are included in the positive charge pump 142 from the Vcc of bus 110 (Fig. 1).
Programmed in one or several unit of flash memory array 155 during operation, voltage from charge pump 205 is provided for one group of bit line switch and demoder 215, and this demoder provides voltage to the drain terminal of the flashing storage unit in the flash memory array 155.In addition, be provided for one group of word line switch and demoder 220, for the grid of memory cell provides voltage from the voltage of charge pump 210.One or several unit of erase flash memory array 155 during operation, voltage from negative charge pump 145 is provided for word line switch and demoder 220, and is provided for one group of source electrode switch and demoder 225 from approximate 5 volts of voltages of one of positive charge pump 142.Can provide potential difference to source electrode switch and demoder for an alternative embodiment.The memory cell source electrode that 225 pairs of source electrode switch and demoders are wiped provides voltage.This switch and demoder 215,220 and 225 are well known to a person skilled in the art that mode work selects accessed particular memory cell and provide suitable voltage for the storer of carrying out accessing operation.
Every group of switch and demoder 215,220 and 225 can provide appropriate voltage for wiping with programming operation by the signal controlling from control circuit 230.For an embodiment, control circuit is the processor that a design provides the control of memory array 155 all operations, these operations comprise read, programming and erase operation.Exercise question at M Fandrich has been described the use of this control circuit for " method and apparatus of executable operations in the flash memory array " in the laid-open U.S. Patents 5509134 on April 16th, 1996, and transfer trustee of the present invention.For the embodiment of another mode, can utilize the external control source for example microprocessor control function is provided by different way.
For an embodiment, wipe for finishing in the flash memory array 155 the negative of one or several memory cell, offer the grid of the particular memory cell that will wipe by word line switch and demoder 220 from the accurate negative voltage of negative charge pump 145.
Fig. 3 has represented the negative charge pump 145 of Fig. 1 and 2 in more detail.The low negative voltage (that is the big negative voltage of amplitude) that 145 designs of negative charge pump that Fig. 3 represents can be used to provide a large amount of different negative voltage levels to comprise and are used to wipe the flash-EEPROM memory cell with negative scrub techniques.
The first group of input clock signal that is illustrated as clock 1 and clock 3 from source electrode is provided for charge pump 145 by capacitor 311-314.The second group of input clock signal that is illustrated as clock 2 and clock 4 from source electrode is provided by capacitor 321-324.
The charge pump 145 of embodiment comprises p slot field-effect transistor (FET) 301-304 and 310 that is connected in series.Transistor 301 have the coupling ground connection a terminal and transistor 310 has the terminal of the output terminal Vout of being coupled to.This equipment 310 is called output stage equipment at this.Threshold voltage for embodiment p channel transistor 301-304 and 310 is similar to 1.5 volts, but can be higher or lower for another mode embodiment.
Except the transistor 301-304 and 310 of series coupled, charge pump 145 every grade of 1-4 also comprise bootstrapping p channel transistor 331-334 respectively.Bootstrap transistor 331-334 is used for the gate terminal precharge to respective stages series coupled p channel device.Therefore, the first order of charge pump 145 (level 1) for example comprises transistor arrangement 301, bootstrap transistor equipment 331 and capacitor 311 and 321.
For embodiment, transistor 301 and 302 substrate are coupled to Vcc, and the substrate of transistor 303 and 304 is coupled to Vss.Transistor 301 and 302 substrate are coupled to that Vcc prevents may be in locking and/or other quality problems that the 145 initial clock period of charge pump are occurred.If the substrate of transistor 301 and 302 is coupled to Vss, the initial clock period of charge pump 145 is forward bias transistor 301 and 302 knot mistakenly.Transistor 303 and 304 further leaves the Vss power supply and therefore can make their substrate be coupled to Vss and have the more low-risk that this problem occurs.The transistor 301-304 of charge pump 145,310 and 331-334 can be metal-oxide semiconductor (MOS) (MOS) transistor of an embodiment, can use the transistor of other type to another mode embodiment.
Two clock signals shown in Figure 3, clock 2 and clock 4 provide high value Vcc and low value ground connection.The amplitude of these clock signals (between high value of clock signal and the low value poor) is Vcc., clock 1 and clock 3 signals provide 3.1 volts high value and ground connection low value.Therefore, clock 1 and clock 3 signals have 3.1 volts amplitude.Clock signal 1 and 3 is called the pumping clock signal at this, because their amplitude is got ratio such as Vcc height by pumping.Be described in greater detail below the mode of clocking 2 and clock signal 4 and pumping clock signal 1 and clock signal 3.
Although Fig. 3 has represented the 1-4 level of charge pump 145 in detail,, use eight grades of-10.5 volts of voltages that are provided for the memory cell of erase flash memory array 155 for embodiment.All the other 5-8 levels are coupled in series between level 4 and the transistor arrangement 310 in the mode of similar 1-4 level.
For describing the work of charge pump circuit 145, single level will be described, the work of level 2.Along with the sequential chart of corresponding clock signal 1-4 shown in Figure 3, clock signal 1 and 4 is initially low.Because clock signal 4 is low, equipment 332 initial turn-on.When clock signal 2 when low, the negative voltage pulse that applies by capacitor 321 is charged to the negative voltage level of equipment 302 source terminals by the capacitor 312 on 332 pairs of equipment 302 gate terminals of equipment.When clock signal 4 when being high then, equipment 332 is closed, off device 302 grids and make capacitor 312 be charged as negative level.
When clock signal 3 then when low because the amplitude of pumping clock signal is 3.1 volts voltages and has been precharged as negative value because of capacitor 312 in this example, voltage is lower than its source terminal voltage significantly on the gate terminal of equipment 302.Therefore, equipment 302 is being imitated connection in the scope that thresholding pressure drop (Vt) falls without having all through the ages.Make and equal 0 across the pressure drop Vt of equipment 302 and mean that bigger electric current is transferred to subordinate quickly and provides more high-amplitude voltage in subordinate from capacitor 321.
Low clock 2 pulses on capacitor 321 begin capacitor 322 is charged towards negative Vcc value.When clock signal 3 raise, equipment 302 began to close.When clock signal 4 step-downs, capacitor 322 is charged near negative two times of Vcc.Equipment 332 becomes the grid discharge of equipment 302 and it is changed towards its drain voltage, so that equipment 302 is closed very soon.When clock signal 2 uprises, equipment 302 keeps closing and equipment 332 keeps connecting so as balanced on equipment 302 drain and gate terminals charge pumping.
Whole observation charge pump circuit 145, when equipment 301 responded the negative edge of pumping clock signals 1, capacitor 311 is equipment 331 ground connection of quilt by having cut out on its gate terminal.Therefore, because being forced to, the gate terminal of the amplitude equipment 301 of pumping clock signal 1 is lower than source terminal.Therefore equipment 301 be switched on so that in fact it is worked in less than the pressure drop Vt scope on equipment 301.
When connecting, equipment 301 with capacitor 321 and capacitor 312 very charging quickly to earth level (because equipment 332 also connection at this moment).Then, equipment 301 begins to close when clock signal 1 uprises.The decline of clock signal 2 makes capacitor 321 become negative Vcc and finishes closing of equipment 301 by 311 discharges of 331 pairs of capacitors of equipment.312 chargings are recharged the grid of equipment 302 up to the rising closing device 332 of clock signal 4 to capacitor in low-clock signal 2 continuation.As mentioned above, when pumping clock signal 3 step-downs, equipment 302 is switched on so that it does not experience the interior work of scope of Vt pressure drop actually.This is to be lower than the voltage of equipment 302 source terminals because the low pulse of pumping clock signal 3 becomes voltage (being precharged to negative value) on equipment 302 gate terminals.Connecting equipment 302 in this way is charged near the value of bearing two times of Vcc capacitor 322 flash.
Identical program continues by level 3 and 4 so that the voltage on charge pump 145 duration of work nodes 340 can reach negative four times of Vcc voltages.All the other grades 5-8 (not shown) is also continued identical process satisfy connection equipment 310 up to the electric charge (not shown) that is coupled to the last capacitor on equipment 310 source terminals.For embodiment, equipment 310 is switched on and is operated in the scope that presents pressure drop Vt, because bootstrap transistor (for example transistor 331-334) is not provided.Be that pressure drop Vt is 1.5 volts under 1.5 volts the situation at the threshold voltage of transistor 310.
Therefore, the charge pump circuit of Fig. 3 is designed to provide negative pumping output voltage, have for this voltage of embodiment and to be approximately equal to the amplitude that pump stage (N) quantity multiply by Vcc, the threshold voltage that deducts output stage equipment 310 is (both, to negative charge pump Vout=-(N*Vcc)-Vt).For eight grades of charge pumps charge pump 145 for example, therefore the voltage Vout of output node can reach the Vt that approximate negative octuple Vcc deducts equipment 340, or negative 13.2 volts (use 1.8+/-the worst case supply voltage of the Vcc of 1500mV 1.66 volts) deducts the Vt of equipment 310.If equipment 310 has 1.5 volts Vt.Charge pump 145 can provide the pumping output voltage V out near negative 11.7 volts.As term pumping voltage or pumping output voltage as used herein be meant for charge pump or the amplitude that for example increases or reduce for other voltage of circuit greater than the voltage of given input voltage.
Should be appreciated that for other embodiment charge pump can comprise than more or less level shown in Figure 3, thinks that identical or other purposes provides the charge pump that produces different negative pumping output voltages.In addition, although be to be understood that the pumping clock signal, clock 1 among Fig. 3 and clock 3 have 3.1 volts of amplitudes in the foregoing description, and for the embodiment of another mode, the amplitude of pumping clock signal also can be higher or lower.
As what those skilled in the art understood, utilize n raceway groove (being also referred to as the n type) transistor to substitute the p channel transistor of charge pump 145 and on series coupled transistor one end, receive positive input voltage but not the similar charge pump of ground connection also can be used to provide the positive charge pump 142 of Fig. 1 and 2 or be the positive charge pump of different purposes.
Fig. 4 has represented the example of this charge pump.The charge pump 400 of Fig. 4 is worked in the mode of the charge pump 145 of similar Fig. 3, and the polarity of signal and voltage is opposite.The positive charge pump that designs in a similar manner as the charge pump among Fig. 4 400 can provide the positive pumping voltage of the Vt that is approximately equal to [(1+N) * Vcc]-output stage equipment 405, and wherein N is the pump stage quantity that provides in positive charge pump.Therefore, comprise the positive pumping output voltage that 4 grades positive charge pump 400 can provide (5*1.65)-1.5=6.75 to lie prostrate under for 1.5 volts of situations at the threshold voltage that uses 1.65 volts worst cases and output stage equipment 405.
For example the positive charge pump of charge pump 400 can be used to provide the positive charge pump 142 of Fig. 1 and 2.In addition, this charge pump can be used for other embodiment positive flashing storage unit scrub techniques and/or be used for using other purposes of pumping voltage.
The pumping clock signal 1 that negative charge pump 145 is received and 3 and positive charge pump 400 the pumping clock signal 1P and the 3P regulation charge pump 145 and 400 that are received utilize low supply voltage proportionally to work.So that they have the amplitude bigger than low supply voltage, charge pump circuit 145 and 400 series coupled transistor can effectively be worked in the scope of pressure drop Vt not being connected across on the transistor by pumping clock signal 1,3,1P, 3P.In this way, the charge pump stage quantity that needn't increase low supply voltage realizes identical pumping output and supply voltage relation.
In addition, by utilizing the pumping clock, some threshold voltage of the charge pump transistor of some embodiment does not need to regulate to such an extent that adapt to than low supply voltage.Low transistor threshold voltage can cause occurring for example higher leakage current.
According to the charge pump of one or several embodiment even can utilize the supply voltage work that is lower than one or several transistor threshold voltage in the charge pump.For some embodiment, for realizing this task, clock signal 3 and 4 shown in Figure 3 also is the pumping clock signal.For this embodiment, can reduce the charge pump stage quantity that is used to provide given pumping voltage., pumping clock signal 2 and 4 may reduce the efficient of this charge pump circuit.For any given charge pump design, may weigh tradeoff space, efficient, threshold voltage and supply voltage.
In addition, for the negative charge pump 145 of Fig. 3 and 4 and positive charge pump 400 both, the output current on output node Vout is directly proportional with input clock frequency respectively.Because the series coupled transistor that the pumping clock of two charge pumps 145 and 400 regulation is every grade is in the scope work of not experiencing the pressure drop Vt that crosses over them, charge pump 145 and 400 capacitor can charge very fast.For some embodiment, having eliminated provides a large amount of extra overlapping and make the capacitor charging provide the time more to need between various clock signals.In this way, can utilize relative high frequency rate clock signal that big relatively output current is provided.
Fig. 5 has represented the clock driver 144 of Fig. 1 in more detail.Voltage controlled oscillator 147 and clock driver 144 co-ordinations produce the clock signal 1-4 shown in Fig. 3.For embodiment, voltage controlled oscillator 147 receive from the Vcc of bus 110 and in output clocking CLK.The CLK signal is provided for the phase generator 505 that is configured on the clock driver 144, and it produces four outs of phase, the PH1-PH4 of CLK signal in its output.
Each signal of PH1-PH4 has the Vcc amplitude at the output terminal of phase generator 505.PH2 and PH4 signal provide clock signal 2 and 4 respectively.PH1 and PH3 signal are provided for pump clock 515.Pump clock 515 receives 3.1 volts of voltage signals from positive charge pump 142 (Fig. 1 and 2) or other voltage increase circuit internal level.In this example, utilize 8 volts of charge pumps 205 that 3.1 volts of pump clock power supplys are provided,, can utilize any positive charge pump.3.1 volt is approximately equal to twice Vcc, thus wherein Vcc equal 1.8 volts+/-150mV 3.1 vor signals can be from the extraction of the first order of for example 8 volts of charge pumps 205.Pump clock 515 utilizes amplitude to 3.1 volt of 3.1 volts of power supply signal pumping PH1 and PH3 signal, provides clock signal 1 and 3 in its output.Clock signal 1 and 3 is provided for negative charge pump 145 in the top mode of describing with reference to Fig. 3.
Pumping clock signal 1P and the 3P of Fig. 4 can produce in the same manner.
With reference to Fig. 3, the pumping output voltage V out of charge pump 145 is owing to the charging and the discharge of capacitor in the circuit are fluctuateed on output node.For for example accurate negative voltage of flashing storage unit erase operation use is provided, voltage regulator circuit for example voltage regulator circuit 150 (Fig. 2) can use.
Fig. 6 at length represents the voltage regulator circuit 150 of an embodiment.Voltage regulator circuit 150 is coupled to the input of voltage controlled oscillator 147.Voltage controlled oscillator 147 is coupled to the input of clock driver 144, and this driver provides the clock signal 1-4 of control negative charge pump 145 work.
The work of voltage regulator circuit 150 control negative charge pumps 145 when voltage controlled oscillator 147 can provide clock signal by clock driver 144.In this way, negative charge pump 145 can be connected when the pumping output voltage V out amplitude in charge pump 145 output was lower than (that is, corrigendum) desirable output voltage, and/or closed when the Vout amplitude is higher than when desired (more negative).
At work, if the Vout level greater than (i.e. corrigendum) desired output-voltage levels (in embodiment illustrated in fig. 3 be-10.5 volts), then the input value on comparator circuit 605 plus ends is corrected than the level that comparator circuit 605 negative terminals provide.The initial conditions of comparator circuit 605 keeps voltage controlled oscillator 147 to connect and increase gradually the output of charge pump 145.
When the Vout level becomes less than (promptly more negative) desired level, then the input value on comparator circuit 605 plus ends is less than the positive level that provides on comparator circuit 605 negative terminals.Because the accumulation of the voltage on the output capacitance dissipates gradually, the initial conditions of comparator circuit 605 has been closed voltage controlled oscillator 147 and has been reduced negative output voltage Vout gradually.In this way, the last voltage level that produces of negative charge pump 145 outputs can be adjusted so that constant relatively Vout level to be provided.
The voltage regulator circuit that should be appreciated that the voltage regulator circuit of similar Fig. 6 also can be used for for example adjusting positive charge pump of Fig. 4 charge pump 400.The reference voltage value of sort circuit and/or resistance value (in the occasion of using resistance) can be selected different needs Vout value.
The voltage regulator circuit that also should be appreciated that other type also can be used for various embodiment.
The embodiment that pumping output voltage method is provided is described referring now to Fig. 7.705 pumping clock signals that the method comprising the steps of have the pumping clock signal of amplitude greater than supply voltage with generation.In step 710, the pumping clock signal is received on the charge pump terminal, provides the pumping output signal in step 715 in charge pump output, and wherein pumping output signal has the amplitude greater than supply voltage.
In above-mentioned instructions, the present invention has been described with reference to particular exemplary embodiment., be to be understood that and carry out various modifications, change to the present invention and do not break away from of the present invention wider spirit and scope as middle elaboration.Therefore, instructions and accompanying drawing are considered to explanation of the present invention and are unrestricted.
Claims (26)
1. a charge pump design is on the integrated device electronics with supply voltage work, and this charge pump comprises:
The pump stage of a predetermined quantity series coupled, at least one is coupled pump stage to receive the first pumping clock signal; With
An output node is coupled in series to an end of predetermined quantity pump stage, and this output node provides the pumping output voltage.
2. the charge pump of claim 1, wherein each of pump stage predetermined quantity further coupling have the second clock signal that amplitude equals supply voltage with reception.
3. the charge pump of claim 1, comprise that further an output stage is coupled between output node and the predetermined quantity pump stage, this output stage has first threshold voltage, and wherein the pumping output voltage amplitude is approximately equal to supply voltage and multiply by predetermined quantity and deduct first threshold voltage.
4. the charge pump of claim 1, further comprise the output stage that is coupled between output node and the predetermined quantity pump stage, this output stage has first threshold voltage, and wherein the pumping output voltage amplitude is approximately equal to the threshold voltage that [(level of 1+ predetermined quantity) * supply voltage] deducts output stage.
5. the charge pump of claim 1, wherein the end opposite of predetermined quantity pump stage is coupled to ground connection and the pumping output voltage is negative pumping output voltage.
6. the charge pump of claim 1, wherein the end opposite of predetermined quantity pump stage is coupled to supply voltage and the pumping output voltage is positive pumping output voltage.
7. the charge pump of claim 2, wherein each predetermined quantity pump stage comprises a transistor, has that gate coupled receives the first pumping clock signal by first capacitor and a terminal coupling receives the second clock signal by second capacitor.
8. the charge pump of claim 2, wherein each pump stage is coupled to receive one of a plurality of phase places of the first pumping clock signal and one of a plurality of phase places of second clock signal.
9. the charge pump of claim 1, further comprise the voltage regulator circuit that is coupled to output node, when dropping to when being lower than predetermined level this voltage regulator circuit, the pumping output voltage regulates the pumping output voltage by starting charge pump, and interruption charge pump work when the pumping output voltage is higher than predetermined level.
10. the nonvolatile memory of supply voltage operation, nonvolatile memory comprises:
A memory array; With
One first charge pump is coupled to memory array, and first charge pump comprises:
The pump stage of a predetermined quantity series coupled, at least one pump stage be coupled with receive the first pumping clock signal and
An output node is coupled in series to an end of predetermined quantity pump stage, and output node provides the pumping output voltage.
11. the nonvolatile memory of claim 10 comprises that further a clock driver is coupled the clock pumping voltage that is higher than supply voltage with the reception amplitude, this clock driver is coupled provides the first pumping clock signal at least one pump stage.
12. the nonvolatile memory of claim 11 comprises that further second charge pump is coupled to clock driver, second charge pump provides pump clock voltage to clock driver.
13. the nonvolatile memory of claim 10, comprise that further a voltage regulator circuit is coupled to first charge pump, regulate the pumping output voltage when the pumping output voltage drops to when being lower than predetermined level voltage regulator circuit by starting first charge pump, when the pumping output voltage is higher than predetermined level, interrupt the operation of first charge pump.
14. the nonvolatile memory of claim 10, wherein first charge pump is a negative charge pump, and the memory erase operation that flash memory array is pointed in this charge pump response is activated.
15. the nonvolatile memory of claim 14, wherein first charge pump further comprises the output stage that is coupling between output node and the predetermined quantity pump stage, this output stage has first threshold voltage, and wherein the pumping output voltage amplitude is approximately equal to supply voltage and multiply by predetermined quantity and deduct first threshold voltage.
16. the nonvolatile memory of claim 10, wherein first charge pump is a positive charge pump, and the storer that flash memory array is pointed in response reads or one of write operation is activated.
17. the nonvolatile memory of claim 16, wherein first charge pump further comprises an output stage that is coupling between output node and the predetermined quantity pump stage, this output stage has first threshold voltage, and wherein the pumping output voltage amplitude is approximately equal to the threshold voltage that [(1+ predetermined magnitude) * supply voltage] deducts output stage.
18. the method that the pumping output voltage is provided, the method comprising the steps of:
The pumping clock signal is to produce the pumping clock signal;
On at least one end of charge pump, receive the pumping clock signal; With the pumping output voltage that provides from charge pump.
19. the method for claim 18 further comprises and regulates the step that the pumping output voltage is substantially equal to predetermined level.
20. the method for claim 18, the step of wherein regulating the pumping output voltage comprises step:
When the pumping output voltage drop to start when being lower than predetermined level charge pump and
When being higher than predetermined level, the rising of pumping output voltage interrupts charge pump operation.
21. the method for claim 18 wherein provides the step of pumping output voltage to comprise to force transistor gate pole tension in the charge pump to be lower than the step of charge pump source gate terminal voltage.
22. a personal computer system comprises:
A bus transfer information;
A processor is coupled to this bus processing instruction; With
A nonvolatile memory is coupled to the instruction that this bus storage of processor is used, and this nonvolatile memory is worked on supply voltage, and this nonvolatile memory comprises
Memory array and
A charge pump is coupled to this memory array, and first charge pump comprises
The pump stage of a predetermined quantity series coupled, at least one pump stage be coupled receive the first pumping clock signal and
An output node is coupled in series to predetermined quantity pump stage one end, and this output node provides the pumping output voltage.
23. the computer system of claim 22, wherein nonvolatile memory comprises that further a clock driver is coupled the pump clock voltage that the reception amplitude is higher than supply voltage, and clock driver is coupled provides the first pumping clock signal at least one pump stage.
24. the computer system of claim 22, wherein nonvolatile memory comprises that further a voltage regulator circuit is coupled to charge pump, this voltage regulator circuit is regulated the pumping output voltage and interrupt the operation of first charge pump when the pumping output voltage is higher than predetermined level by starting first charge pump when being reduced to predetermined level under the pumping output voltage.
25. the computer system of claim 22, wherein charge pump is a negative charge pump, and the memory erase operation that flash memory array is pointed in response is activated.
26. the computer system of claim 22, wherein charge pump is a positive charge pump, and the storer that flash memory array is pointed in response reads or one of write operation is activated.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/161,089 US6160440A (en) | 1998-09-25 | 1998-09-25 | Scaleable charge pump for use with a low voltage power supply |
| US09/161,089 | 1998-09-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1334935A true CN1334935A (en) | 2002-02-06 |
| CN1140955C CN1140955C (en) | 2004-03-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB998137308A Expired - Fee Related CN1140955C (en) | 1998-09-25 | 1999-06-08 | Scalfable charge pump for use with low voltage power supply |
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| Country | Link |
|---|---|
| US (1) | US6160440A (en) |
| EP (1) | EP1151366A4 (en) |
| CN (1) | CN1140955C (en) |
| AU (1) | AU4674699A (en) |
| BR (1) | BR9913910A (en) |
| TW (1) | TW510076B (en) |
| WO (1) | WO2000019289A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423419C (en) * | 2004-04-21 | 2008-10-01 | 友达光电股份有限公司 | D.C voltage converter |
| CN103376812A (en) * | 2012-04-30 | 2013-10-30 | 英飞凌科技股份有限公司 | System and method for a programmable voltage source |
| CN105632559A (en) * | 2014-11-24 | 2016-06-01 | 华邦电子股份有限公司 | Drain regulator for NOR flash memory |
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| DE10050561B4 (en) * | 2000-10-12 | 2005-04-28 | Dialog Semiconductor Gmbh | Integrated circuit with circuit parts with different supply voltage |
| US6628108B1 (en) | 2000-12-22 | 2003-09-30 | Intel Corporation | Method and apparatus to provide a low voltage reference generation |
| US6538494B2 (en) | 2001-03-14 | 2003-03-25 | Micron Technology, Inc. | Pump circuits using flyback effect from integrated inductance |
| US6570807B2 (en) | 2001-08-22 | 2003-05-27 | Micron Technology, Inc. | Intermediate boosted array voltage |
| US6639864B2 (en) * | 2001-12-18 | 2003-10-28 | Intel Corporation | Flash device operating from a power-supply-in-package (PSIP) or from a power supply on chip |
| US6700820B2 (en) | 2002-01-03 | 2004-03-02 | Intel Corporation | Programming non-volatile memory devices |
| ITMI20022268A1 (en) * | 2002-10-25 | 2004-04-26 | Atmel Corp | VARIABLE CHARGE PUMP CIRCUIT WITH DYNAMIC LOAD |
| EP1492218B1 (en) * | 2003-06-24 | 2006-03-29 | STMicroelectronics S.r.l. | Low-consumption regulator for a charge pump voltage generator |
| US7362163B1 (en) | 2004-03-23 | 2008-04-22 | Cypress Semiconductor Corp | Flyback capacitor level shifter feedback regulation for negative pumps |
| US7417488B2 (en) * | 2005-11-04 | 2008-08-26 | Intel Corporation | Regulation circuit for inductive charge pump |
| KR100729353B1 (en) * | 2005-11-22 | 2007-06-15 | 삼성전자주식회사 | Flash memory device with unified regulator/pump structure |
| FR2900290B1 (en) * | 2006-04-19 | 2008-11-21 | Atmel Corp | METHOD AND SYSTEM FOR PROVIDING A CHARGING PUMP FOR LOW VOLTAGE APPLICATIONS |
| JP5331405B2 (en) * | 2008-08-01 | 2013-10-30 | 株式会社東芝 | Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system |
| KR102021415B1 (en) | 2012-12-14 | 2019-09-16 | 에스케이하이닉스 주식회사 | Voltage generator circuit |
| JP5911614B1 (en) | 2015-01-19 | 2016-04-27 | 力晶科技股▲ふん▼有限公司 | Negative reference voltage generator |
| CN107306082B (en) * | 2016-04-18 | 2020-05-22 | 晶门科技（深圳）有限公司 | Charge pump circuit |
| EP3583690A4 (en) | 2017-02-16 | 2020-12-02 | Wispry, Inc. | Charge pump systems, devices, and methods |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| FR2696598B1 (en) * | 1992-10-01 | 1994-11-04 | Sgs Thomson Microelectronics | Charge pump type voltage booster circuit with bootstrap oscillator. |
| US5280420A (en) * | 1992-10-02 | 1994-01-18 | National Semiconductor Corporation | Charge pump which operates on a low voltage power supply |
| US5553030A (en) * | 1993-09-10 | 1996-09-03 | Intel Corporation | Method and apparatus for controlling the output voltage provided by a charge pump circuit |
| US5414669A (en) * | 1993-09-10 | 1995-05-09 | Intel Corporation | Method and apparatus for programming and erasing flash EEPROM memory arrays utilizing a charge pump circuit |
| US5442586A (en) * | 1993-09-10 | 1995-08-15 | Intel Corporation | Method and apparatus for controlling the output current provided by a charge pump circuit |
| US5422586A (en) * | 1993-09-10 | 1995-06-06 | Intel Corporation | Apparatus for a two phase bootstrap charge pump |
| US5438504A (en) * | 1993-10-08 | 1995-08-01 | Sgs-Thomson Microelectronics, Inc. | Voltage multiplier circuits or the like |
| US5553295A (en) * | 1994-03-23 | 1996-09-03 | Intel Corporation | Method and apparatus for regulating the output voltage of negative charge pumps |
| US5532915A (en) * | 1994-03-23 | 1996-07-02 | Intel Corporation | Method and apparatus for providing an ultra low power regulated negative charge pump |
| US7102422B1 (en) * | 1994-04-20 | 2006-09-05 | Nippon Steel Corporation | Semiconductor booster circuit having cascaded MOS transistors |
| JP2718375B2 (en) * | 1994-09-30 | 1998-02-25 | 日本電気株式会社 | Charge pump circuit |
| US5483486A (en) * | 1994-10-19 | 1996-01-09 | Intel Corporation | Charge pump circuit for providing multiple output voltages for flash memory |
| KR0145615B1 (en) * | 1995-03-13 | 1998-12-01 | 김광호 | The driving device of the tft liquid crystal display |
| US5889428A (en) * | 1995-06-06 | 1999-03-30 | Ramtron International Corporation | Low loss, regulated charge pump with integrated ferroelectric capacitors |
| US5602794A (en) * | 1995-09-29 | 1997-02-11 | Intel Corporation | Variable stage charge pump |
| FR2742942B1 (en) * | 1995-12-26 | 1998-01-16 | Sgs Thomson Microelectronics | HIGH VOLTAGE SLOT GENERATOR |
| US5734290A (en) * | 1996-03-15 | 1998-03-31 | National Science Council Of R.O.C. | Charge pumping circuit having cascaded stages receiving two clock signals |
| DE69702256T2 (en) * | 1996-06-24 | 2001-01-18 | Advanced Micro Devices Inc | METHOD FOR A MULTIPLE, BITS PER CELL FLASH EEPROM, MEMORY WITH SIDE PROGRAMMING MODE, AND READING METHOD |
| US5818289A (en) * | 1996-07-18 | 1998-10-06 | Micron Technology, Inc. | Clocking scheme and charge transfer switch for increasing the efficiency of a charge pump or other circuit |
| EP0931379B1 (en) * | 1996-10-10 | 2008-08-06 | Macronix International Co., Ltd. | Triple well charge pump |
| US5798915A (en) * | 1997-01-29 | 1998-08-25 | Microchip Technology Incorporated | Progressive start-up charge pump and method therefor |
-
1998
- 1998-09-25 US US09/161,089 patent/US6160440A/en not_active Expired - Lifetime
-
1999
- 1999-06-08 EP EP99930149A patent/EP1151366A4/en not_active Withdrawn
- 1999-06-08 WO PCT/US1999/012625 patent/WO2000019289A1/en not_active Application Discontinuation
- 1999-06-08 CN CNB998137308A patent/CN1140955C/en not_active Expired - Fee Related
- 1999-06-08 AU AU46746/99A patent/AU4674699A/en not_active Abandoned
- 1999-06-08 BR BR9913910-3A patent/BR9913910A/en not_active Application Discontinuation
- 1999-07-05 TW TW088111378A patent/TW510076B/en active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423419C (en) * | 2004-04-21 | 2008-10-01 | 友达光电股份有限公司 | D.C voltage converter |
| CN103376812A (en) * | 2012-04-30 | 2013-10-30 | 英飞凌科技股份有限公司 | System and method for a programmable voltage source |
| CN103376812B (en) * | 2012-04-30 | 2016-02-24 | 英飞凌科技股份有限公司 | For the system and method for programmable voltage source |
| US9281744B2 (en) | 2012-04-30 | 2016-03-08 | Infineon Technologies Ag | System and method for a programmable voltage source |
| US9743196B2 (en) | 2012-04-30 | 2017-08-22 | Infineon Technologies Ag | System and method for a programmable voltage source |
| CN105632559A (en) * | 2014-11-24 | 2016-06-01 | 华邦电子股份有限公司 | Drain regulator for NOR flash memory |
| CN105632559B (en) * | 2014-11-24 | 2019-06-28 | 华邦电子股份有限公司 | Drain voltage-stablizer |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1151366A4 (en) | 2003-03-05 |
| TW510076B (en) | 2002-11-11 |
| CN1140955C (en) | 2004-03-03 |
| AU4674699A (en) | 2000-04-17 |
| WO2000019289A1 (en) | 2000-04-06 |
| BR9913910A (en) | 2001-07-03 |
| EP1151366A1 (en) | 2001-11-07 |
| US6160440A (en) | 2000-12-12 |
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Legal Events
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| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040303 Termination date: 20180608 |