CN1325205A - Sync sequence key word detection method - Google Patents

Abstract

The present invention discloses a synchronous stream keyword detection method, which is characterized by that the received data is shifted into shift register, the data in said shift register can be compared with UW word to be detected bit-by-bit, and transferred into full adder, after the comparison is completed, the result obtained from full adder is compared with threshold value, when said result is greater than threshold value, it represents that the UW word is detected, it the UV word can be detected for continuous three times, it can judge that the synchronization is searched, it the UW word is not detected for continuous three times and being in synchronous state, it can judge that it is come into the state of loss of synchronism, so that it can allow of more than a bit error, and possess the capability of distinguishing true synchronization from false one and resisting interference.

Description

A kind of sync sequence key word detection method

The present invention relates to the synchronizing sequence detection technique in the digital communication system, relate more specifically to the implementation method that the keyword (Unique Word is hereinafter to be referred as the UW word) in the personal hand-held communication system (hereinafter to be referred as the PHS system) detects.

By detecting the UW word in the receiving sequence, can locate the tram of each gap information data, to extract data like clockwork.Detect by the UW word simultaneously, realize that PHS base station Kongzhong is synchronous, so the UW word in the PHS system detects extremely important.

The PHS system with TDMA/TDD (TDMA/TDD) as the multiple access multiplexing mode, its frame length is 5ms, every frame comprises 8 time slots, preceding four time slot T1, T2, T3 and T4 are for sending out time slot, four time slot R1, R2, R3 and R4 are the time receiving crack in the back, the time slot type of PHS system comprises: control physical slot by time (Control Physical Slot), communication physical slot by time (Communication Physical Slot), synchronization burst (Synchronization Burst is hereinafter to be referred as synchronous Burst).It is as follows that the PHS system utilizes different UW words to distinguish above-mentioned different time-gap:

1) control physical slot by time, Burst synchronously:

Up: 0,110 1,011 1,000 1,001 1,001 1,010 1,111 0,000 32

Descending: 0,101 0,000 1,110 1,111 0,010 1,001 1,001 0,011 32

2) communication physical slot by time (Burst exception synchronously)

Up: 1,110 0,001 0,100 1,001 16

Descending; 0,011 1,101 0,100 1,100 16

When receiving the UW word, allow wrong one at most.

Detect for the UW word of PHS system, at present common have following two kinds of methods:

1) compares a full addition by the sign indicating number displacement

The basic principle of this method is to adjust the phase place of the local frame swynchronization code of receiving end, makes it to aim at the frame swynchronization code in total letter sign indicating number of receiving.But the shortcoming that adopts this method is clearly: received frame synchronizing sequence word length is immutable, and does not allow to have in the synchronizing sequence situation more than a bit-errors to take place.

2) mode of setting up the UW tables of data is searched for the UW word.

The ingenious PHS system that utilizes of this method allows UW word wrong one feature at most, can capture the UW word in the receiving sequence rapidly.But the method lacks flexibility, and when the UW word changes, when perhaps allowing more than one of wrong figure place, the length of table increases with wrong figure place is linear.Moreover its synchronous ability of not distinguishing the true from the false can not be anti-interference after entering synchronously.

In the patent document that retrieves at present, patent specification WO9836519A1 and patent specification US4748623 also disclose similar scheme, but the shortcoming that said method is equally also arranged is immutable and do not allow that situation generation more than a bit-errors etc. is arranged in the synchronizing sequence as received frame synchronizing sequence word length.

The objective of the invention is to overcome the shortcoming of said method, a kind of sync sequence key word detection method is provided,,, change the length and the synchronization character of synchronizing sequence by the parameter setting to detect the UW word that receives in the aerial sequence.Allow to have in the synchronizing sequence generation simultaneously, and have the synchronous and anti-false interference performance that loses of distinguishing the true from the false more than a bit-errors.

For finishing above-mentioned task, the present invention proposes a kind of UW word detection method, wherein RXD receives data, SYNC is the synchronizing sequence that will detect, WIDTH is the synchronizing sequence bit width, and THRESH is a figure place of judging that sequence meets synchronously, and SYNC_GET catches successfully sign synchronously, Times_Caught is the number of times that is consecutively detected the UW word, and Times_Lost is the number of times that does not detect the UW word continuously.

This method may further comprise the steps

1) initialization is provided with SYNC_GET=0, Times_Caught=0 and Times_Lost=0;

2) wait for RXD sampling clock rising edge, if rising edge arrives, then change next step over to, otherwise wait for;

3) RXD is moved into the shift register SHIFT that width is WIDTH;

4) zero clearing counter I and accumulator Acc;

5) compare I bit shift register SHIFT[I] and I bit synchronization word SYNC[I], then continue if equate; Then do not change step 7) over to if do not wait;

6) accumulator Acc adds 1;

7) compare counter I and synchronization character width W IDTH, if I 〉=WIDTH changes 9 over to), otherwise continue;

8) counter I adds 1, changes 5 over to);

9) compare accumulator Acc and THRESH as a result,, otherwise change step 13) over to if Acc 〉=THRESH continues;

10) as if SYNC_GET=0, then Times_Caught=Times_Caught+1 continues; Otherwise Times_Caught=0 changes step 2 over to);

11) true and false synchronous differentiation;

12) if very synchronous, put SYNC_GET=1, Times_Caught=0 changes step 2 over to), if synchronously false, then directly change step 2 over to);

13) as if SYNC_GET=1, then Times_Lost=Times_Lost+1 continues; Otherwise Times_Lost=0 changes step 2 over to);

14) carrying out true and false step-out differentiates;

15) if true step-out is put SYNC_GET=0, Times_Lost=0 changes step 2 over to); If false step-out then directly changes step 2 over to).

Wherein, the true and false synchronous distinguishing rule of step 11) is, when SYNC_GET=0, if continuous three times detect the UW word, promptly can be considered very synchronous, as above in the step if Times_Caught=3 is very synchronous.

The true and false step-out distinguishing rule of step 14) is, when SYNC_GET=1, do not detect the UW word continuous three times, then is considered as true step-out, as above in the step if Times_Lost=3 is true step-out.

By such scheme as seen, the present invention realizes that the method that the UW word detects has tangible advantage, only need to revise parameter synchronization sequence bit width W IDTH, the synchronizing sequence SYNC that will detect, judge the figure place THRESH that sequence meets synchronously, can detect any bit width and any UW word, and allow receiving sequence that appearance wrong more than is arranged, and this method has distinguishes the true from the false synchronously and anti-false step-out interference performance, use very flexible, have generality, can be adapted to the application that various synchronizing sequences detect.

The invention will be further described below in conjunction with drawings and Examples.

Fig. 1 is the frame structure schematic diagram of PHS system.

Fig. 2 is the flow chart of the method for the invention.

Fig. 3 is the flow chart as the embodiment of the invention.

PHS system frame structure shown in Fig. 1, its frame length are 5ms, and every frame comprises 8 time slots, and preceding four time slot T1, T2, T3 and T4 are for sending out time slot, and back four time slot R1, R2, R3 and R4 are the time receiving crack.

Fig. 2 is the flow chart of the method for the invention.Basic ideas of the present invention as can be seen are from this flow chart, to receive data RXD and move into shift register SHIFT, compare by turn with UW word SYNC to be detected then, comparative result is delivered to full adder Acc, again full adder Acc result and threshold value THRESH are compared, if full adder Acc result is not less than threshold value THRESH and then represents to detect the UW word, if the continuous UW word that detects for three times then can be differentiated and searched synchronously; If full adder Acc result then represents not detect the UW word less than threshold value THRESH, current when being in synchronous regime, if continuous do not detect the UW word three times and, then can judge to have entered desynchronizing state.

Below in conjunction with Fig. 3 embodiments of the invention are described.

If PHS base station down Common Control Channel (Common Control Channel, abbreviation CCH) the UW word length WIDTH=32 of time slot and SYNC time slot, the UW word is SYNC=H " 50EF2993 ", criterion is synchronously: UW detects and allows to occur one mistake at most in the receiving sequence, then THRESH 〉=31 make THRESH=31 now.Receive data and be moved into 32 bit shift register, wherein the clock of shift register is for receiving the data sampling clock, with 32 of shift register output by turn with UW word corresponding positions to be detected relatively (as the former 0 to 0 of the latter, 1 to 1, up to 31 to 31), if equate that then comparative result is 1, otherwise be 0.32 comparative results are delivered to full adder, again full adder result and threshold value 31 are compared,, represent that then this detects the UW word, otherwise represent that this does not detect the UW word if full adder Acc result is not less than threshold value 31; Detect the UW word and also need pass through true and false synchronousing distinguishing circuit, if continuous three times detect the UW word, expression has searched synchronously, otherwise is considered as the false search that continues synchronously; If this does not detect the UW word and the current synchronous regime that has been in, then need the result of more continuous three detection UW words, if continuous three times all do not detect the UW word, then be considered as entering desynchronizing state, must search for again synchronously, otherwise be considered as false step-out.

Except the UW word detection of PHS system, method set forth in the present invention also is applicable to other synchronizing sequence testing circuits, has very strong adaptability.

Claims (3)

1, a kind of sync sequence key word detection method, RXD receives data, SYNC is the synchronizing sequence that will detect, WIDTH is the synchronizing sequence bit width, THRESH is a figure place of judging that sequence meets synchronously, and SYNC_GET catches successfully sign synchronously, and Times_Caught is the number of times that is consecutively detected the UW word, Times_Lost is the number of times that does not detect the UW word continuously, it is characterized in that this method may further comprise the steps:

1) initialization is provided with SYNC_GET=0, Times_Caught=0 and Times_Lost=0;

2) wait for RXD sampling clock rising edge, if rising edge arrives, then change next step over to, otherwise wait for;

3) RXD is moved into the shift register SHIFT that width is WIDTH;

4) zero clearing counter I and accumulator Acc;

5) compare I bit shift register SHIFT[I] and I bit synchronization word SYNC[I], then continue if equate

Continuous; Then do not change step 7) over to if do not wait;

6) accumulator Acc adds 1;

7) compare counter I and synchronization character width W IDTH, if I 〉=WIDTH changes 9 over to), otherwise continue

Continuous;

8) counter I adds 1, changes 5 over to);

9) compare accumulator Acc and THRESH as a result,, otherwise change over to if Acc 〉=THRESH continues

Step 13);

10) as if SYNC_GET=0, then Times_Caught=Times_Caught+1 continues;

Otherwise Times_Caught=0 changes step 2 over to);

11) carry out true and false synchronous differentiation;

12) if very synchronous, put SYNC_GET=1, Times_Caught=0 changes step 2 over to),

If synchronously false, then directly change step 2 over to);

13) as if SYNC_GET=1, then Times_Lost=Times_Lost+1 continues; Otherwise

Times_Lost=0 changes step 2 over to);

14) carrying out true and false step-out differentiates;

15) if true step-out is put SYNC_GET=0, Times_Lost=0 changes step 2 over to); If

False step-out then directly changes step 2 over to).

2, according to the described sync sequence key word detection method of claim 1, it is characterized in that: the true and false synchronous differentiation process of step 11) is,

1) continuous detecting UW word is three times;

2) if detect comparative result SYNC_COMP=1 for three times, promptly be considered as very synchronously, put

SYNC_GET=1；

3) if three times are detected comparative result SYNC_COMP=0, promptly be considered as vacation synchronously, put

SYNC_GET=0。

3, according to the described sync sequence key word detection method of claim 1, it is characterized in that: the differentiation process of the true and false step-out of step 14) is, when SYNC_GET=1,

1) continuous detecting UW word is three times;

2) if three times are detected comparative result SYNC_COMP=0, then be considered as true step-out, put

SYNC_GET=0；

3) if three times are detected comparative result SYNC_COMP=1, then be considered as false step-out, SYNC_GET

Constant.

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